Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/2/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12,323,160. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims recite the same subject matter with colorable differences. For instance,
Claim 1 of the present application recites:
An analog filter, comprising: a first time-encoding machine (TEM); and a first delay element whereas claim 1 of the patent application recites an analog feedback comb filter. Both sets recite a filter, however, they are different configurations, function and properties but it is known that all filters are designed to remove unwanted signal. Hence, the limitation of claim 1 is quasi similar to claim 1 of patent 12,323,160.
Claim 2 of the present application recites
The analog filter of claim 1, wherein the first TEM is configured to receive an input signal and generate a time encoded signal. This limitation is identical to claim 2 of the patent 12,323,160.
Claim 3 of the present application recites
The analog filter of claim[[s]] 1 or 2, wherein the first delay element comprises one or more first inverters connected in series. This limitation is identical to claim 3 of the patent 12,323,160.
Claim 4 of the present application recites
The analog filter of claim 3, wherein the first delay element is configured to receive a supply voltage to control the delay of the one or more first inverters. This limitation is identical to claim 4 of the patent 12,323,160.
Claim 5 of the present application recites:
The analog filter of claim 3, further comprising one or more delay-locked loops (DLL) configured to generate a supply voltage for the one or more first inverters of the first delay element. This limitation is identical to claim 5 of the patent 12,323,160.
Claim 6 of the present application recites:
The analog filter of claim 4, wherein the one or more DLLs comprise a plurality of DLLs each configured to generate a respective reference voltage, the analog filter comprising control circuitry configured to cycle between each of the respective reference voltages to be provided as the supply voltage for the one or more first inverters of the first delay element. This limitation is identical to claim 6 of the patent 12,323,160.
Claim 7 of the present application recites:
The analog filter of claim[[s]] 4, wherein the one or more DLLs each comprise a delay line. This limitation is identical to claim 7 of the patent 12,323,160.
Claim 8 of the present application recites:
The analog filter of claim 6, wherein each delay line comprises one or more second inverters connected in series. This limitation is identical to claim 8 of the patent 12,323,160.
Claim 9 of the present application recites:
The analog filter of claim 6, wherein the delay line comprises the one or more first inverters of the first delay element. This limitation is identical to claim 9 of the patent 12,323,160.
Claim 10 of the present application recites:
The analog filter of claim 6, wherein the delay line is switchable between comprising one or more second inverters connected in series and comprising the one or more first inverters of the first delay element. This limitation is identical to claim 10 of the patent 12,323,160.
Claim 11 of the present application recites:
The analog filter of claim 9, further comprising control circuitry configured to periodically switch the delay line between comprising the one or more second inverters and comprising the one or more first inverters of the first delay element. This limitation is identical to claim 11 of the patent 12,323,160.
Claim 12 of the present application recites:
The analog filter of claim 9, wherein the first delay element is switchable between comprising one or more second inverters connected in series and comprising the one or more first inverters of the first delay element. This limitation is identical to claim 12 of the patent 12,323,160.
Claim 13 of the present application recites:
The analog filter of claim 6, wherein the delay line is a digital delay line comprising a plurality of second inverters, wherein the DLL comprises: DLL control circuitry configured to control the number of the second inverters provided in the delay line. This limitation is identical to claim 13 of the patent 12,323,160.
Claim 14 of the present application recites:
The analog filter of claim 3, wherein the delay element is a digital delay element. This limitation is identical to claim 14 of the patent 12,323,160.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cooper (US 4,703,355).
With regard to claim 1, Cooper discloses:
An analog filter (65 Fig. 5), comprising: a first time-encoding machine (TEM) (17 Fig.3); and a first delay element (18 Fig.3).
With regard to claim 2, Cooper discloses:
2. (Original) The analog filter of claim 1, wherein the first TEM is configured to receive an input signal and generate a time encoded signal. (17 Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cooper (US 4,703,355) in view of Hernandez (US 2009/0207060).
With regard to claim 3, Cooper fails to teach
The analog filter of claim 2, wherein the first delay element comprises one or more first inverters connected in series.
Hernandez teaches:
The analog filter of claim 3, wherein the first delay element is configured to receive a supply voltage to control the delay of the one or more first inverters.
A delay line may be a cascade logic gates inverters (Para 29). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing data of the application to have applied the teaching of Hernandez in the filter of Cooper for the benefit to better configure the delay in the analog circuit.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cooper (US 4,703) in view of Chen (US 2015/0215110).
With regard to claim 4 Cooper fails to discloses:
The analog filter of claim 3, wherein the first delay element is configured to receive a supply voltage to control the delay of the one or more first inverters.
Chen discloses:
A reference voltage that is supplied to a delay inverter (Fig. 5). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing data of the application to have applied the teaching of Chen in the filter of Cooper for the benefit to better synchronize and improve the operation of the system.
With regard to claim 5, Cooper fails to teach:
5. (Original) The analog filter of claim 3, further comprising one or more delay-locked loops (DLL) configured to generate a supply voltage for the one or more first inverters of the first delay element.
Chen discloses
A delay locked loop that generates a supply voltage to the one or more inverters (404 Figs 4-5). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing data of the application to have applied the teaching of Chen in the filter of Cooper for the benefit to better synchronize and improve the operation of the system.
With regard to claim 7 Cooper fails to teach:
7. (Currently Amended) The analog filter of claim 4, wherein the one or more DLLs: each comprises a delay line.
Chen discloses this limitation in Fig. 4. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing data of the application to have applied the teaching of Chen in the filter of Cooper for the benefit to better synchronize and improve the operation of the system.
With regard to claim 8 Cooper fails to teach:
The analog filter of claim 6, wherein each delay line comprises one or more second inverters connected in series.
Cheng discloses this limitation in Fig. 4. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing data of the application to have applied the teaching of Chen in the filter of Cooper for the benefit to better synchronize and improve the operation of the system.
With regard to claim 9 Cooper fails to teach:
The analog filter of claim 6, wherein the delay line comprises the one or more first inverters of the first delay element.
Chen discloses this limitation in Fig. 4.Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing data of the application to have applied the teaching of Chen in the filter of Cooper for the benefit to better synchronize and improve the operation of the system.
With regard to claim 14, Cooper discloses:
The analog filter of claim 3, wherein the delay element is a digital delay element (Col. 4, line 21).
With regard to claim 18, Cooper discloses:
The analog filter of claim 1, wherein the analog filter comprises a feedforward filter having a feedforward loop, wherein the delay element is provided in the feedforward loop (fig.4).
19. (Original) The analog filter of claim 18, wherein the feedforward filter is a finite impulse response (FIR) filter.
20. (Original) The analog filter of claim 1, wherein the analog filter comprises a biquadratic filter having a first feedback look comprising the first delay element, a second feedback loop comprising the first delay element and a second delay element, a first feedforward loop comprising the first delay element, a second feedforward loop comprising the second delay element and a third delay element.
With regard to claim 21 Cooper discloses:
21. An electronic device comprising the analog filter of any one of the preceding according to claim (Filter 65 Fig. 5).
With regard to claim 22, Cooper discloses:
The electronic device of claim 21, wherein the device comprises one of a mobile computing device, a laptop computer, a tablet computer, a games console, a remote-control device, a home automation controller or a domestic appliance, a toy, a robot, an audio player, a video player, or a mobile telephone, and a smartphone (col. 3 line 1).
Allowable Subject Matter
Claims 15-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In addition, claims 6, 10-13 are rejected under double patenting.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
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