DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-22 are presented for examination.
Abstract
3. The abstract of the disclosure is acceptable for examination purposes.
Oath Declaration
4. The Oath complies with all the requirements set forth in MPEP 602 and therefore is accepted.
Drawings
5. The drawings received on 05/02/2025 are acceptable for examination purposes.
Priority
6. Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C.119 (a)-(d) for Korean Patent Application No. KR10-2022-0077009, filed on June 23, 2015.
Information Disclosure Statement
7. The references listed in the information disclosure statement (IDS) submitted on 05/02/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
8. Claims 1-22 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
In regards to claim 1:
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, See MPEP 2106.03. The claim recites a transmitting device and, therefore, is a machine or manufacture, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes. MPEP 2106.04. The claims recites the limitations of “encode a first burst, a second burst, a third burst, and a fourth burst to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and a fourth encoded symbol, respectively; an inversion determination circuit configured to generate a first inversion signal based on a fourth transmitting symbol, to generate a second inversion signal based on the first burst, to generate a third inversion signal based on the second burst, and to generate a fourth inversion signal based on the third burst,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO. See MPEP 2106.04(d). The additional limitations of “generate a first transmitting symbol based on the first encoded symbol and the first inversion signal, to generate a second transmitting symbol based on the second encoded symbol and the second inversion signal, to generate a third transmitting symbol based on the third encoded symbol and the third inversion signal, and to generate the fourth transmitting symbol based on the fourth encoded symbol and the fourth inversion signal” do not integrate the abstract idea into a practical application because the claim recites insignificant extra-solution activity as mere pre-solution outputting of data as identified in MPEP 2106.05(g) and does not provide integration into a practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO. See MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “A transmitting device,” “encoding block,” “an inversion determination circuit,” and “an inversion block” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See the prior arts Seol et al. (US 2022/0294476 A1), US Seol et al. (US 2022/0294554 A1) and Sudhakaran et al. (US 10491238 B2) teach well known elements. Therefore, the claim is not patent eligible.
In regards to claim 8:
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, See MPEP 2106.03. The claim recites a series of steps and, therefore, is a process, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes. MPEP 2106.04. The claims recites the limitations of “dividing output data into a first burst, a second burst, a third burst, and a fourth burst; determining whether a bit with a specific number of each of a fourth transmitting symbol, the first burst, the second burst, and the third burst is a first logic level; encoding the first burst, the second burst, the third burst, and the fourth burst to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and the fourth encoded symbol, respectively; selectively inverting the first encoded symbol, the second encoded symbol, the third encoded symbol, and the fourth encoded symbol based on a result of the determination to generate a first transmitting symbol, a second transmitting symbol, a third transmitting symbol, and the fourth transmitting symbol,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO. See MPEP 2106.04(d). The additional limitations of “transmitting a 4-level pulse amplitude modulation (PAM-4) signal based on the first transmitting symbol, the second transmitting symbol, the third transmitting symbol, and the fourth transmitting symbol” do not integrate the abstract idea into a practical application because the claim recites insignificant extra-solution activity as mere pre-solution outputting of data as identified in MPEP 2106.05(g) and does not provide integration into a practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO. See MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “A transmitting and receiving” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See the prior arts Seol et al. (US 2022/0294476 A1), US Seol et al. (US 2022/0294554 A1) and Sudhakaran et al. (US 10491238 B2) teach well known elements. Therefore, the claim is not patent eligible.
In regards to claim 14:
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, See MPEP 2106.03. The claim recites A transmitting and receiving system and, therefore, is a machine or manufacture, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes. MPEP 2106.04. The claims recites the limitations of “a symbol encoding circuit configured: to divide output data into a first burst, a second burst, a third burst, and a fourth burst; to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and a fourth encoded symbol by encoding the first to fourth bursts, respectively; to generate a first transmitting symbol by selectively inverting the first encoded symbol based on a fourth transmitting symbol; to generate a second transmitting symbol by selectively inverting the second encoded symbol based on the first burst; to generate a third transmitting symbol by selectively inverting the third encoded symbol based on the second burst; and to generate a fourth transmitting symbol by selectively inverting the fourth encoded symbols based on the third burst,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO. See MPEP 2106.04(d). The additional limitations of “a transmitting device configured to transmit a 4-level pulse amplitude modulation (PAM-4) signal; and a receiving device configured to receive the PAM-4 signal,--- transmit the PAM-4 signal based on the first to fourth transmitting symbols” do not integrate the abstract idea into a practical application because the claim recites insignificant extra-solution activity as mere pre-solution outputting of data as identified in MPEP 2106.05(g) and does not provide integration into a practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO. See MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “A transmitting and receiving system,” “a transmitting device,” “receiving device,” “symbol encoding circuit,” and “transmitting circuit” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See the prior arts Seol et al. (US 2022/0294476 A1), US Seol et al. (US 2022/0294554 A1) and Sudhakaran et al. (US 10491238 B2) teach well known elements. Therefore, the claim is not patent eligible.
Dependent claims 2-7, 9-13, and 15-22 are extended elements of the abstract idea of the independent claims and the claims are abstract in nature falling withing Mental Processes. The dependent claims do not add any meaningful limits to the abstract idea to improve the technology or the computer component and fails to add significantly more than the abstracts idea. Therefore, the dependent claims 1-22 are not patent eligible.
Double Patenting
9. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
10. Claims 1, 4-14, and 16-22 are non-provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5-16, and 18-23 of patent application No: 12,316,451 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 4-14, and 16-22 of the present application are substantially equivalent to claims 1, 5-16, and 18-23 of the reference application as shown in the chart and explanation below.
Instant Application No. 19/197,610
U.S Patent No. 12,316,451
Claim 1.
A transmitting device comprising: an encoding block configured to encode a first burst, a second burst, a third burst, and a fourth burst to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and a fourth encoded symbol, respectively;
an inversion determination circuit configured to generate a first inversion signal based on a fourth transmitting symbol, to generate a second inversion signal based on the first burst, to generate a third inversion signal based on the second burst, and to generate a fourth inversion signal based on the third burst;
and an inversion block configured to generate a first transmitting symbol based on the first encoded symbol and the first inversion signal, to generate a second transmitting symbol based on the second encoded symbol and the second inversion signal, to generate a third transmitting symbol based on the third encoded symbol and the third inversion signal, and to generate the fourth transmitting symbol based on the fourth encoded symbol and the fourth inversion signal.
Claim 1.
A transmitting device comprising: an encoding block configured to receive the first burst and a second burst, configured to encode the first burst to generate a first encoded symbol, and configured to encode the second burst to generate a second encoded symbol;
an inversion determination circuit configured to receive a bit with a specific sequence number of a second transmitting symbol and a bit with the specific sequence number of a first burst, configured to enable and generate a first inversion signal according to a logic level of the bit with the specific sequence number of the second transmitting symbol, and configured to enable and generate a second inversion signal according to a logic level of the bit with the specific sequence number of the first burst;
and an inversion block configured to generate a first transmitting symbol by selectively inverting the first encoded symbol based on whether the first inversion signal is enabled, and to generate the second transmitting symbol by selectively inverting the second encoded symbol based on whether the second inversion signal is enabled.
Claim 4.
The transmitting device according to claim 1, wherein the encoding block is configured to generate the first to fourth encoded symbols by encoding the first to fourth bursts so that a maximum transition is avoided, and to substantially maintain a logic level of a bit with a specific sequence number of each of the first to fourth encoded symbols to be substantially identical to a logic level of a bit with the specific sequence number of each of the first to fourth bursts.
Claim 5.
The transmitting device according to claim 1, wherein the encoding block generates the first and second encoded symbols by encoding the first and second bursts so that a maximum transition is avoided, and substantially maintains a logic level of a bit with a specific sequence number of each of the first and second encoded symbols to be substantially identical to a logic level of a bit with a specific sequence number of each of the first and second bursts.
Claim 5.
The transmitting device according to claim 1, further comprising: a symbol interleaving circuit configured to generate an interleaved symbol based on at least one bit of each of the first to fourth bursts, wherein the encoding block is configured to generate the first to fourth encoded symbols by encoding remaining bits of the first to fourth bursts, respectively.
Claim 6:
The transmitting device according to claim 1, further comprising: a symbol interleaving circuit configured to generate an interleaved symbol on the basis of at least one bit of each of the first and second bursts, wherein the encoding block generates the first and second encoded symbols by encoding remaining bits of the first and second bursts, respectively.
Claim 6.
The transmitting device according to claim 1, further comprising: a transmitting circuit configured to transmit a 4-level pulse amplitude modulation (PAM-4) signal through a transmission signal bus based on the first to fourth transmitting symbols.
Claim 7.
The transmitting device according to claim 1, further comprising: a transmitting circuit configured to transmit a 4-level pulse amplitude modulation (PAM-4) signal through a transmission signal bus on the basis of the first and second transmitting symbols.
Claim 7.
The transmitting device according to claim 6, further comprising: a serializer configured to generate a plurality of unit symbols each including one most significant bit and one least significant bit by serializing the first and second transmitting symbols; and a transmission driver configured to drive a transmission signal bus by a PAM-4 signal on the basis of the plurality of unit symbols.
Claim 8.
The transmitting device according to claim 7, further comprising: a serializer configured to generate a plurality of unit symbols each including one most significant bit and one least significant bit by serializing the first and second transmitting symbols; and a transmission driver configured to drive a transmission signal bus by a PAM-4 signal on the basis of the plurality of unit symbols.
Claim 8.
A transmitting and receiving method comprising: dividing output data into a first burst, a second burst, a third burst, and a fourth burst; determining whether a bit with a specific number of each of a fourth transmitting symbol, the first burst, the second burst, and the third burst is a first logic level;
encoding the first burst, the second burst, the third burst, and the fourth burst to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and the fourth encoded symbol, respectively; selectively inverting the first encoded symbol, the second encoded symbol, the third encoded symbol, and the fourth encoded symbol based on a result of the determination to generate a first transmitting symbol, a second transmitting symbol, a third transmitting symbol, and the fourth transmitting symbol, respectively;
and transmitting a 4-level pulse amplitude modulation (PAM-4) signal based on the first transmitting symbol, the second transmitting symbol, the third transmitting symbol, and the fourth transmitting symbol.
Claim 9.
A transmitting and receiving method comprising: dividing output data into a first burst and a second burst; determining whether a bit with a specific sequence number of a second transmitting symbol has a first logic level and a bit with a specific sequence number of a first burst has the first logic level;
generating a first encoded symbol by encoding the first burst and generating a second encoded symbol by encoding the second burst, so that a maximum transition is avoided; generating a first transmitting symbol and the second transmitting symbol by selectively inverting the first encoded symbol and the second encoded symbol on the basis of results of the determination;
and transmitting a 4-level pulse amplitude modulation (PAM-4) signal on the basis of the first transmitting symbol and the second transmitting symbol.
Claim 9.
The transmitting and receiving method according to claim 8, wherein a logic level of the bit with the specific sequence number of each of the first to fourth bursts matches a logic level of a bit with the specific sequence number of each of the first to fourth of encoded symbols.
Claim 10.
The transmitting and receiving method according to claim 9, wherein a logic level of the bit with the specific sequence number of each of the plurality of bursts matches a logic level of a bit with a specific sequence number of each of the plurality of encoded symbols.
Claim 10.
The transmitting and receiving method according to claim 8, further comprising: before the generating the first to fourth encoded symbols, providing at least one bit of the plurality of bursts as an interleaved symbol, wherein, in the generating the first to fourth encoded symbols, the first to fourth encoded symbols are generated by encoding remaining bits of the first to fourth bursts, respectively.
Claim 11.
The transmitting and receiving method according to claim 9, further comprising: before the generating the plurality of encoded symbols, providing at least one bit of the plurality of bursts as an interleaved symbol, wherein, in the generating the plurality of encoded symbols, the plurality of encoded symbols are generated by encoding remaining bits of the plurality of bursts, respectively.
Claim 11.
The transmitting and receiving method according to claim 10, further comprising: transmitting a PAM-4 signal based on the interleaved symbol at the same time or after the transmitting the PAM-4 signal.
Claim 12.
The transmitting and receiving method according to claim 11, further comprising: transmitting a PAM-4 signal on the basis of the interleaved symbol at the same time or after the transmitting the PAM-4 signal.
Claim 12.
The transmitting and receiving method according to claim 8, further comprising: receiving the PAM-4 signal and generating a first received symbol, a second received symbol, a third received symbol, and a fourth received symbol; determining whether a bit with the specific sequence number of each of the first to fourth received symbols has the first logic level and generating a first decoded symbol, a second decoded symbol, a third decoded symbol, and a fourth decoded symbol by selectively inverting the first to fourth received symbols according to a result of the determination; and generating a first decoded burst, a second decoded burst, a third decoded burst, and a fourth decoded burst by decoding the first to fourth decoded symbols, respectively.
Claim 13.
The transmitting and receiving method according to claim 9, further comprising: receiving the PAM-4 signal and generating a plurality of received symbols; determining whether a bit with a specific sequence number of the previously received symbol has a first logic level and generating a plurality of decoded symbols by selectively inverting the plurality of received symbols according to a result of the determination; and generating a plurality of decoded bursts by decoding the plurality of decoded symbols.
Claim 13.
The transmitting and receiving method according to claim 12, further comprising: receiving an interleaved symbol at the same time or after the generating the first to fourth received symbols; and generating input data by combining the first to fourth decoded bursts and the interleaved symbol.
Claim 14.
The transmitting and receiving method according to claim 13, further comprising: receiving an interleaved symbol at the same time or after the generating the plurality of received symbols; and generating input data by combining the plurality of decoded bursts and the interleaved symbol.
Claim 14.
A transmitting and receiving system comprising: a transmitting device configured to transmit a 4-level pulse amplitude modulation (PAM-4) signal; and a receiving device configured to receive the PAM-4 signal, wherein the transmitting device comprises:
a symbol encoding circuit configured: to divide output data into a first burst, a second burst, a third burst, and a fourth burst; to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and a fourth encoded symbol by encoding the first to fourth bursts, respectively;
to generate a first transmitting symbol by selectively inverting the first encoded symbol based on a fourth transmitting symbol; to generate a second transmitting symbol by selectively inverting the second encoded symbol based on the first burst; to generate a third transmitting symbol by selectively inverting the third encoded symbol based on the second burst; and to generate a fourth transmitting symbol by selectively inverting the fourth encoded symbols based on the third burst,
and a transmitting circuit configured to transmit the PAM-4 signal based on the first to fourth transmitting symbols.
Claim 15.
A transmitting and receiving system comprising: a transmitting device configured to transmit a 4-level pulse amplitude modulation (PAM-4) signal; and a receiving device configured to receive the PAM-4 signal, wherein the transmitting device comprises:
a symbol encoding circuit configured to divide output data into a first burst and a second burst, to generate a first encoded symbol by encoding the first burst, and to generate a second encoded symbol by encoding the second burst, to selectively invert the first encoded symbol to generate a first transmitting symbol by determining whether a logic level of a bit with a specific sequence number of a second transmitting symbol is 1, and to selectively invert the second encoded symbol to generate the second transmitting symbol by determining whether a logic level of a bit with a specific sequence number of the first burst is 1;
and a transmitting circuit configured to transmit the PAM-4 signal on the basis of the first and second transmitting symbols.
Claim 16.
The transmitting and receiving system according to claim 15, wherein the bit with the specific sequence number is a last most significant bit of each of the first to third bursts and the fourth transmitting symbol.
Claim 16.
The transmitting and receiving system according to claim 15, wherein the bit with the specific sequence number is a last most significant bit of each of the second transmitting symbol and the first burst.
Claim 17.
The transmitting and receiving system according to claim 14, wherein the symbol encoding circuit comprises: an inversion determination circuit configured to generate a first inversion signal based on the fourth transmitting symbol, to generate a second inversion signal based on the first burst, to generate a third inversion signal based on the second burst, and to generate a fourth inversion signal based on the third burst; a first encoder configured to generate the first encoded symbol by encoding the first burst;
a second encoder configured to generate the second encoded symbol by encoding the second burst; a third encoder configured to generate the third encoded symbol by encoding the third burst; a fourth encoder configured to generate the fourth encoded symbol by encoding the fourth burst; a first inverting circuit configured to generate the first transmitting symbol by selectively inverting the first encoded symbol based on the first inversion signal;
a second inverting circuit configured to generate the second transmitting symbol by selectively inverting the second encoded symbol based on the second inversion signal; a third inverting circuit configured to generate the third transmitting symbol by selectively inverting the third encoded symbol based on the third inversion signal; and a fourth inverting circuit configured to generate the fourth transmitting symbol by selectively inverting the fourth encoded symbol based on the fourth inversion signal.
Claim 18.
The transmitting and receiving system according to claim 15, wherein the symbol encoding circuit comprises: an inversion determination circuit configured to generate a first inversion signal on the basis of the logic level of the bit with the specific sequence number of the second transmitting symbol, and to generate a second inversion signal on the basis of the logic level of the bit with the specific sequence number of the first burst; a first encoder configured to generate the first encoded symbol by encoding the first burst;
a second encoder configured to generate the second encoded symbol by encoding the second burst; a first inverting circuit configured to generate the first transmitting symbol by selectively inverting the first encoded symbol on the basis of the first inversion signal;
and a second inverting circuit configured to generate the second transmitting symbol by selectively inverting the second encoded symbol on the basis of the second inversion signal.
Claim 18.
The transmitting and receiving system according to claim 17, further comprising: a symbol interleaving circuit configured to extract at least one bit of each of the first to second bursts, and to generate an interleaved symbol based on the extracted bits, wherein the first encoder is configured to generate the first encoded symbol by encoding remaining bits of the first burst, the second encoder is configured to generate the second encoded symbol by encoding remaining bits of the second burst, the third encoder is configured to generate the third encoded symbol by encoding remaining bits of the third burst, and the fourth encoder is configured to generate the fourth encoded symbol by encoding remaining bits of the fourth burst.
Claim 19.
The transmitting and receiving system according to claim 18, further comprising: a symbol interleaving circuit configured to extract at least one bit of the first burst and at least one bit of the second burst, and to generate an interleaved symbol on the basis of the extracted bits, wherein the first encoder generates the first encoded symbol by encoding remaining bits of the first burst, and the second encoder generates the second encoded symbol by encoding remaining bits of the second burst.
Claim 19.
The transmitting and receiving system according to claim 14, wherein the transmitting circuit comprises: a serializer configured to generate a plurality of unit symbols each including one most significant bit and one least significant bit by serializing the first to fourth transmitting symbols; and a transmission driver configured to drive a transmission signal bus by a PAM-4 signal on the basis of the plurality of unit symbols.
Claim 20.
The transmitting and receiving system according to claim 15, wherein the transmitting circuit comprises: a serializer configured to generate a plurality of unit symbols each including one most significant bit and one least significant bit by serializing the first and second transmitting symbols; and a transmission driver configured to drive a transmission signal bus by a PAM-4 signal on the basis of the plurality of unit symbols.
Claim 20.
The transmitting and receiving system according to claim 14, further comprising: a receiving circuit configured to receive the PAM-4 signal and generate a first received symbol, a second received symbol, a third received symbol, and a fourth received symbol; and a symbol decoding circuit configured to generate a first decoded symbol by selectively inverting the first received symbol based on the fourth received symbol, to generate a second decoded symbol by selectively inverting the second received symbol based on the first received symbol, to generate a third decoded symbol by selectively inverting the third received symbol based on the second received symbol, to generate a fourth decoded symbol by selectively inverting the fourth received symbol based on the third received symbol, and to generate a first decoded burst, a second decoded burst, a third decoded burst, and a fourth decoded burst by decoding the first to fourth decoded symbols, respectively.
Claim 21.
The transmitting and receiving system according to claim 15, further comprising: a receiving circuit configured to receive the PAM-4 signal and generate a first received symbol and a second received symbol; and a symbol decoding circuit configured to generate a first decoded symbol by selectively inverting the first received symbol on the basis of a logic level of a bit with a specific sequence number of a previously received symbol, to generate a second decoded symbol by selectively inverting the second received symbol on the basis of a logic level of a bit with a specific sequence number of the first received symbol, and to generate a first decoded burst and a second decoded burst by decoding the first and second decoded symbols, respectively.
Claim 21.
The transmitting and receiving system according to claim 20, wherein the symbol decoding circuit comprises: a first inverting circuit configured to generate the first decoded symbol by selectively inverting the first received symbol based on a logic level of a bit with a specific sequence number of the fourth received symbol; a second inverting circuit configured to generate the second decoded symbol by selectively inverting the second received symbol based on a logic level of a bit with the specific sequence number of the first received symbol; a third inverting circuit configured to generate the third decoded symbol by selectively inverting the third received symbol based on a logic level of a bit with a specific sequence number of the second received symbol; a fourth inverting circuit configured to generate the fourth decoded symbol by selectively inverting the fourth received symbol based on a logic level of a bit with the specific sequence number of the third received symbol; a first decoder configured to generate the first decoded burst by decoding the first decoded symbol; a second decoder configured to generate the second decoded burst by decoding the second decoded symbol; a third decoder configured to generate the third decoded burst by decoding the third decoded symbol; and a fourth decoder configured to generate the fourth decoded burst by decoding the fourth decoded symbol.
Claim 22.
The transmitting and receiving system according to claim 21, wherein the symbol decoding circuit comprises: a first inverting circuit configured to generate the first decoded symbol by selectively inverting the first received symbol on the basis of the logic level of the bit with the specific sequence number of the previously received symbol; a second inverting circuit configured to generate the second decoded symbol by selectively inverting the second received symbol on the basis of the logic level of the bit with the specific sequence number of the first received symbol; a first decoder configured to generate the first decoded burst by decoding the first decoded symbol; and a second decoder configured to generate the second decoded burst by decoding the second decoded symbol.
Claim 22.
The transmitting and receiving system according to claim 21, further comprising: a data interleaving circuit configured to further receive an interleaved symbol and to generate input data based on the first decoded burst, the second decoded burst, the third decoded burst, the fourth decoded burst, and the interleaved symbol.
Claim 23.
The transmitting and receiving system according to claim 22, further comprising: a data interleaving circuit configured to further receive an interleaved symbol and to generate input data on the basis of the first decoded burst, the second decoded burst, and the interleaved symbol.
From the table above, claims 1, 5-16, and 18-23 of the reference application‘395 contain every limitations of claims 1, 4-14, and 16-22 of the instant application except the feature of “encode a third encoded symbol, and a fourth encoded symbol; and generate a third inversion signal based on the second burst, and to generate a fourth inversion signal based on the third burst.” However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, that the reference application can include the feature of encode a third encoded symbol, and a fourth encoded symbol; and generate a third inversion signal based on the second burst, and to generate a fourth inversion signal based on the third burst since encode and generate a plurality of symbols (first and second symbols).
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized encode a third encoded symbol, and a fourth encoded symbol; and generate a third inversion signal based on the second burst, and to generate a fourth inversion signal based on the third burst would have improved the memory system performance.
Thus, claims 1, 4-14 and 16-22 of the instant application are not patentably distinct over the patent application because both applications contain substantially the same limitations performing the same function. This is a non-provisional nonstatutory double patenting rejection because the patentably indistinct claims have been patented.
Allowable Subject Matter
11. Claims 1, 4-14 and 16-22 will be allowed if rewritten to overcome the rejection(s) under 35 U.S.C. 101 and the double patenting rejection is overcome. The following is an examiner’s statement of reasons for allowance:
In regards to claim 1:
The prior arts of record taken singly or in combination fail to teach, anticipate, suggest, or render obvious the following limitations. Particularly the prior art Seol et al. (US 2022/0294476 A1) teaches “A transmitting device comprising: an encoding block configured to encode a first burst, a second burst, a third burst, and a fourth burst to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and a fourth encoded symbol, respectively” However, the prior arts do not teach “an inversion determination circuit configured to generate a first inversion signal based on a fourth transmitting symbol, to generate a second inversion signal based on the first burst, to generate a third inversion signal based on the second burst, and to generate a fourth inversion signal based on the third burst; and an inversion block configured to generate a first transmitting symbol based on the first encoded symbol and the first inversion signal, to generate a second transmitting symbol based on the second encoded symbol and the second inversion signal, to generate a third transmitting symbol based on the third encoded symbol and the third inversion signal, and to generate the fourth transmitting symbol based on the fourth encoded symbol and the fourth inversion signal” as recited in the independent claim 1. Consequently, claim 1 is/are allowed over the prior arts.
In regards to claim 8:
The prior arts of record taken singly or in combination fail to teach, anticipate, suggest, or render obvious the following limitations. Particularly the prior art Seol et al. (US 2022/0294476 A1) teaches “A transmitting and receiving method comprising: dividing output data into a first burst, a second burst, a third burst, and a fourth burst; determining whether a bit with a specific number of each of a fourth transmitting symbol, the first burst, the second burst, and the third burst is a first logic level; encoding the first burst, the second burst, the third burst, and the fourth burst to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and the fourth encoded symbol, respectively.” However, the prior arts do not teach “selectively inverting the first encoded symbol, the second encoded symbol, the third encoded symbol, and the fourth encoded symbol based on a result of the determination to generate a first transmitting symbol, a second transmitting symbol, a third transmitting symbol, and the fourth transmitting symbol, respectively; and transmitting a 4-level pulse amplitude modulation (PAM-4) signal based on the first transmitting symbol, the second transmitting symbol, the third transmitting symbol, and the fourth transmitting symbol.” as recited in the independent claim 8. Consequently, claim 8 is/are allowed over the prior arts.
In regards to claim 14:
The prior arts of record taken singly or in combination fail to teach, anticipate, suggest, or render obvious the following limitations. Particularly the prior art Seol et al. (US 2022/0294476 A1) teaches “A transmitting and receiving system comprising: a transmitting device configured to transmit a 4-level pulse amplitude modulation (PAM-4) signal; and a receiving device configured to receive the PAM-4 signal, wherein the transmitting device comprises: a symbol encoding circuit configured: to divide output data into a first burst, a second burst, a third burst, and a fourth burst; to generate a first encoded symbol, a second encoded symbol, a third encoded symbol, and a fourth encoded symbol by encoding the first to fourth bursts, respectively” However, the prior arts do not teach “an inversion determination circuit configured to generate a first inversion signal based on a fourth transmitting symbol, to generate a second inversion signal based on the first burst, to generate a third inversion signal based on the second burst, and to generate a fourth inversion signal based on the third burst; and an inversion block configured to generate a first transmitting symbol based on the first encoded symbol and the first inversion signal, to generate a second transmitting symbol based on the second encoded symbol and the second inversion signal, to generate a third transmitting symbol based on the third encoded symbol and the third inversion signal, and to generate the fourth transmitting symbol based on the fourth encoded symbol and the fourth inversion signal” as recited in the independent claim 1. Consequently, claim 1is/are allowed over the prior arts. Dependent claims 2-7, 9-13, 15-22 are objected to as being dependent upon a rejected base claims 1, 8, and 14 respectively, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and also if rewritten to overcome the rejection(s) under 35 U.S.C. 101, and double patenting rejections set forth in this Office action. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Examiner Notes
12. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
13. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/ Examiner, Art Unit 2112
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