DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5-12, 15 and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zheng et al. (hereinafter “Zheng”), CN112053661 (reference will be translated by corresponding US application 2023/0052846).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Zheng teaches a pixel circuit (figs. 3,4), comprising a light emitting element (fig. 3, light emitting element EL), a driving circuit (fig. 3, driving circuitry 11), a first energy storage circuit (fig. 3, first energy storage circuitry 12), a second energy storage circuit (fig. 3, second energy storage circuitry 13), a writing-in control circuit (fig. 3, data writing circuitry 14) and a first control circuit (fig. 3, light emission control circuitry 31); wherein a first terminal of the first energy storage circuit is electrically connected to a control terminal of the driving circuit, and a second terminal of the first energy storage circuit is electrically connected to a first terminal of the driving circuit (fig. 4, first energy storage circuitry 12); the first energy storage circuit is used to store electrical energy (fig. 4, capacitor C1); a first terminal of the second energy storage circuit is electrically connected to a control terminal of the driving circuit (fig. 4, second energy storage circuitry 13); the second energy storage circuit is used to store electric energy (fig. 4, capacitor C2); the writing-in control circuit is electrically connected to a first writing-in control terminal, a writing-in terminal and a second terminal of the second energy storage circuit respectively, is configured to control to connect or disconnect the writing-in terminal and the second terminal of the second energy storage circuit under the control of the first writing-in control signal provided by the first writing-in control terminal (fig. 4 and accompanying text, data writing circuitry 14); the first control circuit is electrically connected to a first control terminal, a power supply voltage terminal and a first terminal of the driving circuit, and is used to control to connect or disconnect the power supply voltage terminal and the first terminal of the driving circuit under the control of a first control signal provided by the first control terminal (fig. 4 and accompanying text, light emission control circuitry 31); a second terminal of the driving circuit is electrically connected to the light emitting element, and the driving circuit is configured to generate a driving current for driving the light emitting element under the control of a potential of the control terminal of the driving circuit (fig. 4 and accompanying text, driving circuitry 11); wherein the driving circuit includes no additional transistor configured to electrically connect the control terminal and the second terminal of the driving circuit (fig. 4, driving circuit 11 has no additional transistor).
Regarding claim 5, Zheng teaches a reference voltage writing-in circuit; wherein the reference voltage writing-in circuit is electrically connected to a second writing- in control terminal, a reference voltage terminal and the control terminal of the driving circuit respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the control terminal of the driving circuit under the control of a second writing-in control signal provided by the second writing-in control terminal (fig. 3, Voltage reference Vr).
Regarding claim 6, Zheng teaches a second control circuit (fig. 3, second resetting circuitry 32); wherein the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element (fig. 3, light emitting element EL), and the second electrode of the light emitting element is electrically connected to the first voltage terminal (fig. 3, voltage V2); the second control circuit is electrically connected to a second control terminal, a reset voltage terminal and the first electrode of the light emitting element, and is configured to control to write a reset voltage provided by the reset voltage terminal into the first electrode of the light emitting element under the control of a second control signal provided by the second control terminal (fig. 3, first resetting circuitry 20, second resetting circuitry 32).
Regarding claim 7, Zheng teaches a resistor circuit; wherein the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element through the resistor circuit, the second electrode of the light emitting element is electrically connected to the first voltage terminal (fig. 3, compensation circuitry 15, voltage V2).
Regarding claim 8, Zheng teaches wherein the first energy storage circuit comprises a first capacitor (fig. 4, capacitor C1); the second energy storage circuit comprises a second capacitor (fig. 4, C2); the writing-in control circuit includes a first transistor (fig. 4, transistor T1); a first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the first capacitor is electrically connected to the first terminal of the driving circuit (fig. 4, driving circuitry 11); a first terminal of the second capacitor is electrically connected to the control terminal of the driving circuit (fig. 4, driving circuitry 11); a control electrode of the first transistor is electrically connected to the first writing- in control terminal, a first electrode of the first transistor is electrically connected to the writing-in terminal, and a second electrode of the first transistor is electrically connected to the second terminal of the second capacitor (fig. 4, transistor T1, capacitor C2); a back gate electrode of the first transistor is electrically connected to the second voltage terminal (fig. 4, voltage Vdt).
Regarding claim 9, Zheng teaches wherein the first control circuit comprises a second transistor (fig. 4, transistor T7); the driving circuit comprises a driving transistor (fig. 4, transistor T3); a control electrode of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the power supply voltage terminal, and a second electrode of the second transistor is electrically connected to the first terminal of the driving transistor (fig. 4, transistor T7, transistor T3); a back gate electrode of the second transistor is electrically connected to the second voltage terminal (fig. 4, Vdd); a control electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit (fig. 4, driving circuitry 11); a back gate electrode of the driving transistor is electrically connected to the second voltage terminal (fig. 4, voltage Vdd).
Regarding claim 10, Zheng teaches wherein the reference voltage writing-in circuit comprises a third transistor (fig. 4, transistor T5); a control electrode of the third transistor is electrically connected to the second writing-in control terminal (fig. 5, transistor T6), a first electrode of the third transistor is electrically connected to the reference voltage terminal (fig. 4, Vr), and a second electrode of the third transistor is electrically connected to the control terminal of the driving circuit (fig. 4, T3); a back gate electrode of the third transistor is electrically connected to the second voltage terminal (fig. 4, Vdd).
Regarding claim 11, Zheng teaches wherein the second control circuit comprises a fourth transistor (fig. 4, transistor T6); a control electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the reset voltage terminal (fig. 4, Vi), and a second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element (fig. 4, N4); a back gate electrode of the fourth transistor is electrically connected to a third voltage terminal (fig. 4, Vi).
Regarding claim 12, Zheng teaches wherein the fourth transistor is an n-type transistor, and the third voltage terminal is the reset voltage terminal (fig. 4, [0042]).
Regarding claim 15, it is a display panel of claim 1 and is rejected on the same grounds presented above.
Regarding claim 16, it is a method of claim 1 and is rejected on the same grounds presented above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng (see above), in view of Cao et al. (hereinafter “Cao”), US Pub. No. 2022/0189397.
Regarding claim 2, Zheng fails to explicitly teach wherein the first control circuit is configured to control the connection between the power supply voltage terminal and the first terminals of the driving circuit in two discontinuous phases in one display period after the control of the first control signal.
However, in the same field of endeavor, Cao teaches during the reset phase the first light emission control signal EM1 is low, during the compensation phase EM1 is high, during writing phase EM1 is high, during the light emission phase EM1 is low (i.e. the first control circuit is configured to control the communication between the supply voltage terminal and the first terminal of the driver circuit under the control of the first control signal in two discontinuous phases within one display cycle).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zheng to include the feature of Cao. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to provide a device with increased efficiency.
Regarding claim 17, it has similar limitations to those of claim 2 and is rejected on the same grounds presented above.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zheng (see above), in view of Zheng et al. (hereinafter “Zheng II”), US Pub. No. 2022/0376024.
Regarding claim 20, Zheng fails to explicitly teach wherein the display panel comprises a first silicon substrate, and the pixel circuit and a gate driving circuit arranged on the first silicon substrate; the display device further includes a second silicon substrate, and a display driver chip arranged on the second silicon substrate; wherein an area of the first silicon substrate is larger than an area of the second silicon substrate: a minimum width of a signal line included in the display panel is greater than a width of a signal line included in the display driver chip.
However, in the same field of endeavor, Zheng II teaches a display substrate including first and second silicon substrates and wherein a width of a signal line included in the display panel is greater than a width of a signal line included in the display driver chip (see fig. 3 and accompanying text, [0046]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filling date of the invention to modify Zheng to include the structure of Zheng II. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to provide a display structure that utilized maximum display efficiency.
Allowable Subject Matter
Claims 3-4, 13, 14, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, either singularly or in combination, teaches or fairly suggests “wherein a display period of the pixel circuit may include an initialization phase, a self-discharge phase, a data preparation phase, a data writing-in phase, and a light emitting phase that are set successively; the first control circuit is configured to control the connection between the power supply voltage terminal and the first terminal of the driving circuit in the initialization phase, the data preparation phase, the data writing-in phase and the light emitting phase, control to disconnect the power supply voltage terminal from the first terminal of the driving circuit in the self- discharging phase under the control of the first control signal” and “wherein the fourth transistor is an n- type transistor; a deep n hydrazine is provided between the back gate electrode of the fourth transistor and a P-type substrate to isolate the back gate electrode of the fourth transistor from the P-type base substrate; the base gate electrode and the first electrode of the fourth transistors are all electrically connected to the reset voltage terminal further comprising an n hydrazine and a p hydrazine; wherein a doping concentration of the n hydrazine is greater than a doping concentration of the deep n hydrazine; a ratio of a thickness of the n hydrazine to a thickness of the deep n hydrazine is greater than or equal to 0.4 and less than or equal to 0.6; a ratio of a thickness of the p hydrazine to the thickness of the deep n hydrazine is greater than or equal to 0.4 and less than or equal to 0.6.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al. (US Pub. No. 2023/0028312) teaches a pixel circuit including a light emitting element, a driving transistor, first and second capacitors, a light emission control circuit and a data input circuit.
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/KENNETH B LEE JR/Primary Examiner, Art Unit 2625