DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,369,472. Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims are merely broader versions of the patented claims and thus are anticipated by the patented claims.
Below is a comparison between present claim 1 and patented claim 6:
Present claim 1
Patented claim 6
A display panel, comprising:
A display panel, comprising:
a base substrate comprising a display area and a peripheral area surrounding the display area;
a base substrate comprising a display area and a peripheral area surrounding the display area;
a plurality of sub-pixels located at the display area, wherein each of the plurality of sub-pixels comprises a light-emitting element and a pixel driving circuit configured to drive the light-emitting element, and at least one of the plurality of sub-pixels further comprises a shielding layer, the shielding layer being electrically connected to a power line through a via hole;
a plurality of sub-pixels located at the display area, wherein each of the plurality of sub-pixels comprises a light-emitting element and a pixel driving circuit configured to drive the light-emitting element, and at least one of the plurality of sub-pixels further comprises a shielding layer;
a plurality of gate lines located at the display area and electrically connected to the plurality of sub-pixels;
a plurality of gate lines located at the display area and electrically connected to the plurality of sub-pixels;
a plurality of light-emitting control lines located at the display area and electrically connected to the plurality of sub-pixels;
a gate driving circuit comprising a plurality of gate driving sub-circuits, the plurality of gate driving sub-circuits comprises a first gate driving sub-circuit and a second gate driving sub-circuit that are spaced apart by pixel driving circuits of a first group of sub-pixels of the plurality of sub-pixels; and
a gate driving circuit comprising cascaded multistage gate driving units electrically connected to the plurality of gate lines, wherein one or more stages gate driving units of the multistage gate driving units comprise a plurality of gate driving sub-circuits, the plurality of gate driving sub-circuits comprises a first gate driving sub-circuit and a second gate driving sub-circuit that are spaced apart by pixel driving circuits of a first group of sub-pixels of the plurality of sub-pixels; and
a gate driving sub-circuit connection line electrically connected to the first gate driving sub-circuit and the second gate driving sub-circuit, wherein an orthographic projection of the gate driving sub-circuit connection line on the base substrate at least partially overlaps with an orthographic projection of the shielding layer on the base substrate.
a gate driving sub-circuit connection line electrically connected to the first gate driving sub-circuit and the second gate driving sub-circuit, wherein an orthographic projection of the gate driving sub-circuit connection line on the base substrate at least partially overlaps with an orthographic projection of the shielding layer on the base substrate.
wherein: the gate driving circuit is located at the display area; and/or the shielding layer is electrically connected to a power line through a via hole.
As shown above, besides wording, the main difference between present claim 1 and patented claim 6 is that patented claim 6 recites “a plurality of light-emitting control lines located at the display area and electrically connected to the plurality of sub-pixels” and “cascaded multistage gate driving units electrically connected to the plurality of gate lines” whereas present claim 1 fails to recite these features. Thus, present claim 1 is merely a broader version of patented claim 6, and therefore, present claim 1 is anticipated by patented claim 6.
Claim 2 is similarly rejected over claim 2 of U.S. Patent No. 12,369,472.
Claim 3 is similarly rejected over claim 3 of U.S. Patent No. 12,369,472.
Claim 4 is similarly rejected over claim 4 of U.S. Patent No. 12,369,472.
Claim 5 is similarly rejected over claim 6 of U.S. Patent No. 12,369,472.
Claim 6 is similarly rejected over claim 7 of U.S. Patent No. 12,369,472.
Claim 7 is similarly rejected over claim 8 of U.S. Patent No. 12,369,472.
Claim 8 is similarly rejected over claim 9 of U.S. Patent No. 12,369,472.
Claim 9 is similarly rejected over claim 10 of U.S. Patent No. 12,369,472.
Claim 10 is similarly rejected over claim 13 of U.S. Patent No. 12,369,472.
Claim 11 is similarly rejected over claim 14 of U.S. Patent No. 12,369,472.
Claim 12 is similarly rejected over claim 11 of U.S. Patent No. 12,369,472.
Claim 13 is similarly rejected over claim 12 of U.S. Patent No. 12,369,472.
Claim 14 is similarly rejected over claim 16 of U.S. Patent No. 12,369,472.
Claim 15 is similarly rejected over claim 17 of U.S. Patent No. 12,369,472.
Claim 16 is similarly rejected over claim 18 of U.S. Patent No. 12,369,472.
Claim 17 is similarly rejected over claim 5 of U.S. Patent No. 12,369,472.
Claim 18 is similarly rejected over claim 19 of U.S. Patent No. 12,369,472.
Claim 19 is similarly rejected over claim 20 of U.S. Patent No. 12,369,472.
Claim 20 is similarly rejected over claim 15 of U.S. Patent No. 12,369,472.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-7, 10-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2017/0345373) in view of Liu (CN 108470717 A)*.
*For translation purposes, the examiner will refer to the US equivalent document US 2020/0243566.
Regarding claim 1, Kang et al. disclose a display panel (Figure 1), comprising:
a base substrate comprising a display area and a peripheral area surrounding the display area (Figure 1, DR is a display area and NR is a peripheral area, see also paragraph [0040].);
a plurality of sub-pixels located at the display area (Figure 1, PX), wherein each of the plurality of sub-pixels comprises a light-emitting element and a pixel driving circuit configured to drive the light-emitting element (Figure 13, OLED is a light-emitting element and M1-M7 are a pixel driving circuit. See also paragraph [0101].);
a plurality of gate lines located at the display area and electrically connected to the plurality of sub-pixels (Figures 2 or 6 and 13, G1-Gn are gate lines. See also paragraph [0043].);
a gate driving circuit (Figure 1, 110 and Figure 11) comprising a plurality of gate driving sub-circuits (Figure 11 and paragraph [0082]), the plurality of gate driving sub-circuits comprises a first gate driving sub-circuit and a second gate driving sub-circuit that are spaced apart by pixel driving circuits of a first group of sub-pixels of the plurality of sub-pixels (Figure 11 shows PXs 12 and 22 between GW1-1 and GWB1-1, etc. See also paragraphs [0082]-[0084].); and
a gate driving sub-circuit connection line electrically connected to the first gate driving sub-circuit and the second gate driving sub-circuit (Paragraphs [0082]-[0083] and Figure 11, GW1-1 and GWB1-1 are first and second sub-blocks of a first gate driver, and thus are connected [although not shown]. It is understood then that there would be a connection line between them as similarly shown for SB1-1 and SB1-2 in Figures 7-8.).
Kang et al. fail to teach:
at least one of the plurality of sub-pixels further comprises a shielding layer, the shielding layer being electrically connected to a power line through a via hole; and
wherein an orthographic projection of the gate driving sub-circuit connection line on the base substrate at least partially overlaps with an orthographic projection of the shielding layer on the base substrate.
Liu discloses a display panel, comprising:
a base substrate (Figure 6A-6C and 7A-7B, 10 is a base substrate.)
at least one of the plurality of sub-pixels further comprises a shielding layer (Figures 6A-6C and 7A-7B, 11 is a shielding layer.), the shielding layer being electrically connected to a power line through a via hole (Figure 6B shows that 11 is electrically connected to 20 [which is a power line since it supplies power] through a via hole 122.); and
a gate driving sub-circuit connection line (Figures 7A-7B, 23 is a gate driving sub-circuit connection line.)
wherein an orthographic projection of the gate driving sub-circuit connection line on the base substrate at least partially overlaps with an orthographic projection of the shielding layer on the base substrate (Figures 7A-7B and paragraph [0083], the orthographic projection of 23 at least partially overlaps with the orthographic projection of 11 on base substrate 10.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the shielding layer teachings of Liu and apply them to the display panel taught by Kang et al. such that there would be a shielding layer which overlaps with the gate driving sub-circuit connection line. The motivation to combine would have been in order to take advantage of the known benefits of a shielding layer such as improving the electrical characteristics of the transistors by shielding light (See paragraph [0004] of Liu, for example.).
Regarding claim 5, Kang et al. and Liu disclose the display panel according to claim 1, wherein the gate driving circuit is located at the display area (Kang et al.: Figure 11).
Regarding claim 6, Kang et al. and Liu disclose the display panel according to claim 1, wherein one end of the gate driving sub-circuit connection line is electrically connected to the first gate driving sub-circuit and the other end of the second gate driving sub-circuit is electrically connected to the second gate driving sub-circuit (In the combination, since the connection line connects the first gate driving sub-circuit and the second gate driving sub-circuit, then one “end” is connected to the first gate driving sub-circuit and the other “end” is connected to the second gate driving sub-circuit.).
Regarding claim 7, Kang et al. and Liu disclose the display panel according to claim 1, further comprising:
a plurality of light-emitting control lines located at the display area and electrically connected to the plurality of sub-pixels (Kang et al.: Figures 11 and 13, EMs and paragraph [0081].); and
a light-emitting control driving circuit located at the display area (Kang et al.: Figure 11 and paragraphs [0082] and [0085].) and comprising cascaded multistage light-emitting control driving units electrically connected to the plurality of light-emitting control lines (Kang et al.: Figure 11 and paragraph [0085]), wherein one or more stages light-emitting control driving units of the multistage light-emitting control driving units comprise a plurality of light-emitting control driving sub-circuits (Kang et al.: Figure 11 and paragraphs [0082] and [0085].), the plurality of light-emitting control driving sub-circuits comprises a first light-emitting control driving sub-circuit and a second light-emitting control driving sub-circuit that are spaced apart by pixel driving circuits of a second group of sub-pixels of the plurality of sub-pixels (Kang et al.: Figure 11 shows PXs 16 and 26 between EM1 and EMB1. See also paragraph [0085].).
Regarding claim 10, Kang et al. and Liu disclose the display panel according to claim 1, wherein:
the first group of sub-pixels is electrically connected to a first gate line of the plurality of gate lines (Kang et al.: Figure 13, PX1 electrically connected to GW1. See also paragraph [0103].);
the gate driving circuit comprises cascaded multistage gate driving units electrically connected to the plurality of gate lines, wherein one or more stages gate driving units of the multistage gate driving units comprise the plurality of gate driving sub-circuits comprises, the first gate driving sub-circuit of each stage gate driving unit of the one or more stages gate driving units (Kang et al.: Figure 4, SB1-3) comprises a first input terminal of each stage gate driving unit (Kang et al.: Figure 4, gate of TR1), and the first input terminal is configured to receive a first input signal (Kang et al.: Figure 4, GCK1 and paragraph [0057].); and
the second gate driving sub-circuit of each stage gate driving unit (Kang et al.: Figure 4, SB1-5) comprises a first output terminal of each stage gate driving unit (Kang et al.: Figure 4, G1), and the first output terminal is configured to output a gate driving signal to the first gate line (Kang et al.: Figure 4 and paragraph [0059], outputs a gate driving signal at G1 [first gate line].).
Regarding claim 11, Kang et al. and Liu disclose the display panel according to claim 10, wherein:
any one stage gate driving unit of the multistage gate driving units comprises the plurality of gate driving sub-circuits (Kang et al.: Figure 4, SB1-1 to SB1-5), and the first gate driving sub-circuit and the second gate driving sub-circuit are spaced apart by the pixel driving circuits of the first group of sub-pixels in a first direction (Kang et al.: Figure 4 shows SB1-3 and SB1-5 are separated by PXs.);
the first gate driving sub-circuit of the any one stage gate driving unit (Kang et al.: Figure 5, SB2-3) is located between the first gate driving sub-circuit of a former stage gate driving unit of the any one stage gate driving unit and the first gate driving sub-circuit of a latter stage gate driving unit of the any one stage gate driving unit in a second direction different from the first direction (Kang et al.: Figure 7 and paragraph [0050] show SB2-3 is between SB1-3 and SB3-3.); and
the second gate driving sub-circuit of the any one stage gate driving unit (Kang et al.: Figure 5, SB2-5) is located between the second gate driving sub-circuit of the former stage gate driving unit of the any one stage gate driving unit and the second gate driving sub-circuit of the latter stage gate driving unit of the any one stage gate driving unit in the second direction (Kang et al.: Figure 7 and paragraph [0050] show SB2-5 is between SB1-5 and SB3-5.).
Regarding claim 12, Kang et al. and Liu disclose the display panel according to claim 7, wherein:
the second group of sub-pixels comprises a plurality of first sub-pixels electrically connected to a first light-emitting control line of the plurality of light-emitting control lines (Kang et al.: Figures 11 and 13, PX16 or PX26 are connected to a first EM), and a plurality of second sub-pixels electrically connected to a second light-emitting control line of the plurality of light-emitting control lines (Kang et al.: Figures 11 and 13, PX36 or PX46 are connected to a second EM. See also paragraph [0085].);
the first light-emitting control driving sub-circuit of each stage light-emitting control driving unit of the one or more multistage light-emitting control driving units comprises a second input terminal of each stage light-emitting control driving unit, and the second input terminal is configured to receive a second input signal (Kang et al.: It is understood that the configuration of the light-emitting control driving unit stages will be similar to that as described for the gate stages [see the explanation in claims 10-11]. Thus, the first light-emitting control driving sub-circuit will similarly have a transistor TR1 [second input terminal] which receives a clock signal [second input signal]); and
the second light-emitting control driving sub-circuit of each stage light-emitting control driving unit comprises a second output terminal of each stage light-emitting control driving unit, and the second output terminal is configured to output a light-emitting control signal to the first light-emitting control line and the second light-emitting control line (Kang et al.: Per the explanation above, the second light-emitting control driving sub-circuit will have an output terminal EM that outputs a light-emitting control signal the light-emitting control lines).
Regarding claim 13, Kang et al. and Liu disclose the display panel according to claim 12, wherein:
any one stage light-emitting control driving unit of the multistage light-emitting control driving units comprises the plurality of light-emitting control driving sub-circuits (Kang et al.: Figure 11, EM1 and EMB1), and the first light-emitting control driving sub-circuit and the second light-emitting control driving sub-circuit are spaced apart by the pixel driving circuits of the first group of sub-pixels in a first direction (Kang et al.: Figure 11 shows EM1 and EMB1 are separated by pixels PX 16 and 26.);
the first light-emitting control driving sub-circuit of the any one stage light-emitting control driving unit is located between the first light-emitting control driving sub-circuit of a former stage light-emitting control driving unit of the any one stage light-emitting control driving unit and the first light-emitting control driving sub-circuit of a latter stage light-emitting control driving unit of the any one stage light-emitting control driving unit in a second direction different from the first direction (Kang et al.: Figure 11 shows only the first 2 stages, however, clearly there will be an EM3, as such EM2 [first light-emitting control driving sub-circuit] is between EM1 [former stage light-emitting control driving unit] and EM3 [latter stage light-emitting control driving unit]); and
the second light-emitting control driving sub-circuit of the any one stage light-emitting control driving unit is located between the second light-emitting control driving sub-circuit of the former stage light-emitting control driving unit of the any one stage light-emitting control driving unit and the second light-emitting control driving sub-circuit of the latter stage light-emitting control driving unit of the any one stage light-emitting control driving unit in the second direction (Kang et al.: Figure 11 shows only the first 2 stages, however, clearly there will be an EMB3, as such EMB2 [second light-emitting control driving sub-circuit] is between EMB1 [former stage light-emitting control driving unit] and EMB3 [latter stage light-emitting control driving unit]).
Regarding claim 20, Kang et al. and Liu disclose a display device, comprising the display panel according to claim 1 (Kang et al.: Figure 1 and paragraph [0039].).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2017/0345373) in view of Liu (CN 108470717 A) and further in view of Han et al. (US 2018/0138256).
Regarding claim 8, Kang et al. and Liu disclose the display panel according to claim 7.
Kang et al. and Liu fail to teach wherein:
an orthographic projection of at least one of the plurality of gate driving sub-circuits on the base substrate overlaps with orthographic projections of anodes of light-emitting elements of a first portion of sub-pixels of the plurality of sub-pixels on the base substrate, and does not overlap with orthographic projections of anodes of light-emitting elements of remaining sub-pixels of the plurality of sub-pixels other than the first portion of sub-pixels on the base substrate; and/or
an orthographic projection of at least one of the plurality of light-emitting control driving sub-circuits on the base substrate overlaps with orthographic projections of anodes of light-emitting elements of a second portion of sub-pixels of the plurality of sub-pixels on the base substrate, and does not overlap with orthographic projections of anodes of light-emitting elements of remaining sub-pixels of the plurality of sub-pixels on the base substrate other than the second portion of sub-pixels.
Han et al. disclose a display panel wherein an orthographic projection of at least one of a plurality of gate driving sub-circuits on a base substrate (Figure 21, GIP TR) overlaps with orthographic projections of anodes of light-emitting elements of a first portion of sub-pixels of the plurality of sub-pixels on the base substrate (Figure 21, ANO for the subpixel shown), and does not overlap with orthographic projections of anodes of light-emitting elements of remaining sub-pixels of the plurality of sub-pixels other than the first portion of sub-pixels on the base substrate (Figure 21, GIP TR will not overlap with ANO of sub-pixels not shown, i.e. remaining sub-pixels.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the orthographic projection teachings of Han et al. in the display panel taught by the combination of Kang et al. and Liu. The motivation to combine would have been in order to minimize the bezel area of the display circuit (See paragraph [0010] of Han et al.) while also maintaining aperture ratio of the pixels, thus maximizing display area and display quality.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2017/0345373) in view of Liu (CN 108470717 A) and further in view of Shin (US 2016/0321995).
Regarding claim 9, Kang et al. and Liu disclose the display panel according to claim 7.
Kang et al. and Liu fail to teach the display panel further comprising:
a plurality of initialization lines located at the display area and electrically connected to the plurality of sub-pixels; and
a plurality of reset lines located at the display area and electrically connected to the plurality of sub-pixels,
wherein the first group of sub-pixels is electrically connected to a first initialization line of the plurality of initialization lines, a first reset line of the plurality of reset lines, a first gate line of the plurality of gate lines and a first light-emitting control line of the plurality of light-emitting control lines, the first initialization line and the first reset line are located on one side of the plurality of gate driving sub-circuits, and the first gate line and the first light-emitting control line are located on one side of the plurality of gate driving sub-circuits away from the first initialization line and the first reset line.
Shin discloses a display panel comprising:
a plurality of initialization lines located at a display area and electrically connected to a plurality of sub-pixels (Figures 1-2, GI [initialization lines]); and
a plurality of reset lines located at the display area and electrically connected to the plurality of sub-pixels (Figures 1-2, GB [reset lines]),
wherein a first group of sub-pixels (Figure 1, first row, for example.) is electrically connected to a first initialization line of the plurality of initialization lines (Figures 1-2, GI), a first reset line of the plurality of reset lines (Figures 1-2, GB) a first gate line of the plurality of gate lines (Figures 1-2, GW) and a first light-emitting control line of the plurality of light-emitting control lines (Figures 1-2, EM), and the first reset line is located on one side of the pixel circuits (Figure 1, GB is below the pixel circuits), and the first gate line and the first light-emitting control line are located on one side of the plurality of gate driving sub-circuits away from the first reset line (Figure 1, GW and EM are above the pixel circuits.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the initialization and reset teachings of Shin in the display panel taught by the combination of Kang et al. and Liu such that the reset lines, gate lines and first light-emitting control lines are on sides of the plurality of gate driving sub-circuits since the subcircuits in Kang et al. are located in-between the pixel areas. The motivation to combine would have been in order to take advantage of the known benefits of providing resetting and initialization, such as solving luminance degradation and improving display quality.
Kang et al., Liu and Shin fail to teach wherein the first initialization line located on the same side of the plurality of gate driving sub-circuits as the reset line, however, it would have been an obvious design choice to “one of ordinary skill” in the art before the effective filing date of the claimed invention to move the first initialization line to the same side of the plurality of gate driving sub-circuits as the reset line since it has been held that merely changing the position of an element is unpatentable when the result does not modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Allowable Subject Matter
Claims 2-4 and 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if a Terminal Disclaimer is filed to overcome the Double Patenting rejection.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reasons for indicating allowable subject matter in claim 2 is the inclusion of the limitations reciting “a first group of circuit connection lines comprising a first circuit connection line and a second circuit connection line, wherein: the second gate driving sub-circuit is electrically connected to the first gate driving sub-circuit through the first circuit connection line and the second circuit connection line, an orthographic projection of one of the first circuit connection line and the second circuit connection line on the base substrate does not overlap with orthographic projections of the pixel driving circuits of the first group of sub-pixels on the base substrate, and an orthographic projection of the other of the first circuit connection line and the second circuit connection line on the base substrate overlaps with an orthographic projection of the pixel driving circuit of at least one sub-pixel of the first group of sub-pixels on the base substrate” which, in combination with the other recited features, are not taught and/or suggested either singularly or in combination within the prior art.
The closest prior art (See cited art and the rejections above.) discloses generally of having connection lines, however, fails to teach and/or suggest the specifically claimed features of first and second connection lines regarding not overlapping and overlapping as highlighted above.
Claims 3-4 and 17 are objected to due to their dependency from claim 2.
The primary reasons for indicating allowable subject matter in claim 14 is the inclusion of the limitations reciting “wherein: the first gate driving sub-circuit comprises a first group of transistors and a second capacitor, and the second gate driving sub-circuit comprises a second group of transistors and a first capacitor; and a number of the second group of transistors is smaller than a number of the first group of transistors, and a width-to-length ratio of a channel of at least one transistor of the second group of transistors is greater than a width-to-length ratio of a channel of each transistor of the first group of transistors” which, in combination with the other recited features, are not taught and/or suggested either singularly or in combination within the prior art.
The closest prior art (See cited art and the rejections above.) discloses generally discloses of gate driving sub-circuits and circuits having transistors and capacitors, however, fails to teach and/or suggest the specifically claimed features of the first and second groups of transistors in the first and second gate driving sub-circuits, respectively, having different numbers of transistors and different width-to-length ratios as highlighted above.
Claims 15-16 are objected to due to their dependency from claim 14.
The primary reasons for indicating allowable subject matter in claim 18 is the inclusion of the limitations reciting “a second group of circuit connection lines comprising a fourth circuit connection line and a fifth circuit connection line, wherein: the second light-emitting control driving sub-circuit is electrically connected to the first light-emitting control driving sub-circuit through the fourth circuit connection line and the fifth circuit connection line, and orthographic projections of the fourth circuit connection line and the fifth circuit connection line on the base substrate overlaps with orthographic projections of the pixel driving circuits of the second group of sub-pixels on the base substrate” which, in combination with the other recited features, are not taught and/or suggested either singularly or in combination within the prior art.
The closest prior art (See cited art and the rejections above.) discloses generally of having connection lines, however, fails to teach and/or suggest the specifically claimed features of fourth and fifth connection lines regarding overlapping the pixel driving circuits of the second group as highlighted above.
Claim 19 is objected to due to its dependency from claim 18.
Conclusion
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/STEPHEN G SHERMAN/Primary Examiner, Art Unit 2621
8 April 2026
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