DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/176,612, filed on February 16, 2021.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 2, 2025, April 24, 2026, and July 22, 2026 were filed on/after the mailing date of the application on May 2, 2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings were received on May 2, 2025. These drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1 and 3-20 of U.S. Patent No. 12,322,024. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the tables below.
Present Application #19/197,768
1
2
3
4
5
6
7
8
9
10
U.S. Patent #12,322,024
1
1
3
4
5
6
7
8
9
10
Present Application #19/197,768
11
12
13
14
15
16
17
18
19
20
U.S. Patent #12,322,024
11
12
13
14
15
16
17
18
19
20
Present Application #19/197,768 Claim 1
U.S. Patent #12,322,024 Claim 1
A method of storing data for a primitive in a graphics processing system,
A method of storing geometry data for a plurality of primitives in a graphics processing system,
the primitive being formed by one or more vertices and
(Limitation A below)
being associated with state data that defines how the primitive is to be rendered, the method comprising:
each primitive associated with state data that defines how the primitive is to be rendered, the method comprising:
adding the primitive to a primitive block based on at least the state data associated with the primitive,
sorting the plurality of primitives into a plurality of primitive blocks based on at least the state data associated with the primitives,
the primitive block comprising two or more primitive sections and a state data section,
each primitive block comprising two or more primitive sections and a single state data section,
wherein each primitive section comprises data for one or more primitives and has one or more size constraints and
wherein each primitive section comprises transformed geometry for one or more primitives and has one or more size constraints and
wherein each primitive is formed by one or more vertices and (Limitation A)
wherein each primitive section comprises a primitive data sub-section and a vertex data sub-section, and
each primitive section comprises a primitive data sub-section and a vertex data sub-section, and
wherein the state data section comprises information identifying state data common to the one or more primitives for which data is stored in the two or more primitive sections; and
wherein the single state data section comprises information identifying state data common to the one or more primitives in each of the two or more primitive sections; and
storing the primitive block in memory.
storing the plurality of primitive blocks in memory.
Claim 1 of the present application differs from claim 1 of the patent application in that claim 1 of the present application is broader in scope than claim 1 of the patent application, thus encompasses that of the patent application.
Present Application #19/197,768 Claim 2
U.S. Patent #12,322,024 Claim 1
The method of claim 1, wherein
A method…comprising…
the data for the one or more primitives is transformed geometry data.
… each primitive section comprises transformed geometry for one or more primitives…
Present Application #19/197,768 Claim 3
U.S. Patent #12,322,024 Claim 3
The method of claim 1, wherein
The method of claim 1, wherein
the primitive block comprises a header section that comprises information identifying a number of primitive sections in the primitive block.
each primitive block comprises a header section that comprises information identifying a number of primitive sections in the primitive block.
Present Application #19/197,768 Claim 4
U.S. Patent #12,322,024 Claim 4
The method of claim 3, wherein
The method of claim 3, wherein
the header section further comprises information identifying a number of primitives in each primitive section of the primitive block.
the header section further comprises information identifying a number of primitives in each primitive section of the primitive block.
Present Application #19/197,768 Claim 5
U.S. Patent #12,322,024 Claim 5
The method of claim 3, wherein
The method of claim 3, wherein
the header section further comprises, for each primitive section, information identifying a location of a start of that primitive section.
the header section further comprises, for each primitive section, information identifying a location of a start of that primitive section.
Present Application #19/197,768 Claim 6
U.S. Patent #12,322,024 Claim 6
The method of claim 1, wherein
The method of claim 1, wherein
the state data section comprises information identifying a value of each of a plurality of state parameters.
the single state data section comprises information identifying a value of each of a plurality of state parameters.
Present Application #19/197,768 Claim 7
U.S. Patent #12,322,024 Claim 7
The method of claim 6, wherein
The method of claim 6, wherein
the plurality of state parameters comprises one or more of a depth compare mode, a blending state, a texture state and a primitive type.
the plurality of state parameters comprises one or more of a depth compare mode, a blending state, a texture state and a primitive type.
Present Application #19/197,768 Claim 8
U.S. Patent #12,322,024 Claim 8
The method of claim 1, wherein
The method of claim 1, wherein
the state data section comprises a pointer to one of a plurality of combinations of state parameters stored in memory.
the single state data section comprises a pointer to one of a plurality of combinations of state parameters stored in memory.
Present Application #19/197,768 Claim 9
U.S. Patent #12,322,024 Claim 9
The method of claim 1, wherein
The method of claim 1, wherein
the one or more size constraints comprises a maximum number of primitives per primitive section.
the one or more size constraints comprises a maximum number of primitives per primitive section.
Present Application #19/197,768 Claim 10
U.S. Patent #12,322,024 Claim 10
The method of claim 1, wherein
The method of claim 1, wherein
the one or more size constraints comprises a maximum number of vertices per primitive section.
each primitive is formed by one or more vertices and the one or more size constraints comprises a maximum number of vertices per primitive section.
Present Application #19/197,768 Claim 11
U.S. Patent #12,322,024 Claim 11
The method of claim 1, wherein
The method of claim 1, wherein
the primitive data sub-section comprises data related to each primitive in the primitive section and the vertex data sub-section comprises data related to each vertex that forms a primitive in the primitive section.
the primitive data sub-section comprises data related to each primitive in the primitive section and the vertex data sub-section comprises data related to each vertex that forms a primitive in the primitive section.
Present Application #19/197,768 Claim 12
U.S. Patent #12,322,024 Claim 12
The method of claim 1, wherein
The method of claim 1, wherein
the vertex data sub-section comprises a vertex entry for each vertex that forms a primitive in the primitive section, and
the vertex data sub-section comprises a vertex entry for each vertex that forms a primitive in the primitive section, and
the primitive data sub- section comprises a primitive entry for each primitive in the primitive section that identifies the vertex entries in the vertex data sub-section that correspond to the vertices that form that primitive.
the primitive data sub-section comprises a primitive entry for each primitive in the primitive section that identifies the vertex entries in the vertex data sub-section that correspond to the vertices that form that primitive.
Present Application #19/197,768 Claim 13
U.S. Patent #12,322,024 Claim 13
The method of claim 12, wherein
The method of claim 12, wherein
each vertex that forms a primitive in a primitive section is assigned a local index that identifies a location of the corresponding vertex entry in the vertex data sub-section and a primitive entry identifies a particular vertex entry in the vertex data via the local index assigned to the corresponding vertex.
each vertex that forms a primitive in a primitive section is assigned a local index that identifies a location of the corresponding vertex entry in the vertex data sub-section and a primitive entry identifies a particular vertex entry in the vertex data via the local index assigned to the corresponding vertex.
Present Application #19/197,768 Claim 14
U.S. Patent #12,322,024 Claim 14
The method of claim 12, wherein
The method of claim 12, wherein
each vertex entry comprises information identifying a location of the corresponding vertex in a rendering space.
each vertex entry comprises information identifying a location of the corresponding vertex in a rendering space.
Present Application #19/197,768 Claim 15
U.S. Patent #12,322,024 Claim 15
The method of claim 14, wherein
The method of claim 14, wherein
the information identifying the location of the corresponding vertex in the rendering space comprises X, y and Z coordinates of the vertex in the rendering space.
the information identifying the location of the corresponding vertex in the rendering space comprises x, y and z coordinates of the vertex in the rendering space.
Present Application #19/197,768 Claim 16
U.S. Patent #12,322,024 Claim 16
The method of claim 14, wherein
The method of claim 14, wherein
each vertex entry further comprises a set of one or more attributes that describe an appearance of the vertex.
each vertex entry further comprises a set of one or more attributes that describe an appearance of the vertex.
Present Application #19/197,768 Claim 17
U.S. Patent #12,322,024 Claim 17
The method of claim 12, wherein
The method of claim 12, wherein
the vertex entries of a vertex data sub-section are stored in the vertex data sub-section in compressed form.
the vertex entries of a vertex data sub-section are stored in the vertex data sub-section in compressed form.
Present Application #19/197,768 Claim 18
U.S. Patent #12,322,024 Claim 18
The method of claim 12, wherein
The method of claim 12, wherein
each primitive section further comprises a vertex compression sub-section that identifies whether the vertex entries of the vertex data sub-section have been stored in compressed form.
each primitive section further comprises a vertex compression sub-section that identifies whether the vertex entries of the vertex data sub-section have been stored in compressed form.
Present Application #19/197,768 Claim 19
U.S. Patent #12,322,024 Claim 19
A primitive block generator for use in a graphics processing system, the primitive block generator comprising:
A primitive block generator for use in a graphics processing system, the primitive block generator comprising:
primitive block generation logic configured to:
primitive block generation logic configured to:
add a primitive to a primitive block based on at least state data associated with the primitive,
sort a plurality of primitives into a plurality of primitive blocks based on at least state data associated with each of the primitives,
the primitive block comprising two or more primitive sections and a state data section,
each primitive block comprising two or more primitive sections and a single state data section,
wherein each primitive section comprises data for one or more primitives and has one or more size constraints and wherein each primitive is formed by one or more vertices and each primitive section comprises a primitive data sub-section and a vertex data sub-section, and
wherein each primitive section comprises transformed geometry for one or more primitives and has one or more size constraints and wherein each primitive is formed by one or more vertices and each primitive section comprises a primitive data sub-section and a vertex data sub-section, and
wherein the state data section comprises information identifying state data common to the one or more primitives for which data is stored in the two or more primitive sections; and
wherein the single state data section comprises information identifying state data common to the one or more primitives in each of the two or more primitive sections; and
store the primitive block in memory.
store the plurality of primitive blocks in memory.
Claim 19 of the present application differs from claim 19 of the patent application in that claim 19 of the present application is broader in scope than claim 19 of the patent application, thus encompasses that of the patent application.
Present Application #19/197,768 Claim 20
U.S. Patent #12,322,024 Claim 20
A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform the method as set forth in claim 1.
A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform the method as set forth in claim 1.
Allowable Subject Matter
Claims 1-20 would be allowable if the Double Patenting rejection set forth above may be overcome.
The following is a statement of reasons for the indication of allowable subject matter:
The present invention relates to a primitive block generators for storing primitives in a graphics processing system.
Prior art includes:
Yang et al. (US 2015/0348306)(cited in the Information Disclosure Statement (IDS) filed May 2, 2025) disclose a method of storing data in a graphics processing system (Figure 2 illustrates primitives received at geometry processing 206 of graphics processing unit (GPU) 202 of graphics processing system 200 to be stored in at least memory 2041), the primitive being formed by one or more vertices (see below) and being associated with state data that defines how the primitive is to be rendered (as noted below, state information (in header 502) describes how the primitives in the primitive block are to be rendered), the method comprising: adding the primitive to a primitive block based on at least the state data associated with the primitive ([0022] notes primitives received at geometry processing module 206 of GPU 202, [0023] notes allocation logic 218 of primitive block allocation module 216 to further compare an indication of a spatial position of a current primitive with corresponding indications of the spatial positions of open primitive blocks 2221, 2222, and 2223, then allocating the current primitive to the primitive block based on the result of the comparison, thus grouping similar primitives together as primitive blocks that have similar states as noted in [0025]), the primitive block (e.g. primitive blocks 2221, 2222, and/or 2223, further illustrated as primitive block 500 of Figure 5) comprising one or more primitive sections (e.g. considered “section” 504 comprising vertex data and “section” 506 comprising primitive indices) and a state data section (e.g. header 502), wherein each primitive section comprises data for one or more primitives (e.g. vertex data and primitive indices) and has one or more size constraints (e.g. a maximum number of vertices and/or primitives that may be included in a primitive block)([0028] notes vertex data 504 of primitive block 500 comprises data for each of the vertices of the primitives included in the primitive block 500, e.g. each of n vertices may include, for example, a set of coordinates in scene space, XYZ, to describe the position of the vertex, and a set of attributes to describe the appearance of the vertex, such as texture coordinates (U,V) and/or a base colour to apply to the vertex; and primitive index data 506 of primitive block 500 comprises a set of indices, e.g. three indices for triangular primitives, for each of the primitives included in the primitive block 500 to define which of the vertices make up each of the primitives; there is a maximum number of vertices, e.g. a vertex threshold, such as 64, 256, 256 of some other suitable amount, and/or a maximum number of primitives, e.g. a primitive threshold, such as 128, 512 or some other suitable amount, that may be included in a primitive block), and wherein the state data section comprises information identifying state data common to the one or more primitives in each of the one or more primitive sections ([0028] notes header 502 of primitive block 500 includes state information, such as depth compare mode, a blending state, a texture state, a primitive type, etc., to describe how the primitives in the primitive block are to be rendered); and storing the primitive block in memory (e.g. memory 2041,)([0028] notes primitive blocks are stored in a parameter memory, such as memory 2041); and
Mang et al. (US 10,269,091) disclose a system and method of generating primitive blocks, the method comprising sending vertex information indicating attributes of a vertex, vertex identifier specifying the identifier for the vertex, and a new vertex indicator indicating whether the vertex is a new vertex for that identifier to a primitive block generator, which stores vertex information for primitives in a given active primitive block and state information for non-active primitive blocks for storage in memory, and further transmits primitive block information, e.g. completed primitive blocks, for further processing, e.g. by fragment processing hardware (Figure 2, column 4, lines 39 thru column 5, lines 65).
Although the prior art of record discloses certain features of the claimed invention as outlined above, the prior art of record fails to teach or suggest, singly or combined, the limitations of independent claims 1, 19, and 20 as recited, more specifically, “…the primitive block comprising two or more primitive sections and a state data section, wherein each primitive section comprises data for one or more primitives and has one or more size constraints and wherein each primitive section comprises a primitive data sub-section and a vertex data sub-section, and wherein the state data section comprises information identifying state data common to the one or more primitives for which data is stored in the two or more primitive sections…” as recited.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, King Y. Poon can be reached at (571)272-7440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617
Prosecution Insights