CTNF 19/197,952 CTNF 86666 DETAILED ACTION This Office Action is a step of the reopen prosecution communication that was mailed out on 12/22/2025, responsive to communication(s) filed on 12/11/2025. 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 have been examined and are pending; claims 1, 8, and 15 are independent claims. Continued Examination Under 37 CFR 1.114 07-42-04 AIA A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 12/11/2025 has been entered. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claim 1-20 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-8 and 10-19, respectively, of Application No. 18/994047. Although, the conflicting claims are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the reference claims. This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented. The following claims are presented side by side for comparison. The comparison shows how the scoped independent claim 1 of the instant application is an obvious variation of the reference independent claim 1. The scope of the independent claims 8 and 15 of the instant application are an obvious variation of the reference claims 11, and 17, respectively. For example, while the reference independent claims 10 and 16, recites, “ partition map to define partitions ,” One of ordinary skill in the art would understand that the detail structure of the partition and mapping that is captured in the dependent claims, claims 11, and 17, respectively, that are captured in the scope of the independent claims 8 and 15 of the instant application . The dependent claims of the instant application are also subject to double patenting, over the claims of the reference, respectively. Instant Application 19/197952 Reference Application No. 18/994047 1. A logic circuitry package for a print cartridge comprising: an interface to communicate with a host print apparatus; a memory arrangement storing digital signature metadata to facilitate verification of associated signed data by the host print apparatus, the digital signature metadata comprising: a schema identifier field storing a schema version number for the host print apparatus to determine which schema to use; a key identifier field storing an identifier of a signing key for the host print apparatus to use for verification; a plurality of data block address fields, each storing an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed, wherein the plurality of data blocks include print apparatus operational parameters; and a plurality of data block length fields corresponding to the plurality of data blocks, each storing data indicating a length of the corresponding data block; and a logic circuit configured to: receive a read request from the host print apparatus; and transmit the digital signature metadata to the host print apparatus in response to the read request to allow the host print apparatus to selectively access and verify individual data blocks of the plurality of data blocks without requiring verification of all data blocks. 1. A logic circuitry package comprising an interface to communicate with a host, and a logic circuit comprising: a memory arrangement accessible by the logic circuit, the logic circuit being configured to cause digital signature metadata to be provided to the host to facilitate verification of associated signed data upon receiving a suitable request from the host, the digital signature metadata comprising: a schema identifier field feature to indicate a schema version number for the host to determine which schema to use; a key identifier field feature to indicate an identifier of a signing key for the host to use a correct key for the verification; a plurality of data block address fields, each data block address field of the plurality of data block address fields feature to indicate an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed; and a plurality of data block length fields corresponding to the plurality of data blocks, each data block length field of the plurality of data block length fields feature to indicate data indicating a length of the corresponding data block, wherein the logic circuit is configured to: receive a read request from the host; and transmit the digital signature metadata to the host in response to the read request. 8. A method for authenticating a print cartridge comprising: storing, in a memory arrangement of a logic circuitry package of the print cartridge, digital signature metadata to facilitate verification of associated signed data, the digital signature metadata comprising: a schema identifier field storing a schema version number; a key identifier field storing an identifier of a signing key; a plurality of data block address fields, each storing an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed, wherein the plurality of data blocks include print apparatus operational parameters; and a plurality of data block length fields corresponding to the plurality of data blocks, each storing data indicating a length of the corresponding data block; receiving, by a logic circuit of the logic circuitry package, a read request from a host print apparatus; and transmitting, by the logic circuit, the digital signature metadata to the host print apparatus in response to the read request to allow the host print apparatus to selectively access and verify individual data blocks of the plurality of data blocks without requiring verification of all data blocks. 10. A method for provisioning a logic circuitry package comprising a memory arrangement, the method comprising: retrieving, via a processing system: a signing key identifier; and signing data comprising: a device type identifier corresponding to the logic circuitry package; a logic circuit identifier for the logic circuitry package for a host to differentiate the logic circuitry package from other logic circuitry packages; a partition map to define partitions of a general use memory portion of the memory arrangement of the logic circuitry package; and data to be stored in a plurality of data blocks of the general use memory portion of the memory arrangement of the logic circuitry package as specified by digital signature metadata; concatenating, via the processing system, the signing data; computing, via the processing system, a digital signature over the concatenated signing data using a signing private key corresponding to the signing key identifier; and writing configuring the logic circuitry package to provide, via the processing system, the digital signature in response to a suitable host request from the general use memory portion of the memory arrangement of the logic circuitry package. 11. (Currently Amended) The method of claim 10, wherein the digital signature metadata is to facilitate verification of associated signed data, the digital signature metadata comprising: a schema identifier field feature to indicate a schema version number for the host to determine which schema to use; a key identifier field feature to indicate an identifier of a signing key for the host to use a correct key for the verification; a plurality of data block address fields, each data block address field of the plurality of data block address fields feature to indicate storing an address corresponding to a data block of a plurality of data blocks over which the digital signature is originally computed; and a plurality of data block length fields corresponding to the plurality of data blocks, each data block length field of the plurality of data block length fields feature to indicate storing data indicating a length of the corresponding data block. 15. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor of a print cartridge, cause the processor to: store, in a memory arrangement of a logic circuitry package of the print cartridge, digital signature metadata to facilitate verification of associated signed data, the digital signature metadata comprising: a schema identifier field storing a schema version number; a key identifier field storing an identifier of a signing key; a plurality of data block address fields, each storing an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed, wherein the plurality of data blocks include print apparatus operational parameters; and a plurality of data block length fields corresponding to the plurality of data blocks, each storing data indicating a length of the corresponding data block; receive a read request from a host print apparatus; and transmit the digital signature metadata to the host print apparatus in response to the read request to allow the host print apparatus to selectively access and verify individual data blocks of the plurality of data blocks without requiring verification of all data blocks . 16. A logic circuitry package comprising an interface to communicate with a controller, and a logic circuit comprising: a memory arrangement accessible by the logic circuit, the logic circuit being configured to provide to the controller, in response to at least one suitable request: a logic circuit identifier for the controller to differentiate the logic circuitry package from other logic circuitry packages, a partition map to define partitions of a general use memory portion of the memory arrangement, digital signature metadata to facilitate verification of associated signed data, specified data corresponding to the digital signature metadata, and a digital signature signed over data including a device type identifier corresponding to the logic circuitry package, the logic circuit identifier, the partition map, and the specified data; wherein the logic circuit is configured to, in response to at least one request from the controller; transmit to the controller, the logic circuit identifier, the partition map, the digital signature, the digital signature metadata, and/or other data, and the specified data corresponding to the digital signature metadata. 17. The logic circuitry package of claim 16, wherein the digital signature metadata comprises: a key identifier field feature to indicate an identifier of a signing key for the controller to use a correct key for the verification; a plurality of data block address fields, each data block address field of the plurality of data block address fields feature to indicate an address corresponding to a data block of a plurality of data blocks over which the digital signature is originally computed; and a plurality of data block length fields corresponding to the plurality of data blocks, each data block length field of the plurality of data block length fields feature to indicate storing data indicating a length of the corresponding data block. Additionally, the claim 1-20 of the instant application are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-13, respectively, of Application No. 19/697475. Although, the conflicting claims are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the reference claims. This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented. The following claims are presented side by side for comparison. The comparison shows how the scoped independent claim 1, 10 and 16 of the instant application are an obvious variation of the reference claims 1, 8 and 15, respectively. The dependent claims of the instant application are also subject to double patenting, over the claims of the reference, respectively. Instant Application 19/197952 Reference Application No. 19/697475 1. A logic circuitry package for a print cartridge comprising: an interface to communicate with a host print apparatus; a memory arrangement storing digital signature metadata to facilitate verification of associated signed data by the host print apparatus, the digital signature metadata comprising: a schema identifier field storing a schema version number for the host print apparatus to determine which schema to use; a key identifier field storing an identifier of a signing key for the host print apparatus to use for verification; a plurality of data block address fields, each storing an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed, wherein the plurality of data blocks include print apparatus operational parameters; and a plurality of data block length fields corresponding to the plurality of data blocks, each storing data indicating a length of the corresponding data block; and a logic circuit configured to: receive a read request from the host print apparatus; and transmit the digital signature metadata to the host print apparatus in response to the read request to allow the host print apparatus to selectively access and verify individual data blocks of the plurality of data blocks without requiring verification of all data blocks. 1. A logic circuitry package comprising an interface to communicate with a host, and a logic circuit comprising: a memory arrangement storing: a logic circuit identifier to differentiate the logic circuitry package from other logic circuitry packages, a partition map to define partitions of a general use memory portion of the memory arrangement, digital signature metadata to facilitate verification of associated signed data, specified data corresponding to the digital signature metadata, and a digital signature signed over data including a device type identifier corresponding to the logic circuitry package, the logic circuit identifier, the partition map, and the specified data; wherein the digital signature metadata comprises: a schema identifier field storing a schema version number for the host to determine which schema to use; a key identifier field storing an identifier of a signing key for the host to use a correct key for the verification; a plurality of data block address fields, each data block address field of the plurality of data block address fields storing an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed; and a plurality of data block length fields corresponding to the plurality of data blocks, each data block length field of the plurality of data block length fields storing data indicating a length of the corresponding data block, wherein the logic circuit is configured to: receive a read request from the host; and transmit the digital signature metadata, the logic circuit identifier, the partition map, the digital signature, and/or other data, and the specified data corresponding to the digital signature metadata to the host in response to the read request. 8. A method for authenticating a print cartridge comprising: storing, in a memory arrangement of a logic circuitry package of the print cartridge, digital signature metadata to facilitate verification of associated signed data, the digital signature metadata comprising: a schema identifier field storing a schema version number; a key identifier field storing an identifier of a signing key; a plurality of data block address fields, each storing an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed, wherein the plurality of data blocks include print apparatus operational parameters; and a plurality of data block length fields corresponding to the plurality of data blocks, each storing data indicating a length of the corresponding data block; receiving, by a logic circuit of the logic circuitry package, a read request from a host print apparatus; and transmitting, by the logic circuit, the digital signature metadata to the host print apparatus in response to the read request to allow the host print apparatus to selectively access and verify individual data blocks of the plurality of data blocks without requiring verification of all data blocks. 9. A method for provisioning a logic circuitry package comprising a memory arrangement, the method comprising: retrieving, via a processing system: a signing key identifier; and signing data comprising: a device type identifier corresponding to the logic circuitry package; a logic circuit identifier to differentiate the logic circuitry package from other logic circuitry packages; a partition map to define partitions of a general use memory portion of the memory arrangement of the logic circuitry package; and data to be stored in a plurality of data blocks of the general use memory portion of the memory arrangement of the logic circuitry package as specified by digital signature metadata; concatenating, via the processing system, the signing data; computing, via the processing system, a digital signature over the concatenated signing data using a signing private key corresponding to the signing key identifier; and writing, via the processing system, the digital signature to the general use memory portion of the memory arrangement of the logic circuitry package, wherein the digital signature metadata is to facilitate verification of associated signed data, the digital signature metadata comprising: a schema identifier field storing a schema version number for a host to determine which schema to use; a key identifier field storing an identifier of a signing key for the host to use a correct key for the verification; a plurality of data block address fields, each data block address field of the plurality of data block address fields storing an address corresponding to a data block of a plurality of data blocks over which the digital signature is originally computed; and a plurality of data block length fields corresponding to the plurality of data blocks, each data block length field of the plurality of data block length fields storing data indicating a length of the corresponding data block. 15. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor of a print cartridge, cause the processor to: store, in a memory arrangement of a logic circuitry package of the print cartridge, digital signature metadata to facilitate verification of associated signed data, the digital signature metadata comprising: a schema identifier field storing a schema version number; a key identifier field storing an identifier of a signing key; a plurality of data block address fields, each storing an address corresponding to a data block of a plurality of data blocks over which a digital signature is originally computed, wherein the plurality of data blocks include print apparatus operational parameters; and a plurality of data block length fields corresponding to the plurality of data blocks, each storing data indicating a length of the corresponding data block; receive a read request from a host print apparatus; and transmit the digital signature metadata to the host print apparatus in response to the read request to allow the host print apparatus to selectively access and verify individual data blocks of the plurality of data blocks without requiring verification of all data blocks . Allowable Subject Matter Claims 1-20 are considered allowable subject matter over PriorArt. The closest PriorArt, those are considered, Gindin (US 2003/0009662) is generally directed to a method for creating a proof of possession confirmation for inclusion by a certification authority into a digital certificate, the digital certificate for use by an end user, is disclosed. In an exemplary embodiment of the invention, the method includes receiving from the certification authority, in response to a certificate request by the end user, a plurality of data fields corresponding to a target host system, the end user, and a form of proof of identity possession by the end user. The content of the plurality of data fields is analyzed and the accuracy thereof is verified. If the plurality of data fields is verified as accurate, then a signed object is sent to the certification authority, the signed object comprising the proof of possession confirmation, Jeran, (US 2018/0046795) is generally directed to an invention for a stored digital signature of the consumable product; verifying the digital signature with a signature scheme that provides additional bit space in the signature in which host setting data is contained; retrieving the host setting data from the verification of the digital signature; and applying the host setting data to the host device, wherein the host device setting data comprises a setting for operation of the host device. The Examiner concludes that, none of Gindin, Jeran, nor any other art teaches or suggests, alone or in combination, the particular combination of steps or elements as recited in the independent claims 1, 8 and 15. Therefore, the independent claims 1, 8 and 15 are considered allowable subject matter over PriorArt. As to the dependent claims 2-7, 9-14, and 16-20, the claims are depending from allowable claims 1, 8 or 15, respectively, and are considered allowable subject matter over PriorArt. While the all claims, 1-20, are considered allowable subject matter over PriorArt, claims 1-20 are provisionally rejected, as addressed above, on the ground of nonstatutory double patenting. Applicant is suggested to submit a Terminal Disclaimer over the reference co-pending U.S. Applications, so that a notice of allowance can be issued. Conclusion 07-101 Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jahangir Kabir whose telephone number is (571) 270-3355. The examiner can normally be reached on 9:00- 5:00 Mon-Thu. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Luu Pham can be reached on (571) 270-5002. The fax number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center and the Private Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from Patent Center or Private PAIR. Status information for unpublished applications is available through Patent Center and Private PAIR for authorized users only. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. /JAHANGIR KABIR/ Primary Examiner, Art Unit 2439 Application/Control Number: 19/197,952 Page 2 Art Unit: 2439 Application/Control Number: 19/197,952 Page 3 Art Unit: 2439 Application/Control Number: 19/197,952 Page 4 Art Unit: 2439 Application/Control Number: 19/197,952 Page 5 Art Unit: 2439 Application/Control Number: 19/197,952 Page 6 Art Unit: 2439 Application/Control Number: 19/197,952 Page 7 Art Unit: 2439 Application/Control Number: 19/197,952 Page 8 Art Unit: 2439 Application/Control Number: 19/197,952 Page 9 Art Unit: 2439 Application/Control Number: 19/197,952 Page 10 Art Unit: 2439 Application/Control Number: 19/197,952 Page 11 Art Unit: 2439 Application/Control Number: 19/197,952 Page 12 Art Unit: 2439 Application/Control Number: 19/197,952 Page 13 Art Unit: 2439 Application/Control Number: 19/197,952 Page 14 Art Unit: 2439 Application/Control Number: 19/197,952 Page 15 Art Unit: 2439 Application/Control Number: 19/197,952 Page 16 Art Unit: 2439 Application/Control Number: 19/197,952 Page 17 Art Unit: 2439 Application/Control Number: 19/197,952 Page 18 Art Unit: 2439 Application/Control Number: 19/197,952 Page 19 Art Unit: 2439 Application/Control Number: 19/197,952 Page 20 Art Unit: 2439 Application/Control Number: 19/197,952 Page 21 Art Unit: 2439 Application/Control Number: 19/197,952 Page 22 Art Unit: 2439 Application/Control Number: 19/197,952 Page 23 Art Unit: 2439 Application/Control Number: 19/197,952 Page 24 Art Unit: 2439 Application/Control Number: 19/197,952 Page 25 Art Unit: 2439 Application/Control Number: 19/197,952 Page 26 Art Unit: 2439 Application/Control Number: 19/197,952 Page 27 Art Unit: 2439 Application/Control Number: 19/197,952 Page 28 Art Unit: 2439 Application/Control Number: 19/197,952 Page 29 Art Unit: 2439 Application/Control Number: 19/197,952 Page 30 Art Unit: 2439
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