Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
The certified copies of GB 2406250.7 and GB2406251.5 have been retrieved on 09/17/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/03/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities:
In Claim 1, “logic which comprises” is suggested to read “logic comprising”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“one or more geometry processing modules” in Claims 1, 2.
“a tiling front-end module” in Claims 1-6.
“a tiling back-end module” in Claims 1, 8, 9, and 11.
“a block generator module” in Claims 2 and 3.
“an accumulator module” in Claim 6.
“a control stream generator module” in Claim 9.
“one or more geometry processing modules” in Claim 20.
“a tiling front-end module” in Claim 20.
“a tiling back-end module” in Claim 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For the sake of further prosecution, Examiner will treat “one or more geometry processing modules”, “a tiling front-end module”, “a tiling back-end module”, “a block generator module”, “an accumulator module”, and “a control stream generator module” all as hardware or software configured to perform their respective recited functions/operations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-10, and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rollingson et al. (US 20190108671 A1), hereinafter referenced as Rollingson, in view of Wang et al. (US 20150379672 A1), hereinafter referenced as Wang.
Regarding Claim 1, Rollingson discloses a graphics processing unit configured to process a sequence of primitives using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising geometry processing logic (Rollingson: [0045-0046, 0048-0070, Fig. 5], discloses a system, 500 in Fig. 5, <interpreted as a graphics processing unit> implements tile-based rendering <process sequence of primitives, using a subdivided rendering space> and comprises geometry processing logic, see 502 and 504, geometry pipelines as shown below) which comprises:
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a plurality of geometry pipelines configured to receive batches of primitives of the sequence of primitives (Rollingson: [0026-0032, 0048-0070, Fig. 5], discloses two geometry pipelines configured to receive geometry data divided into groups <batches of a sequence of primitives that make up a scene>), wherein each of the geometry pipelines comprises:
one or more geometry processing modules configured to perform one or more geometry processing functions on the primitives of a batch of primitives received at the geometry pipeline (Rollingson: [0038, 0048-0070, Fig. 5], discloses CCT modules at 512 and 514, that cull/clip/transform <performs geometry processing functions> the input geometry data received at the geometry pipeline <primitives of a batch of primitives>),
and a tiling back-end module configured to: receive the tile-primitive indications determined by the plurality of geometry pipelines, and for each of the tiles for which a tile-primitive indication is received, include indications of the primitives that are present within that tile in a control stream for that tile in an order in accordance with an order of the primitives within the sequence of primitives (Rollingson: [0075-0087, Figs. 4-5], discloses a tile arbiter and tiling pipelines in parallel <tiling back end module> and a tiling engine that creates a list <control stream> of primitives for each tile, based on the primitive position data in the primitive position blocks received from the geometry processing pipeline, processing in an order based on the geometry group number within the scene geometry, see [Fig. 4] below).
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Rollingson teaches geometry pipelines and determining tile-primitive indications through primitive position data, masks, and bounding volumes, however, Rollingson does not explicitly disclose the language of
… and a tiling front-end module configured to determine, for each tile of a set of one or more tiles, one or more tile-primitive indications indicating which of the primitives of the batch of primitives received at the geometry pipeline are present within that tile;
However, Wang discloses
… and a tiling front-end module configured to determine, for each tile of a set of one or more tiles, one or more tile-primitive indications indicating which of the primitives of the batch of primitives received at the geometry pipeline are present within that tile (Wang: [0051-0061], see below, discloses a binning pass 351 <the front-end tiling module> that stores, for each tile of a scene divided into multiple tiles, a list of primitives that touch the tile <one or more tile-primitive indications which of the primitives of the scene received at the pipeline are present within the tile>);
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by Rollingson by front-end binning as taught by Wang. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification for computational efficiency.
Regarding Claim 20, it recites limitations similar to Claim 1. As shown in the rejection, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose
A non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a graphics processing unit configured to process a sequence of primitives using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising geometry processing logic (Rollingson: [0009], discloses a non-transitory computer-readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a system; [0046], discloses a graphics processing unit <comprises geometry processing logic> configured to process primitives using tile-based rendering) which comprises: …
Regarding Claim 18, Rollingson discloses
A method of processing a sequence of primitives in a graphics processing unit configured to use a rendering space which is sub-divided into a plurality of tiles, the method comprising implementing a geometry processing phase of a rendering process, wherein the geometry processing phase (Rollingson: [0006], discloses a method; [0045-0046, 0048-0070, Fig. 5], discloses implementing tile-based rendering <process sequence of primitives, using a subdivided rendering space> and comprises geometry processing logic, see 502 and 504, geometry pipelines as shown below) comprises:
receiving batches of primitives of the sequence of primitives at a plurality of geometry pipelines (Rollingson: [0026-0032, 0048-0070, Fig. 5], discloses two geometry pipelines receiving geometry data divided into groups <batches of a sequence of primitives that make up a scene>); at each of the geometry pipelines:
performing one or more geometry processing functions on the primitives of a batch of primitives received at the geometry pipeline (Rollingson: [0038, 0048-0070, Fig. 5], discloses CCT modules at 512 and 514, that cull/clip/transform <performs geometry processing functions> the input geometry data received at the geometry pipeline <primitives of a batch of primitives>),
receiving the tile-primitive indications determined by the plurality of geometry pipelines at a tiling back-end module (Rollingson: [0074-0079], discloses a tile arbiter receiving the primitive position blocks <includes the tile-primitive indications> and forwards them to their determined tiling pipelines, ensuring the correct order);
and for each of the tiles for which a tile-primitive indication is received at the tiling back-end module, including indications of the primitives that are present within that tile in a control stream for that tile in an order in accordance with an order of the primitives within the sequence of primitives (Rollingson: [Figs. 4-5, 0074-0079], discloses the tiling engine creates a list <control stream> of each tile and the primitives it contains, using the primitive position data in the primitive position blocks received from the geometry processing pipeline, processing in an order based on the geometry group number within the scene geometry).
Rollingson teaches geometry pipelines and determining tile-primitive indications through primitive position data, masks, and bounding volumes, however, Rollingson does not explicitly disclose the language of
and determining, at a tiling front-end module of the geometry pipeline, for each tile of a set of one or more tiles, one or more tile-primitive indications indicating which of the primitives of the batch of primitives received at the geometry pipeline are present within that tile;
However Wang discloses
and determining, at a tiling front-end module of the geometry pipeline, for each tile of a set of one or more tiles, one or more tile-primitive indications indicating which of the primitives of the batch of primitives received at the geometry pipeline are present within that tile (Wang: [0051-0061], see below, discloses a binning pass 351 <the front-end tiling module> that stores, for each tile of a scene divided into multiple tiles, a list of primitives that touch the tile <one or more tile-primitive indications which of the primitives of the scene received at the pipeline are present within the tile>);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the method disclosed by Rollingson by front-end binning as taught by Wang. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification for computational efficiency..
Regarding Claim 19, it recites limitations similar to Claim 18. As shown in the rejection, the combination of Rollingson and Wang disclose the method of Claim 18. The combination of Rollingson and Wang further disclose
A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method as set forth in claim 18 to be performed when the code is run (Rollingson: [0009], discloses a non-transitory computer-readable storage medium having stored thereon a computer readable description <code> able to execute a method)
Regarding Claim 2, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose wherein for each of the geometry pipelines:
said one or more geometry processing modules of the geometry pipeline comprises a block generator module configured to generate primitive blocks, wherein each of the primitive blocks includes primitive data representing a set of one or more primitives (Rollingson: [0039], discloses for each geometry pipeline, a geometry block generator that is configured to generate geometry blocks, wherein each geometry block comprises primitive data at least one primitive),
and the one or more tile-primitive indications for a tile determined by the tiling front-end module of the geometry pipeline comprise
a tile-primitive mask for each of the primitive blocks indicating which of the primitives of the primitive block are present within that tile (Rollingson: [0041], discloses a mask <tile-primitive mask> for each geometry block identifying which primitives of the geometry block fall within a tile).
Regarding Claim 7, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose wherein the geometry pipelines are configured to
operate in parallel on different batches of primitives (Rollingson: [Fig. 5], illustrates geometry pipelines operating in parallel on split scene geometry data <different batches of primitives>).
Regarding Claim 8, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose wherein
each of the batches of primitives is associated with an indication of its position according to the order of the primitives within the sequence of primitives (Rollingson: [0030], discloses each geometry group is associated with a geometry group number which indicates the order of that geometry group relative to the other geometry groups),
and wherein the tiling back-end module comprises a primitive ordering arbiter configured to: receive the tile-primitive indications determined by the plurality of geometry pipelines; and order the received tile-primitive indications in accordance with the indications of the positions of the batches of primitives (Rollingson: [0006; 0042-0043], discloses the tiling back end module comprising an arbiter <primitive ordering arbiter> that receives primitive position blocks <tile-primitive indications> associated with the same geometry of the geometry block <batch> from the different pipelines and forward them in an order in accordance based on the geometry group number).
Regarding Claim 9, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose wherein the tiling back-end module comprises:
a plurality of tile pipelines (Rollingson: [Fig. 5], illustrates a plurality of tile pipelines);
and a tile arbiter configured to determine which of the tile pipelines to send each of the tile- primitive indications to, and to send each of the tile-primitive indications to the tile pipeline determined for that tile-primitive indication (Rollingson: [Fig. 5], illustrates an arbiter; [0074-0076], discloses an arbiter that determines which pipeline to send each of the primitive position blocks <interpreted as a tile-primitive indication> to, and sends each of the primitive position blocks <interpreted as a comprising tile-primitive indication> to the determined tile pipeline);
wherein each of the tile pipelines comprises a control stream generator module configured to, for each of the tiles for which a tile-primitive indication is received at the tile pipeline, include in a control stream for that tile, indications of primitives that are present within that tile (Rollingson: [0043, 0077], discloses each tiling pipeline comprises a tiling engine <control stream generation module> configured to generate a list <control stream> for each tile, based on the position primitive block received from the geometry processing pipeline <tile-primitive indication>, indicating which primitives are present within that tile).
Regarding Claim 10, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 9. The combination of Rollinson and Wang further disclose wherein the tile arbiter is configured to
determine which of the tile pipelines to send each of the tile-primitive indications to using either a round robin scheme or a load balancing scheme (Rollingson: [0099], discloses the tile arbiter selecting tile pipelines to receive the primitive position block in a round robin manner <scheme>).
Regarding Claim 12, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose wherein the geometry processing logic further comprises
splitting logic configured to: receive the sequence of primitives; split the sequence of primitives into the batches of primitives, wherein each batch of primitives is associated with an indication of its position according to the order of the primitives within the sequence of primitives; and for each of the batches, send that batch of primitives to one of the geometry pipelines with the indication of its position according to the order of the primitives within the sequence of primitives (Rollingson: [0030-0033, 0043], discloses obtaining geometry data of vertices <sequence of primitives> and dividing it into a plurality of geometry groups <batches of primitives>, each group is assigned a geometry group number/primitive interleave marker indicated the order of that geometry group relative to other geometry groups <indication of its position according to the order of the primitives within the sequence of primitives> then, a subset of the geometry groups is provided to each geometry pipeline <each patch is sent to one of the pipelines> while being associated with their geometry group number/primitive interleave marker; [0093], discloses switching logic processing sequencing, side band, and primitive position data).
Regarding Claim 13, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose wherein the one or more geometry processing modules comprise
one or more of: a vertex data master module, a primitive processing module, a clipping module, a vertex block generator module, and a vertex compression module (Rollingson: [Fig. 5], illustrates the geometry processing modules of the geometry pipelines comprise a cull/clip/transform module <interpreted as a clipping module or a primitive processing module>, a geometry block generator <interpreted as a vertex block generator module>, a compression engine to compress the geometry blocks <interpreted as vertex compression module>).
Regarding Claim 14, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose wherein the graphics processing unit comprises
fragment processing logic configured to render an image using data stored in a buffer by the geometry processing logic (Rollingson: [0001-0002], discloses rendering a scene <a displayed scene is interpreted as an image> using data stored in a buffer that has been processed through a tile-based rendering process <geometry processing logic>; [0011], discloses the method implemented by program code).
Regarding Claim 15, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 14. The combination of Rollingson and Wang further disclose wherein the data stored in the buffer comprises
primitive data which results from performing the geometry processing functions at the one or more geometry processing modules of each of the geometry pipelines (Rollingson: [0067-0068], discloses a buffer in the geometry pipeline storing primitive position blocks <primitive data> output from the geometry block processing modules that perform geometry processing functions in each geometry processing pipeline, see [Fig. 5]).
Regarding Claim 16, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 14. The combination of Rollingson and Wang further disclose wherein the data stored in the buffer comprises
the control streams for the tiles of the rendering space (Rollingson: [0067-0068, 0087], discloses a buffer stores primitive blocks which identify the position of one or more primitives to be tiled <interpreted as control stream>).
Regarding Claim 17, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 1. The combination of Rollingson and Wang further disclose wherein
the primitives represent objects in a scene to be rendered (Rollingson: [0001-0002], discloses primitives are geometric data <representing objects> to be rendered in a scene).
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Rollingson and Wang in view of Larsen et al. (US 20230388651 A1), hereinafter referenced as Larsen.
Regarding Claim 3, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 2. The combination of Rollingson and Wang further disclose wherein for each of the geometry pipelines:
the block generator module of the geometry pipeline is configured to determine a bounding box for each of the primitive blocks, wherein the bounding box for a primitive block indicates a region of the rendering space which wholly encompasses all of the primitives in the primitive block (Rollingson: [0042, 0053, 0074], discloses determining a primitive position block for each geometry block, where each geometry block contains at least one primitive, and for each primitive position block, there is primitive position data comprising a bounding box that wholly encompasses a primitive of a geometry block),
and the tiling front-end module of the geometry pipeline is configured to (Wang: [Fig. 3], illustrates a tiling front end module)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by the combination of Rollingson and Wang by having a front end tiling module as further taught by Wang. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification computational efficiency.
The combination of Rollingson and Wang do teach a tiling front end module for binning (Wang: [Fig. 3]) and a tiling engine to create lists of primitives in a tile within the rendering space (Rollingson: [0042, 0064-0065]), but the combination of Rollingson and Wang fail to explicitly disclose
determine, for each tile of the rendering space in the bounding box for a primitive block, which of the primitives of that primitive block are present within that tile
However, Larsen discloses
determine, for each tile of the rendering space in the bounding box for a primitive block, which of the primitives of that primitive block are present within that tile (Larsen: [0013, 0228-0244], discloses determining, for each tile of the rendering space in a draw call, which primitives of that draw call are present within the tile with a primitive list, see Fig. 3 below where each draw call is interpreted as a primitive block including a bounding box represented by dashed lines)
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by the combination of Rollingson and Wang by building primitive lists using draw calls as taught by Larsen. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification for computational efficiency.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Rollingson, Wang, and Larson in view of Brigg et al. (US 20210110510 A1), hereinafter referenced as Brigg.
Regarding Claim 4, the combination of Rollingson, Wang, and Larsen disclose the graphics processing unit of Claim 3. The combination of Rollingson, Wang, and Larsen further disclose wherein the tiling front-end module of each of the geometry pipelines comprises
bounding box for a primitive block (Larsen: [Fig. 3], discloses draw calls, see the dashed lines wholly encompassing sets of primitives, <interpreted as bounding box for a primitive block>)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by the combination of Rollingson and Wang by using draw calls as taught by Larsen. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification for computational efficiency.
The combination of Rollingson, Wang, and Larsen fail to explicitly disclose
region generation logic configured to determine, for each tile of the rendering space in the bounding box for a primitive block, a tile-primitive association indication for each of the primitives of the primitive block that has a primitive bounding box that is present within that tile, wherein the primitive bounding box for a primitive indicates a region of the rendering space which wholly encompasses that primitive
However, Brigg discloses
region generation logic configured to determine, for each tile of the rendering space in the scene, a tile-primitive association indication for each of the primitives of the primitive block that has a primitive bounding box that is present within that tile, wherein the primitive bounding box for a primitive indicates a region of the rendering space which wholly encompasses that primitive (Briggs: [0088-0089, Fig. 6], discloses top level sorting logic, see [Fig. 6] below, where for each tile in the rendering space in the scene, it is determined <tile primitive indication> for the primitive having a bounding box present in the tile, wherein the primitive bounding box for a primitive indicated a region of rendering space defined by the maximum and minimum X and Y coordinates of the vertices <wholly encompasses the primitive>, the primitive 610 in [Fig. 6] is determined to be in all four regions <tiles> because of its bounding box, even though the actual primitive is present in three regions).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by the combination of Rollingson, Wang, and Larson by identifying tiles within a bounding box as taught by Brigg. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification for a computationally inexpensive method of determining where primitives may be present within tiles.
Regarding Claim 6, the combination of Rollingson, Wang, Larsen, and Brigg disclose the graphics processing unit of Claim 4. The combination of Rollingson, Wang, Larsen, and Brigg disclose(s) wherein the tiling front-end module of each of the geometry pipelines further comprises
an accumulator module configured to: receive tile-primitive association indications relating to a tile and relating to primitives of a primitive block (Brigg: [Fig. 3, 0065-0074], illustrates tiling engine <accumulator module> receiving geometry data and transforms it into a list relating to tiles and primitives within a primitive block);
and determine the tile-primitive mask for the primitive block indicating which of the primitives of the primitive block are present within the tile (Brigg: [0065-0074], discloses storing a list <mask> for each primitive block indicating which of the primitives within the primitive block are in the macro region <tile>, see [Fig. 13] below).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by the combination of Rollingson, Wang, Larsen, and Brigg by determining primitive lists for each primitive block as further taught by Brigg. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification for bandwidth savings and cache locality.
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Rollingson, Wang, Larson, and Brigg in view of Barone et al. (US 20090046098 A1), hereinafter referenced as Barone.
Regarding Claim 5, the combination of Rollingson, Wang, Larsen, and Brigg disclose the graphics processing unit of Claim 4. The combination of Rollingson, Wang, Larsen, and Brigg further disclose wherein the tiling front-end module of each of the geometry pipelines further comprises
tiling refinement logic configured to: receive the determined tile-primitive association indications determined by the region generation logic of that geometry pipeline (Brigg: [Fig. 3, Abs], illustrates the tiling engine as a front end tiling module in the geometry processing pipeline, where the lower level sorting unit 322, receives the determined identifiers outputted by the top level sorting unit 320);
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determine, for each of the received tile-primitive association indications whether the primitive to which the tile-primitive association indication relates is present within the tile to which the tile-primitive association indication relates (Brigg: [0100], discloses and the lower-level sorting logic 410 may be configured to use a near perfect or perfect tiling method to determine whether a primitive, at least partially, falls within a sub-region or lower level region <within the tile> identified in the top level sorting);
and remove a tile-primitive association indication in response to a primitive being output to the rasterization logic (Brigg: [0107], discloses removing the primitive identifiers in the queue in response to a primitive being output to rasterization logic).
the primitive to which the tile-primitive association indication relates (Brigg: [0157], discloses a primitive to which the primitive identifier relates)
the tile to which the tile-primitive association indication relates (Brigg: [0157], discloses a primitive to which the primitive identifier relates)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by the combination of Rollingson, Wang, Larsen, and Brigg by fine level sorting as further taught by Brigg. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to optimize computational efficiency by using a hierarchical multi-phase sorting method allowing for minimal mistakes and less memory use.
The combination of Rollingson, Wang, Larsen, and Brigg fail to disclose
… in response to determining that the primitive to which the tile-primitive association indication relates is not present within the tile to which the tile-primitive association indication relates
However, Barone discloses
Geometric culling in response to determining that the primitive (Barone: [0058-0089], discloses not binning, or geometric culling, in response a primitive not being present in the candidate tile, see [Fig. 5] below)
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by the combination of Rollingson, Wang, Larsen, and Brigg by primitive-tile testing and culling indications as taught by Barone. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification for precise identifications of primitives within tiles.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Rollingson and Wang in view of Livesley (GB 2611372 A), hereinafter referenced as Livesley.
Regarding Claim 11, the combination of Rollingson and Wang disclose the graphics processing unit of Claim 9. The combination of Rollingson and Wang further disclose wherein the tiling back-end module comprises wherein
all of the tile pipelines (Rollingson: [Fig. 5], discloses all of the tiling pipelines are configured to receive input from the GTA) configured to receive input from the GTA
The combination of Rollingson and Wang teach on-chip memory, buffers, and memory storing tiling data but fail to explicitly disclose
a tail pointer cache configured to store, for each of the tiles of the rendering space, an indication of the location in the control stream for the tile of the data that is most-recently written to the control stream, wherein all of the tile pipelines are configured to read and write data for the control streams of all of the tiles of the rendering space from and to the tail pointer cache
However, Livesley discloses
wherein the system is configured to read and write data for the control streams of all of the tiles of the rendering space from and to the tail pointer cache (Livesley: [0017], a system configured to read and write data for a control stream for each tile of the rendering space from and to a memory; [0110, 0130-0132], discloses the memory may further include a tail pointer cache).
a tail pointer cache configured to store, for each of the tiles of the rendering space, an indication of the location in the control stream for the tile of the data that is most-recently written to the control stream (Livesley: [0110], discloses a tail point cache storing for each tile of the control lists being written by the slave unit <where a set of tiles is interpreted as a rendering space>, a PIM number of a primitive <location of a primitive in respect to the other primitives> that was most recently written to the tail pointer cache, keeping track of the current PIM for each tile <in the control stream for the tile of data that is most recently written to the control stream>),
It is noted that a standard tail pointer cache would be capable of storing, for each of the tiles of the rendering space, an indication of the location in the control stream for the tile of the data that is most-recently written to the control stream. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the graphics processing unit disclosed by the combination of Rollingson and Wang by using a tail pointer cache as taught by Livesley . One of ordinary skill in the art would have been motivated to make this modification for optimized graphics processing with O(1) append operations and reduced latency, enhancing performance and efficiency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kurokawa et al. (US 20240362192 A1) discloses an LRU cache.
Cho et al. (US 20190197760 A1) discloses tile lists and binning.
Bader et al. (US 20090326888 A1) discloses two phase, broad and narrow phases, collision detection.
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/I.O./Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618
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