DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
Examiner states for the record that no Information Disclosure Statement is presently filed in this application. All references cited in the parent application have been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-17 of U.S. Patent No. 12,373,355 contains every element of claims 1-19 of the instant application and as such anticipates claims 1-19 of the instant application.
Claim Correspondence
Instant Application
U.S. Patent No. 12,373,355
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“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 9, 11-14, 16, 17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raikin et al. (Pub. No. US 2016/0077946).
Claim 1:
Raikin et al. disclose a network adapter, comprising:
a host interface, to communicate with a host over a peripheral bus [fig. 1 – host interface];
a network interface, to send and receive packets to and from a network for the host [fig. 1 – network interface];
packet processing circuitry, to process the packets [fig. 1 – packet processing]; and
Translation-as-a-Service (TaaS) circuitry, which is integrated in the network adapter and is to:
receive from a requesting device a request to translate an input address into one or more requested addresses in a requested address space [par. 0040 – “Applications 38 can thus invoke, inter alia, remote direct memory access (RDMA) read and write operations, which cause NIC 34 to read and write data directly between addresses in memory 30 and network 24.”];
translate the input address into the one or more requested addresses [par. 0041 – “Typically, the memory ranges for at least some of these data transfer operations are specified in terms of virtual memory addresses, which are translated by NIC 34 into physical addresses in memory 30.”]; and
return a translation-as-a-service response message comprising values of the one or more requested addresses to the requesting device [par. 0040 – Data is read and returned. (“Applications 38 can thus invoke, inter alia, remote direct memory access (RDMA) read and write operations, which cause NIC 34 to read and write data directly between addresses in memory 30 and network 24.”)].
Claim 3 (as applied to claim 1 above):
Raikin et al. disclose,
wherein the TaaS circuity is to receive a translation request specifying an input address for which no translation exists, and to respond to the translation request with a translation response indicating that no translation exists [par. 0038 – “Typically, the virtual memory space that is allocated by operating system 40 to applications 38 can exceed the actual amount of space available in memory 30. A memory management unit (MMU) 42 therefore detects and notifies the operating system when page faults occur. The operating system swaps pages 48 of application data 46 into memory 30 when they are needed and out to one or more swap devices 36 when they are not. Operating system 40 updates a page table 50 to indicate respective locations of pages 48 of virtual memory that are currently present in memory 3 0 and to invalidate pages that are swapped out.”].
Claim 4 (as applied to claim 1 above):
Raikin et al. disclose,
wherein the request specifies a requested size, and wherein the TaaS circuitry is to return, in the translation-as-a-service response message, a memory range having the requested size [par. 0040 – Data is having a size according to the request is read and returned. (“Applications 38 can thus invoke, inter alia, remote direct memory access (RDMA) read and write operations, which cause NIC 34 to read and write data directly between addresses in memory 30 and network 24.”)].
Claim 9 (as applied to claim 1 above):
Raikin et al. disclose,
wherein the one or more requested addresses comprise one of (i) a Virtual Address (VA), (ii) a Physical Address (PA) and (iii) a Machine Address (MA) [par. 0041 – “Typically, the memory ranges for at least some of these data transfer operations are specified in terms of virtual memory addresses, which are translated by NIC 34 into physical addresses in memory 30.”].
Claim 11 (as applied to claim 1 above):
Raikin et al. disclose,
wherein the input address points to one of (i) a contiguous memory range and (ii) a pattern of memory addresses [par. 0041 – “Typically, the memory ranges for at least some of these data transfer operations are specified in terms of virtual memory addresses, which are translated by NIC 34 into physical addresses in memory 30.”].
Claim 12 (as applied to claim 1 above):
Raikin et al. disclose,
wherein the request is received in response to an On-Demand Paging (ODP) page-fault notification in which the network adapter notifies the requesting device of an unmapped memory page, the request requesting an input address to which the unmapped memory page is to be mapped [par. 0026 – “The above-mentioned U.S. Pat. No. 8,255,475 describes an I/O device, such as a network interface controller (NIC), which responds to a page fault in handling an incoming data packet by transmitting a response packet over the network to the source of the data packet so as to cause the source to refrain from transmitting further data packets while the page fault is serviced.”].
Claim 13 (as applied to claim 1 above):
Raikin et al. disclose,
wherein the request specifies a Virtual Address (VA) in a logical volume defined on a storage the request requesting a corresponding address on the storage device [par. 0041 – “Typically, the memory ranges for at least some of these data transfer operations are specified in terms of virtual memory addresses, which are translated by NIC 34 into physical addresses in memory 30.”].
Claim 14 (as applied to claim 1 above):
Raikin et al. disclose,
wherein the request requests translation of a Virtual Address (VA) into a Physical Address (PA) responsively to receiving a storage command of a remote storage access protocol, the command specifying the VA [par. 0041 – “Typically, the memory ranges for at least some of these data transfer operations are specified in terms of virtual memory addresses, which are translated by NIC 34 into physical addresses in memory 30.”].
Claim 16 (as applied to claim 1 above):
Raikin et al. disclose,
wherein the request requests translation of the input address into a Machine Address (MA) [par. 0041 – “Typically, the memory ranges for at least some of these data transfer operations are specified in terms of virtual memory addresses, which are translated by NIC 34 into physical addresses in memory 30.”].
Claim 17:
Claim 17, directed to a method, is rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis.
Claim 19 (as applied to claim 17 above):
Claim 19, directed to a method, is rejected for the same reasons set forth in the rejection of claim 3 above, mutatis mutandis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raikin et al. (Pub. No. US 2016/0077946) as applied to claim 1 above, and further in view of Wigmore et al. (Pub. No. US 2021/0216215).
Claim 8 (as applied to claim 1 above):
Raikin et al. disclose all the limitations above but do not specifically disclose,
wherein, in addition to returning the values of the one or more requested addresses, the TaaS circuitry is to further return metadata corresponding to the one or more requested addresses.
In the same field of endeavor, Wigmore et al. disclose,
wherein, in addition to returning the values of the one or more requested addresses, the TaaS circuitry is to further return metadata corresponding to the one or more requested addresses [par. 0144 – “t may be determined that one or more of the data structures of storage metadata 722 does not have current information (or no information) about the specified logical storage device and/or location. If such a determination is made, SSI 716 may send one or more read requests 1002 (e.g., RDMA read requests) directly to global memory 640 for current metadata concerning the data of the read operation. Such requests may be configured as atomic operations to lock the memory locations of the metadata (e.g., portions of 62, 72, 72′, 82 and 300”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Raikin et al. to include reading metadata, as taught by Wigmore et al., in order to keep information about a logical storage device and/or location current.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shpiner et al. (Pub. No. US 2019/0173810) disclose, “In the present embodiment, the memory range for at least some RDMA requests is assumed to be specified in terms of virtual memory addresses, which are translated by network adapter 36 into machine addresses (i.e., physical addresses) in system memory 44, as described hereinbelow” [par. 0035]
Beecroft et al. (Pub. No. US 2004/0221128) disclose, “As can be seen from the above, the network interface described above includes a memory management function for translating virtual addresses into physical addresses, which provides advantages not previously available to computer systems. In particular significant reductions in the latency of the network can be achieved as memory access is facilitated, but remains secure, without intervention by the operating system. The present invention is particularly suited to implementation in areas such as weather prediction, aerospace design and gas and oil exploration where high performance computing technology is required to solve the complex computations employed. Moreover, by compressing the virtual addresses describing the virtual address space, the memory space taken up by the address translation processes can be significantly reduced whilst still supporting the adoption of 64 bit virtual addresses whereby the latency of the computer network can be kept to a minimum.” [par. 0045]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
30 May 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139
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