Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lo (US Pub. No. 20200177522) in view of Sabih (US Pat. No. 7310396).
As to claim 1, Lo discloses a serializer (10GBASE-R serializer 2840 on a transmit path from MAC 2836 and SGMII serializer 2852 on a transmit path from MAC 2854, Fig. 28A, para. 0140) for a physical layer interface (SERDES connecting MAC 1036 and PHY 1024, Fig. 10, para. 0100) of an electronic device (network-interface integrated circuits containing MAC, PHY, and SERDES circuitry, Figs. 10 and 28A, paras. 0100 and 0140), comprising:
a serializing module (10GBASE-R SERDES 1140, Fig. 11A, para. 0102), having a serial operating frequency (SERDES operating at the higher 10GBASE-R rate, Fig. 11A, paras. 0096–0102), for converting (serializing the signal, Fig. 11A, para. 0102) a data packet sequence (data frames generated by the MAC and presented to the reconciliation sublayer and interface, para. 0096) transmitted in parallel (XGMII output supplied by MAC 1136 to SERDES 1140, Fig. 11A, para. 0102) to a dataflow transmitted in serial (serialized signal transmitted from SERDES 1140 to SERDES 1144, Fig. 11A, para. 0102); and
a data up-conversion processing module (replicating circuit 1126 converting lower-speed MII data into higher-speed XGMII data according to the ratio of the high speed to the low speed, Fig. 11A, paras. 0098 and 0101), comprising:
a frequency division unit (Lo’s clock-divider circuit 1526 divides a recovered high-speed clock by an integer T to produce a lower-frequency clock, Fig. 15, paras. 0110–0112), electrically connected to a media access control block (Lo’s divider establishes a lower clock for a slower data path, Lo’s MAC operates at the lower speed relative to the PHY, Figs. 15, 25, and 28A, paras. 0110–0112, 0137, and 0140) and the serializing module (Lo’s divider derives the lower-path clock from the high-speed-path clock, while Lo’s serializing module operates in that high-speed path, thereby placing the divider and serializing module within the same operative clock and data-conversion circuit, Figs. 11A and 15, paras. 0102 and 0110–0112), for receiving the serial operating frequency (clock-divider circuit 1526 receives the recovered clock associated with the high-speed path, Fig. 15, paras. 0110–0112) and generating a device operating frequency based on the serial operating frequency (divider 1526 divides the recovered high-speed clock by integer T to generate the lower-frequency slow-path clock, Fig. 15, paras. 0110–0112), wherein the device operating frequency is provided to the media access control block (Lo teaches synchronizing the slow-path clock to the high-speed-path clock at a fixed ratio and operating the MAC more slowly than the PHY, Figs. 15, 25, and 28A, paras. 0111–0112, 0137, and 0140), and the device operating frequency is less than the serial operating frequency (Lo’s divider 1526 divides the recovered clock by an integer greater than two and produces an exemplary 31.25 MHz slow-path clock from high-speed clocks of 5.625 GHz, 2.8125 GHz, or 1.40625 GHz, Fig. 15, paras. 0110–0112);
electrically connected to the media access control block (Lo’s transmit FIFO 2510 receives slow data from the slower-operating MAC, Fig. 25, para. 0137) and the serializing module (Lo’s FIFO 2510 precedes PHY transmit path 2516, Lo, Fig. 25, para. 0137), for receiving the data packet sequence (Lo’s slow MAC data is queued into transmit FIFO 2510, Fig. 25, para. 0137) from the media access control block (slow data supplied by Lo’s lower-speed MAC to transmit FIFO 2510, Fig. 25, para. 0137);
wherein the data packet sequence comprises a plurality of non-repeated data packets (the original successive data frames generated by Lo’s MAC before rate adaptation constitute non-repeated data packets because replication is subsequently performed by the distinct replicating circuit 1126, paras. 0095–0101), and the dataflow comprises repeated data packets (“data packets” encompasses the repeated frame-data units carried in the physical-layer dataflow and does not require repetition of an independently framed packet having a separately repeated start delimiter; Lo’s replicating circuit 1126 replicates lower-speed data according to the ratio of the high speed to the low speed to form the higher-speed XGMII output and expressly provides replication factors of 1,000, 500, or 250, Fig. 11A, paras. 0098 and 0101).
Sabih discloses, what Lo lacks, a plurality of asynchrony register units (Sabih’s asynchronous FIFO 500 includes two parallel input-register branches formed by input registers 517 and 519, multiplexer 521, associated locations of shift register 523, and clock-comparison circuit 533, Figs. 5A–5B, col. 5, lines 15–32 and 55–65);
wherein each of the asynchrony register units receives the serial operating frequency (each register unit includes the respective input register 517 or 519, corresponding shift-register storage in register 523, and shared clock-comparison circuitry 533, which receives faster output clock CLK322 and controls transfer and output of the data in the faster clock domain, Figs. 5A–5B, col. 5, lines 15–32 and 55–65 and col. 6, lines 1–23) and an output operating frequency from the media access control block (each register unit receives its lower-domain data through input register 517 or 519 according to input clock CLK156 and divided clock CLK156/2, which corresponds to the operating frequency associated with the lower-speed source, Figs. 5A–5B, col. 5, lines 15–25);
based on the serial operating frequency (shift register 523 shifts out data on rising edges of faster output clock CLK322, Figs. 5A–5B, col. 5, lines 43–50 and col. 6, lines 13–23);
based on the output operating frequency (Sabih’s input registers 517 and 519 capture successive input data on alternating rising edges of the lower-domain input clock CLK156, through divided clock CLK156/2, Fig. 5A, col. 5, lines 15–25) and for outputting the data packet sequence (Sabih’s shift register 523 shifts out the successively received data, Figs. 5A–5B, col. 5, lines 29–50 and col. 6, lines 13–23);and
the output operating frequency is less than the serial operating frequency (Sabih receives input data in the 156.25 MHz clock domain and outputs corresponding data in the 322.265625 MHz clock domain, Figs. 5A–5B, col. 4, lines 50–61).
Lo and Sabih are analogous art because they are from the same field of endeavor, namely, circuitry for transferring data between communication-interface components operating in different clock or data-rate domains.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lo and Sabih before him or her, to modify the FIFO-based rate-conversion circuitry positioned between the slower MAC and faster PHY transmit path of Lo to include the dual-clock asynchronous FIFO register architecture of Sabih because Sabih teaches a known implementation for receiving successive input data in a slower input-clock domain and outputting the corresponding data in a faster output-clock domain.
The suggestion/motivation for doing so would have been to provide reliable clock-domain crossing while preserving the intended data throughput.
Therefore, it would have been obvious to combine Sabih with Lo to obtain the invention as specified in the instant claim.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lo (US Pub. No. 20200177522) in view of Mahalawat et al. (US Pat. No. 7356047), hereinafter referred to as Mahalawat.
As to claim 6, Lo discloses a deserializer (Lo: 10GBASE-R and SGMII deserializers provided in the MAC/PHY receive paths, Fig. 28B, para. 0140) for a physical layer interface (Lo: SERDES circuitry connecting MAC and PHY circuitry, Figs. 10 and 28B, paras. 0100 and 0140) of an electronic device (Lo: network-interface integrated circuits containing MAC, PHY, and SERDES circuitry, Figs. 10 and 28B, paras. 0100 and 0140), comprising: a deserializing module (Lo: receiving SERDES circuitry corresponding to the transmit-side serializers and converting the received serial signal for the parallel MAC-side interface, Figs. 11B and 28B, paras. 0102 and 0140), having a deserial operating frequency (Lo: SERDES operating at the higher physical-interface rate, Figs. 11B and 28B, paras. 0096–0102 and 0140), for receiving a dataflow transmitted in serial (Lo: serialized signal received through the higher-speed SERDES link, Fig. 11B, para. 0102) and converting the dataflow (Lo: deserializing the received signal for processing on the parallel interface, Fig. 11B, para. 0102) to a data packet sequence (Lo: received frame data supplied toward the MAC-side receive path, Figs. 11B and 28B, paras. 0096–0102 and 0140) transmitted in parallel (Lo: parallel XGMII data produced on the receiving side of the SERDES link, Fig. 11B, paras. 0098 and 0102), wherein the data packet sequence comprises repeated data packets (Lo: the transmit-side replicating circuit repeats lower-speed data according to the high-speed-to-low-speed ratio, and the receiving-side circuitry receives the resulting repeated high-speed data for down-sampling, Fig. 11B, paras. 0098 and 0101); and
each of the data down-conversion processing modules comprising: a frequency division unit (Lo: clock-divider circuit 1526 divides a recovered high-speed clock by integer T to produce a lower-frequency clock, Fig. 15, paras. 0110–0112), electrically connected to a media access control block (Lo’s divider establishes a lower clock for a slower data path and Lo’s MAC operates at the lower speed relative to the PHY, Figs. 15, 25, and 28B, paras. 0110–0112, 0137–0138, and 0140) and the deserializing module (Lo’s divider derives the lower-path clock from the recovered high-speed-path clock, while Lo’s deserializing module operates in that high-speed receive path, Figs. 15 and 28B, paras. 0110–0112 and 0140), for receiving a data processing frequency (Lo: clock-divider circuit 1526 receives a recovered clock associated with the high-speed data path, Fig. 15, paras. 0110–0112) and generating a data operating frequency based on the data processing frequency (Lo: divider 1526 divides the recovered high-speed clock by integer T to establish a lower-speed clock having a fixed ratio to the high-speed clock, Fig. 15, paras. 0110–0112), wherein the data operating frequency is provided to the media access control block (Lo teaches synchronizing the slow-path clock to the high-speed-path clock at a fixed ratio and operating the MAC more slowly than the PHY, Figs. 15, 25, and 28B, paras. 0111–0112, 0137–0138, and 0140), and the data operating frequency is less than the deserial operating frequency (Lo: divider 1526 divides the recovered clock by an integer greater than two and produces an exemplary 31.25 MHz slow-path clock from high-speed clocks of 5.625 GHz, 2.8125 GHz, or 1.40625 GHz, Fig. 15, paras. 0110–0112).
Mahalawat discloses, what Lo lacks, a plurality of data down-conversion processing modules (Mahalawat: respective MAC and PHY SGMII rate-adaptation units 20 and 26 include receive-rate-adaptation logic for reducing repeated higher-rate frame data to lower-rate frame data, Fig. 1, col. 3, lines 32–40; col. 5, lines 1–19);
an alignment unit (Mahalawat: MAC Rx PCS constitutes an alignment unit because it detects the SPD Start-of-Packet and EPD End-of-Packet framing delimiters and regenerates RX_DV based on the detected delimiters, Fig. 1, col. 5, lines 20–32), electrically connected to the deserializing module (Mahalawat: the MAC deserializer recovers data and clock from the received serial bitstream and sends the recovered data to MAC Rx PCS, thereby connecting the delimiter-detecting PCS to the deserializer, Fig. 1, col. 5, lines 25–30), for receiving the data processing frequency (Mahalawat: the MAC deserializer recovers the clock from the serial bitstream, and MAC Rx PCS processes the recovered receive data in the 312.5 MHz PCS clock domain, Fig. 1, col. 5, lines 25–34) and the data packet sequence from the deserializing module (Mahalawat: the MAC deserializer sends recovered data to MAC Rx PCS for delimiter detection and generation of decoded 8-bit data, Fig. 1, col. 5, lines 25–32), and for determining a starting position of each data packet in the data packet sequence (Mahalawat: detection of the SPD Start-of-Packet delimiter determines the starting position of each received frame, while detection of EPD determines its ending position; MAC Rx PCS detects these framing delimiters and regenerates RX_DV accordingly, Fig. 1, col. 5, lines 20–32); and
a packet discard unit (Mahalawat: MAC Rx Rate Adapter constitutes a packet-discard unit because its SAMPLE_EN-controlled sampling retains one instance from each repeated data segment and omits the remaining repeated instances, Figs. 1 and 3, col. 5, lines 32–41), electrically connected to the alignment unit (Mahalawat: MAC Rx PCS detects the framing delimiters, produces decoded data and RX_DV, and supplies the resulting aligned receive-path data to the downstream MAC Rx Rate Adapter, Fig. 1, col. 5, lines 25–34) and the deserializing module (Mahalawat: the MAC deserializer supplies recovered data to MAC Rx PCS, which supplies the decoded and frame-aligned data to MAC Rx Rate Adapter, thereby operatively connecting the rate adapter to the deserializer through the PCS, Fig. 1, col. 5, lines 25–34), for receiving the data processing frequency (Mahalawat: SAMPLE_EN controls the MAC Rx Rate Adapter’s sampling according to the higher-rate clock cycles, including sampling once every 2, 20, or 200 cycles for Type-1 segments and once every 3, 30, or 300 cycles for Type-2 segments, Fig. 3, col. 5, lines 32–41) and the data packet sequence from the alignment unit (Mahalawat: after MAC Rx PCS detects SPD and EPD, regenerates RX_DV, and generates decoded 8-bit data, MAC Rx Rate Adapter samples that aligned data based on the speed information, Fig. 1, col. 5, lines 25–34), discarding the repeated data packets in the data packet sequence (Mahalawat: sampling each repeated segment only once discards the redundant copies by excluding them from the rate-adapter output; SAMPLE_EN causes sampling once every 2, 20, or 200 repetitions for Type-1 segments and once every 3, 30, or 300 repetitions for Type-2 segments, Figs. 2–3, col. 4, lines 33–65; col. 5, lines 32–41), and
outputting a restored data packet sequence comprising non-repeated data packets (Mahalawat: sampling only one instance from each repeated segment restores the lower-rate frame-data sequence supplied to the receive MAC without the redundant repetitions, Figs. 1–3, col. 4, lines 45–65; col. 5, lines 25–41).
Lo and Mahalawat are analogous art because they are from the same field of endeavor, namely, serializer/deserializer circuitry for transferring Ethernet data between MAC and PHY components operating at different data rates.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lo and Mahalawat before him or her, to modify the receive-side deserializer and down-sampling rate-conversion circuitry of Lo to include the receive-side framing-alignment and sampling circuitry of Mahalawat because Mahalawat teaches a specific implementation for aligning the parallel data recovered from a serial dataflow and removing the redundant data introduced during rate adaptation.
The suggestion/motivation for doing so would have been to improve receiving-side down-sampling operation, with the expected benefits of preserving packet boundaries, eliminating redundant repetitions, and supplying the restored lower-rate data sequence to the MAC.
Therefore, it would have been obvious to combine Mahalawat with Lo to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 2 – 5 and 7 - 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Smith (US Pat. No. 9432298) disclosed a System, Method, And Computer Program product for improving memory systems.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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