DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because they are directed to a “computer-readable storage medium.”
Applicant discloses at paragraph [0106] that a computer-readable medium is also known as a machine readable storage medium. At paragraph [0107], Applicant further discloses “The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.”
Specifically, the Examiner draws the Applicant’s attention to the open-ended language in the quoted portions above. Under the broadest reasonable interpretation, these portions encompass transitory forms of signal transmission.
The United States Patent and Trademark Office (USPTO) is obliged to give claims their broadest reasonable interpretation consistent with the specification during proceedings before the USPTO. See In re Zietz, 893 F.2d 319 (Fed. Cir. 1989). The broadest reasonable interpretation of a claim drawn to a computer readable medium typically covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, particularly when the specification is silent. (See MPEP 2111.01.) When the broadest reasonable interpretation of a claim covers a signal per se, the claim must be rejected under 35 U.S.C. § 101 as covering non-statutory subject matter. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007).
The USPTO recognizes that applicants may have claims directed to computer readable media that cover signals per se, which the USPTO must reject under 35 U.S.C. § 101 as covering both non-statutory subject matter and statutory subject matter. In an effort to assist the patent community in overcoming a rejection or potential rejection under 35 U.S.C. § 101 in this situation, the USPTO suggests the following approach. A claim drawn to such a computer readable medium that covers both transitory and non-transitory embodiments may be amended to narrow the claim to cover only statutory embodiments to avoid a rejection under 35 U.S.C. § 101 by adding the limitation "non-transitory" to the claim. Such an amendment would typically not raise the issue of new matter, even when the specification is silent because the broadest reasonable interpretation relies on the ordinary and customary meaning that includes signals per se. The limited situations in which such an amendment could raise issues of new matter occur, for example, when the specification does not support a non-transitory embodiment because a signal per se is the only viable embodiment such that the amended claim is impermissibly broadened beyond the supporting disclosure. See e.g., Gentry Gallery, Inc. v. Berkline Corp., 134F.3d 1473 (Fed. Cir. 1998).
In view of the Applicant’s specification (as cited above) and the guidance provided (also above), a “computer-readable storage medium” under the broadest reasonable interpretation includes signals per se and therefore constitutes non-statutory subject matter. The Examiner recommends that the Applicant amend the rejected claims to recite “non-transitory computer-readable storage medium.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-7, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal (US 2022/0334747), Huang et al. (US 2023/0015066), and Li (US 2020/0042223).
Regarding claim 1, Agarwal discloses:
A memory sub-system comprising:
a memory device comprising multiple quad-level cell (QLC) block sets and multiple single-level cell (SLC) block sets ([0033] Next-generation flash storage devices include multiple dies, and each die may include multiple blocks. The flash storage devices may combine the multiple blocks to form a large block that may be referred to as a jumbo block; [0034] in ZNS, one block (or multiple blocks) is allocated to a particular zone; FIG. 7 multiple zones (i.e. block sets); [0076] FIG. 9 illustrates an example diagram 900 of a storage device having a first partition 902 containing die plane blocks 910, 912, 920, 922, 930, 932, 940, 942 and second partitions 950, 952 associated with different zones; [0040] the first partition involving the SLC block…the second partition includes a triple-level cell (TLC) block; [0045] NVM 110 can include, for example, flash integrated circuits, NAND memory (e.g., SLC memory, multi-level cell (MLC) memory, TLC memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, or any combination thereof))
Agarwal does not appear to explicitly teach “a processing device coupled to the memory device, the processing device to perform operations comprising: allocating an SLC block set from the multiple SLC block sets for storing data, the allocating of the SLC block set comprising selecting the SLC block set from the multiple SLC block sets based on a program/erase cycle count of the SLC block sets; detecting a migration trigger condition; based on detecting the migration trigger condition, allocating a QLC block set from the multiple QLC block sets to store the data; migrating the data from the SLC block set to the QLC block set, and based on migrating the data from the SLC block set to the QLC block set, releasing the SLC block set.” However, Huang et al. disclose:
a processing device coupled to the memory device (FIG. 1 Processor 117), the processing device to perform operations comprising:
allocating ([0048] At operation 331, a memory sub-system can determine that a new free block should be selected in order to store received host data) an SLC block set from the multiple SLC block sets for storing data (FIG. 3 step 333-1 New Block in SLC Mode), the allocating of the SLC block set comprising selecting the SLC block set from the multiple SLC block sets based on a program/erase cycle count of the SLC block sets (FIG. 3 step 335-1 Determine Block with Lowest SLC PEC);
…allocating (FIG. 3 step 331 New Free Block) a QLC block set from the multiple QLC block sets to store the data (FIG. 3 step 333-3 New Block in QLC Mode);
…releasing the SLC block set ([0048] The new free block can be a block that does not store data that needs to be saved. For example,…the data of the free block is no longer needed by the memory sub-system and can be reallocated for writing additional data to (implies that the block is released back to the free pool of blocks)).
Agarwal and Huang et al. are analogous art because Agarwal teaches zones namespaces and Huang et al. teach monitoring mixed block modes.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Agarwal and Huang et al. before him/her, to modify Agarwal’s teachings of a partitioned memory device with the Huang et al. teachings of monitoring mixed mode blocks because doing so enables the memory device to determine particular program erase count (PEC) for each memory cell type (SLC, QLC). This allows for two different approaches for determining a next block to write host data to: a next block with a lowest PEC count or a next block with a lowest PEC ratio ( Huang et al. [0018]). The combination would prevent cell endurance degradation and increase reliability in the mixed mode memory system.
Agarwal and Huang et al. do not appear to explicitly teach “detecting a migration trigger condition; based on detecting the migration trigger condition…migrating the data from the SLC block set to the QLC block set, and based on migrating the data from the SLC block set to the QLC block set” However, Li discloses:
detecting a migration trigger condition (FIG. 5C step 552 Evaluate free block pool in SLC region to determine available blocks; step 554 Fallen to threshold? YES);
based on detecting the migration trigger condition (FIG. 5C step 552), allocating (FIG. 3 step 331 New Free Block) a QLC block set from the multiple QLC block sets to store the data ([0049] a large block of data from SLC drive 322 is sequentially written to QLC drive 324 (i.e., at the next available data block in QLC drive 324));
migrating the data from the SLC block set to the QLC block set (FIG. 5C step 566 Sequentially write valid pages into QLC block to fill full block, update FTL mapping, and erase SLC pages), and
based on migrating the data from the SLC block set to the QLC block set, releasing the SLC block set (FIG. 5C step 566 erase SLC pages; the method of FIG. 5C is performed to increase the number of free SLC blocks, which implies that the blocks are released to the free block pool).
Agarwal, Huang et al., and Li are analogous art because Agarwal teaches zones namespaces; Huang et al. teach monitoring mixed block modes; and Li teaches a high-density storage device that provides high endurance and improved performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Agarwal, Huang et al., and Li before him/her, to modify the combined teachings of Agarwal and Huang et al. with Li’s teachings of migrating data from SLC memory blocks to QLC memory blocks because doing so increase the number of program-erase cycles in the memory device. The combination would provide high endurance and improved performance.
Regarding claim 2, Huang et al. further disclose:
The memory sub-system of claim 1, wherein selecting of the SLC block set comprises identifying the SLC block set as having a lowest program/erase cycle count among the multiple SLC block sets (FIG. 3 step 335-1 Determine Block with Lowest SLC PEC).
Regarding claim 3, Li further discloses:
The memory sub-system of claim 2, wherein releasing of the SLC block set comprises updating zone mapping information of the SLC block set to indicate that the SLC block set is unmapped (FIG. 5C step 566 update FTL mapping; [0055] if the host data updates an existing page, controller 140 marks the previous location as invalid (denoted with an “X”) and updates the mapping with the new location).
Regarding claim 6, Huang et al. further disclose:
The memory sub-system of claim 1, wherein the operations comprise selecting the SLC block set for migration to the QLC block set based on one of:
a program/erase cycle count of the SLC block set (FIG. 3 step 335-1 Determine Block with Lowest SLC PEC), a block version of the SLC block set, or a finished time of the SLC block set, the finished time indicating when the SLC block set is fully written.
Regarding claim 7, Agarwal and Huang et al. further disclose:
The memory sub-system of claim 1, wherein the allocating of the QLC block set (Huang et al.: FIG. 3 step 333-3 New Block in QLC Mode) comprises selecting the QLC block set from the multiple block sets (Agarwal: FIG. 9 zones).
Regarding claim 15, Huang et al. disclose:
A method comprising:
allocating ([0048] At operation 331, a memory sub-system can determine that a new free block should be selected in order to store received host data), by a processing device (FIG. 1 Processor 117), an SLC block set in a memory device (FIG. 1 Memory Device 130) for storing data, the allocating of the SLC block set comprising selecting the SLC block set from multiple SLC block sets of the memory device (FIG. 3 step 333-1 New Block in SLC Mode) based on the SLC block set having a lowest program/erase cycle count among the multiple SLC block sets (FIG. 3 step 335-1 Determine Block with Lowest SLC PEC);
…allocating (FIG. 3 step 331 New Free Block), by the processing device, from multiple QLC block sets in the memory device, a QLC block set to store the data (FIG. 3 step 333-3 New Block in QLC Mode);
…releasing, by the processing device, the SLC block set ([0048] The new free block can be a block that does not store data that needs to be saved. For example,…the data of the free block is no longer needed by the memory sub-system and can be reallocated for writing additional data to (implies that the block is released back to the free pool of blocks)).
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Huang et al. do not appear to explicitly teach “detecting, by the processing device, a migration trigger condition; based on detecting the migration trigger condition…migrating, by the processing device, the data from the SLC block set to the QLC block set, and based on migrating the data from the SLC block set to the QLC block set.” However, Li discloses:
detecting, by the processing device, a migration trigger condition (FIG. 5C step 552 Evaluate free block pool in SLC region to determine available blocks; step 554 Fallen to threshold? YES);
based on detecting the migration trigger condition (FIG. 5C step 552), allocating (FIG. 3 step 331 New Free Block), by the processing device, from multiple QLC block sets in the memory device, a QLC block set to store the data ([0049] a large block of data from SLC drive 322 is sequentially written to QLC drive 324 (i.e., at the next available data block in QLC drive 324));
migrating, by the processing device, the data from the SLC block set to the QLC block set (FIG. 5C step 566 Sequentially write valid pages into QLC block to fill full block, update FTL mapping, and erase SLC pages), and
based on migrating the data from the SLC block set to the QLC block set, releasing, by the processing device, the SLC block set (FIG. 5C step 566 erase SLC pages; the method of FIG. 5C is performed to increase the number of free SLC blocks, which implies that the blocks are released to the free block pool).
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Regarding claim 16, Huang et al. further disclose:
The method of claim 15, comprising selecting the SLC block set for migration to the QLC block set based on one of:
a program/erase cycle count of the SLC block set (FIG. 3 step 335-1 Determine Block with Lowest SLC PEC), a block version of the SLC block set, or a finished time of the SLC block set, the finished time indicating when the SLC block set is fully written.
Regarding claim 17, Huang et al. further disclose:
The method of claim 15, wherein the allocating of the QLC block set comprises selecting the QLC block set from the multiple block sets based on at least one of:
a lowest program/erase cycle count associated with each die in the memory device;
a program/erase cycle count of the QLC block set (FIG. 3 step 335-3 Determine Block with Lowest QLC PEC);
a number of unmapped SLC block sets in each die of the memory device; and
a round robin selection scheme.
Regarding claim 18, Huang et al. disclose:
A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising:
allocating ([0048] At operation 331, a memory sub-system can determine that a new free block should be selected in order to store received host data) an SLC block set in a memory device (FIG. 1 Memory Device 130) for storing data, the allocating of the SLC block set comprising selecting the SLC block set from multiple SLC block sets of the memory device (FIG. 3 step 333-1 New Block in SLC Mode) based on the SLC block set having a lowest program/erase cycle count among the multiple SLC block sets (FIG. 3 step 335-1 Determine Block with Lowest SLC PEC);
…allocating (FIG. 3 step 331 New Free Block) from multiple QLC block sets in the memory device, a QLC block set to store the data (FIG. 3 step 333-3 New Block in QLC Mode);
…releasing the SLC block set ([0048] The new free block can be a block that does not store data that needs to be saved. For example,…the data of the free block is no longer needed by the memory sub-system and can be reallocated for writing additional data to (implies that the block is released back to the free pool of blocks)).
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Huang et al. do not appear to explicitly teach “detecting a migration trigger condition; based on detecting the migration trigger condition…migrating the data from the SLC block set to the QLC block set, and based on migrating the data from the SLC block set to the QLC block set.” However, Li discloses:
detecting a migration trigger condition (FIG. 5C step 552 Evaluate free block pool in SLC region to determine available blocks; step 554 Fallen to threshold? YES);
based on detecting the migration trigger condition (FIG. 5C step 552), allocating (FIG. 3 step 331 New Free Block) from multiple QLC block sets in the memory device, a QLC block set to store the data ([0049] a large block of data from SLC drive 322 is sequentially written to QLC drive 324 (i.e., at the next available data block in QLC drive 324));
migrating the data from the SLC block set to the QLC block set (FIG. 5C step 566 Sequentially write valid pages into QLC block to fill full block, update FTL mapping, and erase SLC pages), and
based on migrating the data from the SLC block set to the QLC block set, releasing the SLC block set (FIG. 5C step 566 erase SLC pages; the method of FIG. 5C is performed to increase the number of free SLC blocks, which implies that the blocks are released to the free block pool).
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Regarding claim 19, Huang et al. further disclose:
The computer-readable storage medium of claim 18, wherein the operations comprise selecting the SLC block set for migration to the QLC block set based on one of:
a program/erase cycle count of the SLC block set (FIG. 3 step 335-1 Determine Block with Lowest SLC PEC), a block version of the SLC block set, or a finished time of the SLC block set, the finished time indicating when the SLC block set is fully written.
Regarding claim 20, Huang et al. further disclose:
The computer-readable storage medium of claim 18, wherein the allocating of the QLC block set comprises selecting the QLC block set from the multiple block sets based on at least one of:
a lowest program/erase cycle count associated with each die in the memory device;
a program/erase cycle count of the QLC block set (FIG. 3 step 335-3 Determine Block with Lowest QLC PEC);
a number of unmapped SLC block sets in each die of the memory device; and
a round robin selection scheme.
Claims 11-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal, Huang et al., and Li as applied to claim 11 above, and further in view of Jang (US 2022/0188008).
Regarding claim 11, Huang et al. and Li et al. further disclose:
The memory sub-system of claim 1, wherein the QLC block set is a first QLC block (FIG. 3 step 333-3 New Block in QLC Mode);
Agarwal, Huang et al. and Li et al. do not appear to explicitly teach “the operations comprise: detecting a QLC static wear leveling condition; and based on detecting the QLC wear leveling condition, performing QLC static wear leveling on the multiple QLC blocks, the performing QLC static wear leveling comprising moving the data from the first QLC block set to a second QLC block set.” However, Jang discloses:
the operations comprise:
detecting a QLC static wear leveling condition ([0078] SWL may be triggered when a deviation for the erase counts of the memory blocks becomes equal to or more than for example, a preset value); and
based on detecting the QLC wear leveling condition, performing QLC static wear leveling on the multiple QLC blocks, the performing QLC static wear leveling comprising moving the data from the first QLC block set to a second QLC block set ([0081] Now, the controller 110 may migrate data of the victim block selected in operation S109 to a target block, and perform wear leveling in operation S111).
Agarwal, Huang et al., Li, and Jang are analogous art because Agarwal teaches zones namespaces; Huang et al. teach monitoring mixed block modes; Li teaches a high-density storage device that provides high endurance and improved performance; and Jang teaches static wear leveling.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Agarwal, Huang et al., Li, and Jang before him/her, to modify the combined teachings of Agarwal, Huang et al., and Li with Jang’s teachings of performing static wear leveling based on a QLC wear leveling condition because doing so would lengthen the lifetime of the memory device.
Regarding claim 12, Jang further discloses:
The memory sub-system of claim 11, wherein the operations comprise selecting the second QLC block based on determining the first QLC block set and the second QLC block set satisfy the QLC static wear leveling condition ([0070] The SWL component 260 may migrate data of the victim block, selected by the victim block selector 250, to a target block. The target block may be selected through various methods; It would be obvious to one skilled in the art before the effective filing date that the various methods of selecting the target block include satisfying the QLC static wear leveling condition).
Regarding claim 14, Agarwal further discloses:
The memory sub-system of claim 11, wherein the first QLC block set and the second QLC block set are located on a same die of the memory device (FIG. 9 z0 and z1 on D1).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Agarwal, Huang et al., Li, and Jang as applied to claim 11 above, and further in view of Segal et al. (US 2011/0271043).
Regarding claim 13, Agarwal further discloses:
The memory sub-system of claim 11, wherein:
the first QLC block set is from a first die of the memory device (FIG. 9 DO);
the second QLC block set is from a second die of the memory device (FIG. 9 D1); and
Agarwal, Huang et al., Li, and Jang do not appear to explicitly teach “the operations comprise selecting the second QLC block set from the second die based on determining the second QLC block set has a lowest program/erase cycle count of QLC block sets in the second die.” However, Segal et al. disclose:
the operations comprise selecting the second QLC block set from the second die based on determining the second QLC block set has a lowest program/erase cycle count of QLC block sets in the second die ([0033] static wear leveling operations may be performed, for example, in order to extend the useful life of the Flash memory device. Each flash memory block is typically rated for a certain number of P/E cycles. For example, MLC blocks may be rated for 3,000 P/E cycles…static wear leveling may prevent or delay some blocks of memory from exceeding a predetermined P/E cycle threshold while other blocks have endured fewer P/E cycles by distributing Flash cell erasures and re-writes evenly across the Flash memory array).
Agarwal, Huang et al., Li, Jang, and Segal et al. are analogous art because Agarwal teaches zones namespaces; Huang et al. teach monitoring mixed block modes; Li teaches a high-density storage device that provides high endurance and improved performance; Jang teaches static wear leveling; and Segal et al. teach static wear leveling.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Agarwal, Huang et al., Li, Jang, and Segal et al. before him/her, to modify the combined teachings of Agarwal, Huang et al., Li, and Jang with the Segal et al. teachings performing static wear leveling based on a QLC wear leveling condition because doing so would lengthen the lifetime of the memory device.
Allowable Subject Matter
Claims 4, 5, and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the examiner’s statement of reasons for allowance:
While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Agarwal, Huang et al. Li, Jang, and Segal when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Regarding claim 4, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The memory sub-system of claim 1, wherein:
the SLC block set is a first SLC block set;
a first portion of the multiple SLC block sets form a mapped pool of SLC block sets, the mapped pool of SLC block sets comprises the first SLC block set;
a second portion of the multiple SLC block sets form an unmapped pool of SLC block sets; and
the operations comprise:
detecting an SLC static wear leveling condition; and
based on detecting the SLC static wear leveling condition, performing static wear leveling on the multiple SLC blocks, the performing of the static wear leveling comprising:
identifying a second SLC block set from the unmapped pool of SLC block sets;
moving the data from the first SLC block set to the second SLC block set; and
moving the first SLC block set from the mapped pool of SCL block sets to the unmapped pool of SLC block sets.”
Claim 5 would be allowable based on its dependency from claim 4.
Regarding claim 8, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The memory sub-system of claim 7, wherein the selecting of the QLC block set comprises:
identifying a set of dies within the memory device having at least one unmapped QLC block;
determining a lowest program/erase cycle count associated with each die in the set of dies;
selecting a die from the set of dies based on the lowest program/erase cycle count associated with each die; and
selecting the QLC block set from a plane of the die based on the QLC block set having a lowest program/erase cycle count of QLC block sets in the plane.”
Regarding claim 9, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The memory sub-system of claim 7, wherein the selecting of the QLC block set comprises:
determining a number of unmapped SLC block sets in each die of multiple dies of the memory device;
identifying a die, from among the multiple dies, of the memory device having a lowest number of unmapped SLC block sets; and
selecting the QLC block set from a plane of the die based on the QLC block set having a lowest program/erase cycle count of QLC block sets in the plane.”
Regarding claim 10, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The memory sub-system of claim 7, wherein selecting a die from among multiple dies of the memory device based on a round robin selection scheme; and
selecting the QLC block set from a plane of the die based on the QLC block set having a lowest program/erase cycle count of QLC block set in the plane.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because they disclose wear leveling:
Pletka et al. (US 2024/0427515)
Cariello (US 2021/0042236)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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/TRACY A WARREN/ Primary Examiner, Art Unit 2137
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