DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement dated July 29th, 2025, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-5, 6, 9-10, 13-14, 16, and 18-19 of U.S. Patent No. 12,346,613. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of U.S. Patent 12,346,613 contains every element of claims 1 and 4 of the instant application and as such anticipates claims 1 and 4 of the instant application.
Claims 4 and 5 of U.S. Patent 12,346,613 contains every element of claim 6 of the instant application and as such anticipates claim 6 of the instant application.
Claim 6 of U.S. Patent 12,346,613 contains every element of claim 7 of the instant application and as such anticipates claim 7 of the instant application.
Claim 8 of U.S. Patent 12,346,613 contains every element of claims 8 and 11 of the instant application and as such anticipates claim 8 and 11 of the instant application.
Claim 9 and 10 of U.S. Patent 12,346,613 contains every element of claims 2-3, 9-10, and 16-17 of the instant application and as such anticipates claims 2-3, 9-10, and 16-17 of the instant application.
Claims 13 and 14 of U.S. Patent 12,346,613 contains every element of claims 13 and 14 of the instant application and as such anticipates claims 13 and 14 of the instant application.
Claim 16 of U.S. Patent 12,346,613 contains every element of claims 15 and 18 of the instant application and as such anticipates claims 15 and 18 of the instant application.
Claims 18 and 19 of U.S. Patent 12,346,613 contains every element of claim 20 of the instant application and as such anticipates claim 20 of the instant application.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-5, 6, 9-10, 13-14, 16, and 18-19 of U.S. Patent No. 11,960,777. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of U.S. Patent 11,960,777 contains every element of claims 1 and 4 of the instant application and as such anticipates claims 1 and 4 of the instant application.
Claims 4 and 5 of U.S. Patent 11,960,777 contains every element of claim 6 of the instant application and as such anticipates claim 6 of the instant application.
Claim 6 of U.S. Patent 11,960,777 contains every element of claim 7 of the instant application and as such anticipates claim 7 of the instant application.
Claim 8 of U.S. Patent 11,960,777 contains every element of claims 8 and 11 of the instant application and as such anticipates claim 8 and 11 of the instant application.
Claim 9 and 10 of U.S. Patent 11,960,777 contains every element of claims 2-3, 9-10, and 16-17 of the instant application and as such anticipates claims 2-3, 9-10, and 16-17 of the instant application.
Claims 13 and 14 of U.S. Patent 11,960,777 contains every element of claims 13 and 14 of the instant application and as such anticipates claims 13 and 14 of the instant application.
Claim 16 of U.S. Patent 11,960,777 contains every element of claims 15 and 18 of the instant application and as such anticipates claims 15 and 18 of the instant application.
Claims 18 and 19 of U.S. Patent 11,960,777 contains every element of claim 20 of the instant application and as such anticipates claim 20 of the instant application.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-9, 12-13, and 15-16 of U.S. Patent No. 11,593,036. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of U.S. Patent 11,593,036 contains every element of claims 1 and 4 of the instant application and as such anticipates claims 1 and 4 of the instant application.
Claims 4 and 5 of U.S. Patent 11,593,036 contains every element of claim 6 of the instant application and as such anticipates claim 6 of the instant application.
Claim 6 of U.S. Patent 11,593,036 contains every element of claim 7 of the instant application and as such anticipates claim 7 of the instant application.
Claim 7 of U.S. Patent 11,593,036 contains every element of claims 8 and 11 of the instant application and as such anticipates claim 8 and 11 of the instant application.
Claim 8 and 9 of U.S. Patent 11,593,036 contains every element of claims 2-3, 9-10, and 16-17 of the instant application and as such anticipates claims 2-3, 9-10, and 16-17 of the instant application.
Claims 12 of U.S. Patent 11,593,036 contains every element of claim 13 of the instant application and as such anticipates claim 13 of the instant application.
Claim 13 of U.S. Patent 11,593,036 contains every element of claims 15 and 18 of the instant application and as such anticipates claims 15 and 18 of the instant application.
Claims 15 and 16 of U.S. Patent 11,593,036 contains every element of claim 20 of the instant application and as such anticipates claim 20 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-10, 12-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Verma et al. [US2016/0080490] in view of Colgrove et al. [US2013/0042052]. Verma teaches online data movement without compromising data integrity. Colgrove teaches logical sector mapping in a flash storage array.
Regarding claims 1, 8, and 15, Verma teaches a method comprising:
generating, by a storage controller of a storage system [Verma paragraph 0062, first lines “…A computer system is provided including at least one processor…”], a plurality of parity shards for a data segment based on a number of parity units selected based on a parity configuration supported by the storage system [Verma paragraph 0035, most lines “…Embodiments may further include increasing the number of copies in a mirror and converting a parity (RAID5/6) to parity with mirroring (RAID5/6+1) dynamically and sparsely (only on the sections that need to be moved), removing a disk from a RAID array by mirroring its contents across the remaining disks to avoid compromising integrity, moving data across fault domains to increase the resiliency of a RAID array to more than its initial creation (e.g. migrating an array that can lose an enclosure to one that can lose a rack), and converting a mirror space to a parity space in place (or vice-versa) without rewriting the data…” and paragraph 0057, last lines “…As mentioned above, the resiliency schemes may include mirroring, parity or combinations thereof (including the various RAID implementations) or other resiliency schemes…”],
Verma fails to explicitly teach wherein the plurality of parity shards and the data segment are to be stored in fast durable storage of a storage element that integrates fast durable storage and bulk durable storage;
Colgrove teaches wherein the plurality of parity shards and the data segment are to be stored in fast durable storage of a storage element that integrates fast durable storage and bulk durable storage [Colgrove paragraph 0057, last lines “…A write request may be placed in an NVRAM buffer, such as RAM 172, and a write completion acknowledgment may be sent to a corresponding client computer of the client computers 110a-110c. At a later time, an asynchronous process may flush the buffered write requests to the storage devices 176a-176m…”(Where the RAM reads on fast storage and storage devices reads on bulk storage.)];
Verma and Colgrove are analogous arts in that the both deal with improving data storage performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Verma’s storage system with various parity schemes with Colgrove’s use of NVRAM to hold data before it’s eventually moved to SSD storage which is bulk storage for the benefit of better utilizing available bandwidth and capacity by migrating on to new hardware without compromising the resiliency of the data [Verma paragraph 0033, last lines “…requiring storage that can adapt to these changes by allowing data to migrate away from drives that have reached their end of life, migrate onto new hardware, and shift around to better utilize the available bandwidth and capacity based on the workload. This is done in real time without compromising the integrity or resiliency of data…”].
based on a determination that a condition for moving the data segment is satisfied [Verma paragraph 0046, first lines “…determining that data is to be moved from the first data store to the second data store…” and “…The determining module 106 may identify which data (among data 113) can be moved, which data must move and where the data is to be moved to…”], moving at least a portion of the data segment and the plurality of parity shards from the fast durable storage to the bulk durable storage [Colgrove paragraph 0057, last lines “…A write request may be placed in an NVRAM buffer, such as RAM 172, and a write completion acknowledgment may be sent to a corresponding client computer of the client computers 110a-110c. At a later time, an asynchronous process may flush the buffered write requests to the storage devices 176a-176m…”(Where the RAM reads on fast storage and storage devices reads on bulk storage.)], wherein the bulk durable storage uses another parity configuration [Verma paragraph 0057, most lines “…determining that a resiliency scheme for at least a specified portion of a data store is to be changed from a first resiliency scheme to a second, different resiliency scheme, the data store including one or more portions of data (310). For example, the determining module 106 of computer system 101 may determine that resiliency scheme 114A for at least some data 113 on the first data store 112 is to be changed to a second resiliency scheme 114B. As mentioned above, the resiliency schemes may include mirroring, parity or combinations thereof (including the various RAID implementations) or other resiliency schemes…”].
Regarding claims 2, 9, and 16, as per claim 1, Colgrove teaches the fast durable storage comprises nonvolatile random access memory [Colgrove paragraph 0057, last lines “…A write request may be placed in an NVRAM buffer, such as RAM 172…”].
Regarding claims 3, 10, and 17, as per claim 1, Colgrove teaches the bulk durable storage comprises one or more solid state drives [Colgrove paragraph 0057, last lines “…At a later time, an asynchronous process may flush the buffered write requests to the storage devices 176a-176m…” and paragraph 0040, middle lines “…The storage devices 176a-176 may be SSDs utilizing Flash memory…”].
Regarding claims 5, 12, and 19 as per claim 1, Verma teaches selecting the number of parity units comprises selecting from among two or more levels of redundancy associated with different system performance or durability criteria [Verma paragraph 0035, most lines “…Embodiments may further include increasing the number of copies in a mirror and converting a parity (RAID5/6) to parity with mirroring (RAID5/6+1) dynamically and sparsely (only on the sections that need to be moved), removing a disk from a RAID array by mirroring its contents across the remaining disks to avoid compromising integrity, moving data across fault domains to increase the resiliency of a RAID array to more than its initial creation (e.g. migrating an array that can lose an enclosure to one that can lose a rack), and converting a mirror space to a parity space in place (or vice-versa) without rewriting the data…” and paragraph 0057, last lines “…As mentioned above, the resiliency schemes may include mirroring, parity or combinations thereof (including the various RAID implementations) or other resiliency schemes…”].
Regarding claims 6, 13, and 20, as per claim 1, Colgrove teaches further comprising modifying the data segment in the fast durable storage prior to moving the data segment to the bulk durable storage [Colgrove paragraph 0058, first half “…A deduplication table may utilize a key comprising a hash value determined from a data component associated with a storage access request. The initial steps of a deduplication operation may be performed concurrently with other operations, such as a read/write request, a garbage collection operation, a trim operation, and so forth. For a given write request, the data sent from one of the client computer systems 110a-110c may be a data stream, such as a byte stream…”].
Regarding claims 7 and 14, as per claim 1, Colgrove teaches modifying the data segment comprises performing a data optimization operation selected from data deduplication, data compression, or garbage collection [Colgrove paragraph 0058, first half “…A deduplication table may utilize a key comprising a hash value determined from a data component associated with a storage access request. The initial steps of a deduplication operation may be performed concurrently with other operations, such as a read/write request, a garbage collection operation, a trim operation, and so forth. For a given write request, the data sent from one of the client computer systems 110a-110c may be a data stream, such as a byte stream…”].
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Verma et al. [US2016/0080490] in view of Colgrove et al. [US2013/0042052] in view of Sprouse et al. [US2016/0117253]. Verma teaches online data movement without compromising data integrity. Colgrove teaches logical sector mapping in a flash storage array. Sprouse teaches method for improving mixed random performance in low queue depth workloads.
Regarding claims 4, 11, and 18 as per claim 1,Both Verma and Colgrove fail to explicitly teach the condition for moving the data segment comprises detecting that a complete RAID stripe has been formed in the fast durable storage.
However, Sprouse does teach the condition for moving the data segment comprises detecting that a complete RAID stripe has been formed in the fast durable storage [Sprouse paragraph 0059, last half “…during the read mode, all writes (e.g., both host writes and garbage collection writes) are buffered in a capacitor backed RAM (e.g., DRAM or SRAM, sometimes called a write cache) until a predetermined criteria is met (e.g., until the buffer is full, until enough data has accrued to complete a RAID stripe, etc.). During this time, read commands are serviced quickly since there are no blocking write operations. In some embodiments, when the predetermined criteria is met (e.g., when the buffer is full, when enough data has accrued to complete a RAID stripe, etc.), the storage device switches to the write mode, during which the storage device issues as many writes in parallel as possible…”].
Verma, Colgrove, and Sprouse are analogous arts in that the all deal with improving data storage performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Verma and Colgrove with Sprouse’s use of detecting when the cache has a complete RAID stripe for the benefit of improving random performance in low queue depth workloads by optimizing the flush of cache data [Sprouse paragraph 0011, most lines “…improving mixed random performance in low queue depth workloads. Some embodiments include systems, methods and/or devices to schedule a regular flush of a write cache in accordance with a determination that a workload is a non-qualifying workload and to schedule an optimized flush of the write cache…”].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ives et al. [US9,383,940] Ives teaches a first RAID group with a first level of protection and a second RAID group with a second level of protection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139
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