DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claims 1 and 11 introduce “a first command” and claims 1-20 recite “the first command” while also referring to “a first I/O command” and “the first I/O command”. Recitations of “the first command” could easily be confused with “the first I/O command” and therefore the Examiner requests changing the designation of “a first command” and “the first command” to recite something more distinguishing such as “a secure erase command” and “the secure erase command” or “a first erase command” and “the first erase command” or something similar to avoid the confusion.
Claim 1 recites, “in response to receiving, from the host, a first input/output (I/O) command that designates the first namespace in a first period that is after the first operation is started but before the first operation is completed”, which as best understood by the Examiner in light of the specification should be amended to recite, “in response to receiving, from the host and in a first period that is after the first operation is started but before the first operation is completed, a first input/output (I/O) command that designates the first namespace
Claim 1 recites, “in response to receiving, from the host, a second I/O command that designates the second namespace in the first period, execute the second I/O command”, which as best understood by the Examiner in light of the specification should be amended to recite, “in response to receiving, from the host and in the first period, a second I/O command that designates the second namespace
Claims 7 and 8 recite, “wherein the controller is configured to”, which as best understood by the Examiner in light of the specification should be amended to recite, “wherein the controller is further configured to”.
Claim 11 recites, “receiving, from the host, a first input/output (I/O) command that designates the first namespace in a first period that is after the first operation is started but before the first operation is completed”, which as best understood by the Examiner in light of the specification should be amended to recite, “receiving, from the host and in a first period that is after the first operation is started but before the first operation is completed, a first input/output (I/O) command that designates the first namespace
Claim 11 also recites, “receiving, from the host, a second I/O command that designates the second namespace in the first period”, which as best understood by the Examiner in light of the specification should be amended to recite, “receiving, from the host and in the first period, a second I/O command that designates the second namespace
Claims 2-10 and 12-20 are objected to for failing to correct the deficiencies of a base claim from which they depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6-7, 9, 10, 11, 14, 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0121344 A1 (Seo) in view of the NVM Express Base Specification, Revision 1.4, published June 10, 2019 (NVMe) in further view of US Patent Application Publication No. Pub. No. US 2019/0087113 A1 (Isozaki) in further view of US Patent Application Publication No. US 2020/0218465 A1 (Klein).
Regarding claim 1 and analogous claim 11:
Seo discloses, a memory system, comprising: a non-volatile memory including a plurality of blocks (by disclosing that the storage device (100), which may be an NVMe SSD device, is divided into a plurality of logical blocks which are managed in namespaces, the logical blocks correspond to actual physical locations of blocks within the memory device (120) [0042-0043] [0045] [Fig. 1] [Fig. 23] [Fig. 25]), each of the plurality of blocks being a unit of a data erase operation (the FTL of the controller (110) performs erasure on the non-volatile memory (120) in units of blocks [0138] [0144] [Fig. 23] [Fig. 25]) and a controller electrically connected to the non-volatile memory and configured to: manage a plurality of namespaces (a controller (110) is connected to the non-volatile memory and includes a namespace manager (111a) that manages a plurality of namespaces, such as a 1st to 3rd [Figs. 3A-3B]), the plurality of namespaces including at least a first namespace and a second namespace (there may be 3 [Figs. 3A-3B] or even 5 or more namespaces [see Fig. 6])
Seo does not explicitly disclose, but NVMe teaches receiving, from a host, a first command requesting a secure erase of secure erase target data that is data stored in the first namespace (by teaching that a NVMe Format command may specify a secure erase setting specifying a user data erase that may erase all user data associated with a namespace identifier specified in the command. The erasure may result in all data in the namespace being zero filled or one filled (i.e., erased) [§5.23 Format NVM command – NVM Command Set Specific, pgs. 234-236] [Fig. 327] [Fig. 328])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the NVMe SSD with namespaces that cover an LBA range as taught by Seo to include the NVM Format command which includes secure erase functionality of a specified namespace, which securely erases all user data of the specified namespace as taught by NVMe as taught by NVMe.
One of ordinary skill in the art would have been motivated to make this modification because it would securely erase data to make sure that the user data and metadata are destroyed and cannot be accessed as taught by NVMe in [§5.23 Format NVM command – NVM Command Set Specific, pgs. 234-236] [Fig. 327] [Fig. 328]. Furthermore, it would provide compliance with the NVMe standard, which is designed to address the needs of Enterprise and Client systems that utilize PCI Express based solid-state drives as taught by NVMe in [§1.4 Theory of Operation, pg. 7, ¶1].
Seo does not explicitly disclose, but Isozaki teaches, in response to receiving, from the host, a first input/output (I/O) command that designates the first namespace in a first period that is after the first operation is started but before the first operation is completed, abort the first I/O command or suspend execution of the first I/O command until the first operation is completed; and in response to receiving, from the host, a second I/O command that designates the second namespace in the first period, execute the second I/O command (by teaching that an access to a range whose data is erased in progress is rejected (or queued, or an error sent back to the host), whereas access to a range other than the range whose data is erased in progress is permitted [0088-0094]. The erased range may be a namespace as a namespace erase may be requested with a command identifying the namespace for erasure in namespace units [0105-0107]. The access requests come from a user of a host [Figs. 1A-1B] [0032]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device as taught by Seo in view of NVMe to reject an access request to a namespace address range that is in progress of an erase operation, but to otherwise permit an access to a namespace address range that is not in progress of an erase operation as taught by Isozaki.
One of ordinary skill in the art would have been motivated to make this modification because a user doesn’t knowledge about how far the erase has progressed, and as if the access request were allowed, it would be indeterminate to the user whether that access request was to an already erased area or not yet erased area. Accordingly, it is better to prevent the access request so that there is not confusion. However, a similar restriction does not apply to requests to access ranges that are not undergoing erase because such confusion does not apply and normal operation should be performed as taught by Isozaki in [0089] [0094].
Seo in view of NVMe in further view of Isozaki does not explicitly disclose, but Klein teaches, start to execute a first operation that includes: identifying one or more first blocks of the plurality of blocks, each of the one or more first blocks storing at least part of the secure erase target data; and executing the data erase operation on each of the one or more first blocks (by teaching that a selective erase operation may erase a particular logical address or particular logical address range (i.e., the logical address range of a namespace such as taught by the combination of Seo in view of NVMe) [0014]. The selective erase operation also erases ephemeral data in invalid pages, such as in the invalid pages of the logical addresses of a namespace [0014]. In this way, both valid and invalid data corresponding to the selective erase operation is erased [Abstract] [0026] [0031] [0042-0044]. The host may send the erase command specifying the logical block addresses [0016]. In response, the controller looks up the addresses in metadata tables and identifies the affected pages and the blocks in which the pages of data are stored [0042]. Valid data that are not the target of erasure are copied from the blocks and then the blocks are erased [0044]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the secure erase of a range of LBAs making up a namespace as taught by Seo in view of NVMe to include identifying the blocks that include all pages previously written by the LBAs (including valid and invalid data), and then erasing those blocks after moving out valid data not mapped to an LBA targeted by the erasure as taught by Klein.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that ephemeral data (data that is currently valid, but was previously valid) that may otherwise stay around for an indeterminate amount of time is deleted as taught by Klein in [0013-0014].
Regarding claim 4 and analogous claim 14:
The memory system according to claim 1 is made obvious by Seo in view of NVMe in further view of Isozaki in further view of Klein (Seo-NVMe-Isozaki-Klein).
Seo does not explicitly disclose, but Klein teaches, wherein the first operation further includes: a copy operation for copying valid data other than any of the secure erase target data from the one or more first blocks to one or more copy destination blocks of the plurality of blocks (by teaching that valid data page from the blocks that are to be erased that are not mapped to the logical addresses targeted by the selective erasure operation are copied to other blocks before the blocks are erased [0044]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the secure erase of a range of LBAs making up a namespace as taught by Seo in view of NVMe to include identifying the blocks that include all pages previously written by the LBAs (including valid and invalid data), and then erasing those blocks after moving out valid data not mapped to an LBA targeted by the erasure as taught by Klein.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that ephemeral data (data that is currently valid, but was previously valid) that may otherwise stay around for an indeterminate amount of time is deleted as taught by Klein in [0013-0014].
Regarding claim 6 and analogous claim 16:
The memory system according to claim 4 is made obvious by Seo-NVMe-Isozaki-Klein.
Seo further discloses, wherein the first operation further includes: an unmap operation for invalidating LBAs of the deleted namespace (i.e., the secure erase target data as taught by NVMe in view of Klein as previously applied in claims 1 and 4) (by teaching that when a namespace is deleted, an unmapping operation is performed on the first mapping information (the LBAs of the deleted namespace) which marks the data as invalid and removes the mapping information from the mapping table [0095] [0127-0129]).
Regarding claim 7 and analogous claim 17:
The memory system according to claim 6 is made obvious by Seo-NVMe-Isozaki-Klein.
Seo further discloses, wherein the controller is configured to execute the unmap operation before the copy operation (by teaching that unmapping the LBAs corresponding to the deleted namespace and marking the data as invalid improves the efficiency of the garbage collection operation (i.e., the copying of remaining valid data that is not subject to the deletion request out of the block (i.e., the copy operation as taught by Klein as applied in the rejections for claims 1 and 4 above)) [0095] [0101] [0138]).
Regarding claim 9 and analogous claim 19:
The memory system according to claim 1 is made obvious by Seo-NVMe-Isozaki-Klein.
Seo further discloses, but Klein teaches wherein the secure erase target data includes valid data stored in the first namespace (by teaching that unmapping the LBAs corresponding to the deleted namespace and marking the corresponding data as invalid (i.e., because it was previously valid (i.e., includes valid data stored in the first namespace)) improves the efficiency of the garbage collection operation (i.e., the copying of remaining valid data that is not subject to the deletion request out of the block (i.e., the copy operation as taught by Klein as applied in the rejections for claim 1)) [0095] [0101] [0138]).
Regarding claim 10 and analogous claim 20:
The memory system of claim 1 is made obvious by Seo-NVMe-Isozaki-Klein.
Seo does not explicitly disclose, but Klein teaches, wherein the secure erase target data includes invalid data previously stored as valid data in the first namespace (by teaching that a selective erase operation may erase a particular logical address or particular logical address range (i.e., the logical address range of a namespace such as taught by the combination of Seo in view of NVMe) [0014]. The selective erase operation also erases ephemeral data in invalid pages, such as in the invalid pages of the logical addresses of a namespace which were previously written with valid data [0014]. In this way, both valid and invalid data corresponding to the selective erase operation is erased [Abstract] [0026] [0031] [0042-0044]. The host may send the erase command specifying the logical block addresses [0016]. In response, the controller looks up the addresses in metadata tables and identifies the affected pages and the blocks in which the pages of data are stored [0042]. Valid data that are not the target of erasure are copied from the blocks and then the blocks are erased [0044]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the secure erase of a range of LBAs making up a namespace as taught by Seo in view of NVMe to include identifying the blocks that include all pages previously written by the LBAs (including valid and invalid data, which was previously valid), and then erasing those blocks after moving out valid data not mapped to an LBA targeted by the erasure as taught by Klein.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that ephemeral data (data that is currently valid, but was previously valid) that may otherwise stay around for an indeterminate amount of time is deleted as taught by Klein in [0013-0014].
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Seo-NVMe-Isozaki-Klein in further view of US 2021/0397382 A1 (Shillo).
Regarding claim 2 and analogous claim 12:
The memory system according to claim 1 is made obvious by Seo-NVMe-Isozaki-Klein.
Seo does not explicitly disclose, but Shillo teaches, wherein the controller is further configured to: abort a write command that designates the first namespace and was received before receiving the first command (by teaching that if a later pending command completely overlaps with affected address range of an earlier pending command, and the later pending command replaces the data of the completely overlapped earlier pending command (i.e., such as the way a later pending erase operation which writes all 0’s or 1’s to the block would replace the data of an earlier pending write operation), the earlier pending command may be discarded [0039-0040]. In this way, only the most updated data is written into the overlapped area and unnecessary writes are avoided [0044].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device as taught by Seo-NVMe- Isozaki-Klein with the determination of whether data of an earlier pending write command is completely overlapped with a later pending command that also changes the data (such as an erasure to an LBA range of namespace as taught by Seo-NVMe- Isozaki-Klein), and discarding the earlier pending write command as taught by Shillo.
One of ordinary skill in the art would have been motivated to make this modification because it is an optimization to refrain from writing data to a storage when it is determined that such data will be momentarily overwritten (i.e., such as by an erase command as taught by Seo-NVMe-Isozaki-Klein) as taught by Shillo in [0044].
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Seo-NVMe-Isozaki-Klein in further view of US 2020/0201577 A1 (Longnos).
Regarding claim 3 and analogous claim 13:
The memory system according to claim 1 is made obvious by Seo-NVMe-Isozaki-Klein.
Seo does not explicitly disclose, but Longnos teaches, wherein the controller is further configured to: before starting the first operation, wait for completion of execution of a read command that designates the first namespace and was received before receiving the first command (by teaching that before a memory controller performs a received sanitize request, the memory controller needs to wait until all previous requests sent to the memory are first completed. The requests may include read and write requests [0085]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the secure erase to the namespace as taught by Seo-NVMe-Isozaki-Klein to start after any outstanding I/O commands (such as read commands to the namespace as taught by Seo-NVMe-Isozaki-Klein) are completed as taught by Longnos.
One of ordinary skill in the art would have been motivated to make this modification because the memory controller needs to wait as taught by Longnos in [0085] and otherwise if it is started while there are outstanding I/O commands to the namespace, the Format NVM command may fail as taught by NVMe in [pg. 234, last ¶].
Allowable Subject Matter
Claims 5 and 15 and 8 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 5 (and analogous claim 15) recites, “wherein the controller is further configured to: when the second I/O command is a write command, suspend execution of the second I/O command until the copy operation is completed, and then execute the second I/O command”. However, Isozaki teaches that while data erasing is being performed in an area, commands can be performed normally (i.e., without being rejected/suspended/queued for later) so long as they target an area where the erasing is not occurring. Accordingly, Isozaki does not teach to suspend execution of a second I/O command until the copy operation is completed, because Isozaki teaches to complete the command normally because it is directed to a different area that is not undergoing eras. Furthermore, Seo, Shillo, NVMe, and Klein do not provide reasons why one of ordinary skill in the art would modify the prior art to arrive at the claimed invention. Accordingly, the claims are indicated as allowable.
Claim 8 (and analogous claim 18) recites, “wherein the controller is configured to :execute the unmap operation during execution of the copy operation, and invalidate the valid data among the secure erase target data stored in the one or more first blocks.” However, Seo teaches that the unmapping should occur before garbage collection (before the copy operation) to improve the efficiency of the garbage collection operation [0095]. Furthermore, US Patent Application Publication No. US Patent Application Publication No. US 2021/0073120 A1 (McVay) explains that invalidating of the LBAs that are targeted by the secure erase operation is required before garbage collection is performed (which includes copying the valid data), so that the valid data may be correctly copied and the invalid data correctly erased [0034-0036]. Furthermore, the prior art does not provide a reason why one of ordinary skill in the art would modify the prior art to arrive at the claimed invention. Accordingly, the claims are indicated as allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Patent Application Publication No. US 2015/0161039 A1 (Yeh) – teaches marking target LBA’s for erasure as invalid before erasing the block of data that the target LBA’s belong to [Abstract] [Fig. 26] [0084] [0099-0103].
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
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