DETAILED ACTION
This action is in response to the Application filed on 05/06/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/08/2025 and 06/03/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 9 – 10 and 18 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Patent No. 10,483,849; (hereinafter Saleem).
Regarding claim 1, Saleem [e.g. Figs. 1A, 1B] discloses a voltage regulator comprising: a voltage output that provides an output voltage [e.g. Vout] to a load circuit [e.g. having Iload] coupled to the voltage output to thereby cause a load current [e.g. Iload] in the load circuit; an output capacitor [e.g. Cout] coupled to the voltage output and periodically charged by an output current to thereby maintain the output voltage at the voltage output [e.g. col. 5, lines 25 – 39]; and a current generation circuit [e.g. 135, 155, 140, 132, 105, 110, 115, 145, 160, 120, 125, Lout] configured to: generate a duty cycle signal [e.g. output of 105 or 110] having a plurality of duty cycle intervals each divided into a current-on duration [e.g. PMOS ON PON high, Fig. 1B, t1 – t3] and a current-off duration [e.g. PMOS OFF PON low, Fig. 1B t6 - t7]; maintain the output current at the voltage output during the current-on duration in each of the plurality of duty cycle intervals [e.g. Fig. 1B; t1 – t3, t7 – t9]; remove the output current from the voltage output during the current-off duration in each of the plurality of duty cycle intervals [e.g. Fig. 1B; t6 – t7 and after t-12]; and estimate and report the load current in the load circuit throughout each of the plurality of duty cycle intervals regardless of a presence and an absence of the output current [e.g. col. 2, lines 27 – 35 recite “The method further comprises measuring a dead-time of the switching regulator to estimate the load current in Pulse Width Modulation mode. The method further comprises transitioning to Pulse Frequency Modulation mode, tentatively, when the dead-time is greater than the pulse filter trip point, for estimating the load-current. The load current is estimated in the Pulse Frequency Modulation mode by deriving a slope of a waveform of an output voltage of the switching regulator during the dead-time”. Col. 5, lines 6 – 14 recite “In the PFM mode, the load current is estimated and compared against an upper threshold ‘y’ using a current sense circuit 135, a current comparator circuit 140 and a first multiplexer 145. Similarly, in the PWM mode, the load current is approximately estimated using a pulse filter 150, a zero crossing detector 155 and a second multiplexer 160 in addition to the current sense circuit 135, the current comparator circuit 140 and the first multiplexer 145”].
Regarding claim 9, Saleem [e.g. Figs. 1A, 1B] discloses an electronic power system comprising a voltage regulator, the voltage regulator comprises: a voltage output that provides an output voltage [e.g. Vout] to a load circuit [e.g. having Iload] coupled to the voltage output to thereby cause a load current [e.g. Iload] in the load circuit; an output capacitor [e.g. Cout] coupled to the voltage output and periodically charged by an output current to thereby maintain the output voltage at the voltage output [e.g. col. 5, lines 25 – 39]; and a current generation circuit [e.g. 135, 155, 140, 132, 105, 110, 115, 145, 160, 120, 125, Lout] configured to: generate a duty cycle signal [e.g. output of 105 or 110] having a plurality of duty cycle intervals each divided into a current-on duration [e.g. PMOS ON PON high, Fig. 1B, t1 – t3] and a current-off duration [e.g. PMOS OFF PON low, Fig. 1B t6 - t7]; maintain the output current at the voltage output during the current-on duration in each of the plurality of duty cycle intervals [e.g. Fig. 1B; t1 – t3, t7 – t9]; remove the output current from the voltage output during the current-off duration in each of the plurality of duty cycle intervals [e.g. Fig. 1B; t6 – t7 and after t-12]; and estimate and report the load current in the load circuit throughout each of the plurality of duty cycle intervals regardless of a presence and an absence of the output current [e.g. col. 2, lines 27 – 35 recite “The method further comprises measuring a dead-time of the switching regulator to estimate the load current in Pulse Width Modulation mode. The method further comprises transitioning to Pulse Frequency Modulation mode, tentatively, when the dead-time is greater than the pulse filter trip point, for estimating the load-current. The load current is estimated in the Pulse Frequency Modulation mode by deriving a slope of a waveform of an output voltage of the switching regulator during the dead-time”. Col. 5, lines 6 – 14 recite “In the PFM mode, the load current is estimated and compared against an upper threshold ‘y’ using a current sense circuit 135, a current comparator circuit 140 and a first multiplexer 145. Similarly, in the PWM mode, the load current is approximately estimated using a pulse filter 150, a zero crossing detector 155 and a second multiplexer 160 in addition to the current sense circuit 135, the current comparator circuit 140 and the first multiplexer 145”].
Regarding claim 10, Saleem [e.g. Figs. 1A, 1B] discloses further comprising a power source [e.g. Vdd] and the load circuit [e.g. having Iload], wherein the voltage regulator [e.g. 120, 125, Lout] is coupled between the power source and the load circuit [e.g. as shown].
Regarding claim 18, Saleem [e.g. Figs. 1A, 1B] discloses a method for determining a voltage regulator load current under a light-load condition comprising: providing an output voltage [e.g. Vout] to a load circuit [e.g. having Iload] to thereby cause a load current [e.g. Iload] in the load circuit; periodically charging an output capacitor [e.g. Cout] by an output current to thereby maintain the output voltage [e.g. Fig. 1B]; generating a duty cycle signal [e.g. output of 105 or 110] having a plurality of duty cycle intervals each divided into a current-on duration [e.g. PMOS ON PON high, Fig. 1B, t1 – t3] and a current-off duration [e.g. PMOS OFF PON low, Fig. 1B t6 - t7]; maintaining the output current during the current-on duration in each of the plurality of duty cycle intervals [e.g. Fig. 1B; t1 – t3, t7 – t9]; removing the output current during the current-off duration in each of the plurality of duty cycle intervals [e.g. Fig. 1B; t6 – t7 and after t-12]; and estimating and reporting the load current in the load circuit throughout each of the plurality of duty cycle intervals regardless of a presence and an absence of the output current [e.g. col. 2, lines 27 – 35 recite “The method further comprises measuring a dead-time of the switching regulator to estimate the load current in Pulse Width Modulation mode. The method further comprises transitioning to Pulse Frequency Modulation mode, tentatively, when the dead-time is greater than the pulse filter trip point, for estimating the load-current. The load current is estimated in the Pulse Frequency Modulation mode by deriving a slope of a waveform of an output voltage of the switching regulator during the dead-time”. Col. 5, lines 6 – 14 recite “In the PFM mode, the load current is estimated and compared against an upper threshold ‘y’ using a current sense circuit 135, a current comparator circuit 140 and a first multiplexer 145. Similarly, in the PWM mode, the load current is approximately estimated using a pulse filter 150, a zero crossing detector 155 and a second multiplexer 160 in addition to the current sense circuit 135, the current comparator circuit 140 and the first multiplexer 145”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 2 – 3 and 11 – 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saleem in view of US Pub. No. 2016/0336857; (hereinafter Ilango).
Regarding claim 2 and claim 11, Saleem fails to disclose wherein the current generation circuit is further configured to generate the duty cycle signal based on a target of the output voltage, and the voltage regulator further comprises a voltage control circuit configured to determine the target of the output voltage.
Ilango [e.g. Fig. 1] teaches wherein the current generation circuit is further configured to generate the duty cycle signal [e.g. output of U3 to M1] based on a target of the output voltage [e.g. VREF], and the voltage regulator further comprises a voltage control circuit [e.g. U8] configured to determine the target of the output voltage [e.g. VREF].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Saleem by wherein the current generation circuit is further configured to generate the duty cycle signal based on a target of the output voltage, and the voltage regulator further comprises a voltage control circuit configured to determine the target of the output voltage as taught by Ilango in order of being able to maintain the output voltage between desired limits.
Regarding claim 3 and claim 12, Saleem [e.g. Figs. 1A, 1B] discloses wherein the current generation circuit comprises: a voltage converter [e.g. 120, 125, Lout] configured to generate a switching voltage at a switching node [e.g. SW_OUT] during the current-on duration in each of the plurality of duty cycle intervals [e.g. Fig. 1B] based on an input voltage [e.g. Vdd]; and a power inductor [e.g. Lout] coupled between the switching node and the voltage output and configured to induce the output current during the current-on duration based on the switching voltage [e.g. Fig. 1B].
Saleem fails to disclose a pulse-width modulation (PWM) controller configured to generate the duty cycle signal based on the target of the output voltage and a feedback of the output voltage.
Ilango [e.g. Fig. 1] teaches a pulse-width modulation (PWM) controller [e.g. U3] configured to generate the duty cycle signal [e.g. output of U3 to M1] based on the target of the output voltage [e.g. Vref] and a feedback of the output voltage [e.g. FB].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Saleem by a pulse-width modulation (PWM) controller configured to generate the duty cycle signal based on the target of the output voltage and a feedback of the output voltage as taught by Ilango in order of being able to maintain the output voltage between desired limits.
Claims 4, 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saleem in view of Ilango and further in view of US Pub. No. 2010/0320986; (hereinafter Collins).
Regarding claim 4 and claim 13, Saleem fails to disclose wherein the PWM controller is further configured to determine the current-on duration and the current-off duration in each of the plurality of duty cycle intervals such that the output capacitor can be charged to the target of the output voltage during the current-on duration and discharged to maintain the output voltage at or above a threshold voltage during the current-off duration.
Collins [e.g. Figs. 3 - 4] teaches wherein the PWM controller [e.g. 60, 70, 44] is further configured to determine the current-on duration [e.g. Fig. 4; ton] and the current-off duration [e.g. lower level of swinging node voltage] in each of the plurality of duty cycle intervals such that the output capacitor [e.g. Vout corresponding to output voltage at 33] can be charged to the target of the output voltage during the current-on duration [e.g. Fig. 4; output voltage at Vupr level (max)] and discharged to maintain the output voltage at or above a threshold voltage [e.g. Vlwr] during the current-off duration [e.g. the output voltage is discharged to a minimum level Vlwr].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Saleem by wherein the PWM controller is further configured to determine the current-on duration and the current-off duration in each of the plurality of duty cycle intervals such that the output capacitor can be charged to the target of the output voltage during the current-on duration and discharged to maintain the output voltage at or above a threshold voltage during the current-off duration as taught by Collins in order of being able to maintain the output voltage between desired limits.
Regarding claim 19, Saleem fails to disclose further comprising determining the current-on duration and the current-off duration in each of the plurality of duty cycle intervals such that the output capacitor can be charged to a target of the output voltage during the current-on duration and discharged to maintain the output voltage at or above a threshold voltage during the current-off duration.
Collins [e.g. Figs. 3 - 4] teaches further comprising determining the current-on duration [e.g. Fig. 4; ton] and the current-off duration [e.g. lower level of swinging node voltage] in each of the plurality of duty cycle intervals such that the output capacitor [e.g. Vout corresponding to output voltage at 33] can be charged to a target of the output voltage during the current-on duration [e.g. Fig. 4; output voltage at Vupr level (max)] and discharged to maintain the output voltage at or above a threshold voltage [e.g. Vlwr] during the current-off duration [e.g. the output voltage is discharged to a minimum level Vlwr].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Saleem by further comprising determining the current-on duration and the current-off duration in each of the plurality of duty cycle intervals such that the output capacitor can be charged to a target of the output voltage during the current-on duration and discharged to maintain the output voltage at or above a threshold voltage during the current-off duration as taught by Collins in order of being able to maintain the output voltage between desired limits.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 5 – 8 and 14 – 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 5 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the current generation circuit further comprises a load current determination circuit that comprises: a skip timer circuit configured to determine the current-off duration in each of the plurality of duty cycle intervals; and a processing circuit configured to estimate the load current throughout each of the plurality of duty cycle intervals based on the input voltage, the output voltage, an inductance of the power inductor, the determined current-off duration in each of the plurality of duty cycle intervals, and a duration of each of the plurality of duty cycle intervals”.
The primary reason for the indication of the allowability of claim 14 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the current generation circuit further comprises a load current determination circuit that comprises: a skip timer circuit configured to determine the current-off duration in each of the plurality of duty cycle intervals; and a processing circuit configured to estimate the load current throughout each of the plurality of duty cycle intervals based on the input voltage, the output voltage, an inductance of the power inductor, the determined current-off duration in each of the plurality of duty cycle intervals, and a duration of each of the plurality of duty cycle interval”.
The primary reason for the indication of the allowability of claim 20 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising estimating the load current throughout each of the plurality of duty cycle intervals based on an input voltage, the output voltage, an inductance of a power inductor inducing the output current, the current-off duration in each of the plurality of duty cycle intervals, and a duration of each of the plurality of duty cycle intervals”.
Claims 6 – 8 and 15 – 17 are objected to because inherent dependency on claim 5 and 14.
Conclusion
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
