DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 102(a1)/(a2) as being anticipated by Korson et al. (US 2004/0046615).
Regarding claim 1, Korson et al. discloses a circuit, comprising: a read data port [FIG. 1: memory output signal] configured to be coupled to a memory [FIG. 1: memory] having stored therein alternate runs of data at different memory addresses [FIG. 1: memory output signal]; wherein the read data port is configured to receive data read from said memory [¶0011: the control circuit drives the non-clock inputs to the memory through line 3] with a memory access time in a sequence of read events [] from the different memory addresses [¶0007: an on-chip measurement oscillation circuit performs both the access time measurement and the cycle time measurement of a device under test where the circuit is a read mode and every cycle is a read operation]; wherein the data read from the memory in subsequent read events in the sequence of read events exhibits toggling in response to said alternate runs of data [¶0011: the control circuit drives the non-clock inputs to the memory through line 3, the control circuit to force an address bit for the next cycle to be the inverse of the current cycle during testing, by using the control circuit to preload address with a logic o and another address with logic 1 then every cycle will read from the opposite address causing a change on the output of memory]; an edge detector coupled to the read data port, wherein the edge detector is configured to detect toggling of data read from said memory in the subsequent read events [¶0017, 0021: pulse generator outputs two signals in response to change in logic level shown in FIG. 2]; and triggering circuitry coupled to the edge detector and configured to produce a trigger signal to start a new read event in said sequence of read events in response to said toggling of data which indicates an end of a previous read event in the sequence of read events [FIG. 2, ¶0019, 0021: during set-up, address A0 was set to logic 0 while address A1 was set to logic 1, pulse generator at the start of testing will cause the address that is read to change from A0 to A1, from logic 0 to logic 1 and through the ring oscillator the output of the memory will continue to toggle as the address that is read continues to switch between A0 and A1, a change on pulse generator input line will create a change in the logic level on both output lines after a delay]; wherein a duration of said alternate runs of data in said sequence of read events is indicative of said memory access time [¶0025: the cycle time is calculated by multiplying the passing frequency by 32 to reverse the effect of the divide down circuit and then multiplying again by 2 to arrive at the clock frequency and not the memory output frequency, this frequency is then inverted to determine the time period of the clock cycle].
Regarding claim 2, Korson et al. discloses the circuit of claim 1, comprising an address calculator triggered by said trigger signal and configured to produce different memory addresses to said memory in said sequence of read events from different memory addresses [¶0021].
Regarding claim 3, Korson et al. discloses the circuit of claim 1, comprising a finite state machine (FSM) configured to implement said sequence of read events from the different memory addresses, wherein the FSM comprises: a first input configured to receive a start signal for controlling starting said sequence of read events from different memory addresses [FIG. 2, ¶0016]; and a second input configured to receive a clock signal [¶0024]; wherein the FSM is configured to determine the cumulative duration of said alternate runs of data read in the sequence of read events started by said start signal based on said clock signal [¶0025].
Regarding claim 4, Korson et al. discloses the circuit of claim 3, comprising a counter triggered by said trigger signal and configured to produce a count value of the number of read events in said sequence of read events, wherein the FSM is configured to stop the sequence of read events from different memory addresses in response to the count value produced by counter reaching a count threshold [¶0023].
Regarding claim 5, Korson et al. discloses the circuit of claim 1, wherein the read data port comprises: an AND gate coupled to receive data output from the memory and provide a first signal indicative of a slowest run of logical ones in said alternate runs of data [FIG. 1-2, ¶0015-16: where the universal NOR gate implements the function of an AND gate]; an OR gate coupled to receive data output from the memory and provide a second signal indicative of a slowest run of logical zeros in said alternate runs of data [FIG. 1]; and a multiplexer configured to apply to said triggering circuitry one or the other of the first signal and the second signal based on a state signal having a first value and a second value, respectively, the state signal generated in response to toggling at the end of a previous read event in the sequence of read events [FIG. 1-2].
Regarding claim 7, the rationale in the rejection of claim 1 is herein incorporated.
Regarding claim 8, Korson et al. discloses the memory device of claim 7, wherein the memory comprises one of: a flash memory, a floating gate transistor memory, a magneto-resistive random-access memory or a phase change memory [¶0011].
Regarding claim 9, the rationale in the rejection of claim 1 is herein incorporated.
Regarding claim 10, Korson et al. discloses the circuit of claim the method of claim 9, wherein detecting toggling comprises: logically ANDing data output from the memory to generate a first signal indicative of a slowest run of logical ones in said alternate runs of data [FIG. 1-2]; and logically ORing data output from the memory to generate a second signal indicative of a slowest run of logical zeros in said alternate runs of data [FIG. 1-2].
Regarding claim 11, Korson et al. discloses the method of claim 10, wherein producing the trigger signal comprises selecting one or the other of the first signal and the second signal based on a state signal having a first value and a second value, respectively, wherein the state signal is generated in response to toggling at the end of a previous read event in the sequence of read events [¶0023].
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. IIJIMA (US20200073555) discloses a memory access circuit and NAND device connected by an address bus designating and address for the memory access, a data bus for communicating read data, a read enable signal used as a clock signal indicating transmission of a read transfer period and the timing of acquiring the read data.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
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