DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 10/09/2024, 04/18/2025, 07/02/2025 have been considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 5-11, 14-16, 19-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-5, 9, 15 of U.S. Patent No.US 12,314,162. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of US 12,314,162 claims the subject matter claimed by instant claims 2, 5-7. Claims 4-5 of US 12,314,162 respectively claim the subject matter claimed by instant claims 8-9. Claim 9 of US 12,314,162 claims the subject matter claimed by instant claims 10, 11,14-16, 19. Claim 15 of US 12,314,162 claims the subject matter claimed by instant claims 20-21. Refer to the comparison table below.
19/1999869 US 12,314,162
2. A receiver to sample a signal, the receiver comprising:an equalizer including a data sampler to produce binary data samples of the signal and feedback to equalize the signal responsive to the data samples and a tap value; anda tap-value generator including:a monitor sampler to produce monitor samples of the signal; the tap-value generator to generate the tap value for the equalizer as a function of the monitor samples and only one of two values of the binary data samples.
1. A signal receiver to sample a plurality of digital signals conveyed in parallel from a memory controller and timed to a timing-reference signal from the memory controller, the signal receiver comprising: a plurality of decision-feedback equalizers, each decision-feedback equalizer including: a sampler having a sampler input port to receive a respective one of the plurality of digital signals conveyed in parallel from the memory controller; a tap port to receive a respective equalizer-tap value; and a timing port to receive the timing-reference signal from the memory controller; each decision-feedback equalizer to equalize the respective digital signal on the sampler input port responsive to the respective equalizer-tap value; and an adaptive tap-value generator coupled to the tap port of one of the decision-feedback equalizers, the adaptive tap-value generator including a monitor sampler, to produce monitor samples of the digital signal to the one of the decision-feedback equalizers, and to generate the respective equalizer-tap value for the one of the decision-feedback equalizers as a function of least-mean squares of errors at the sampler input port of the one of the decision-feedback equalizers; wherein the digital signals are binary signals, the adaptive tap-value generator generating the equalizer-tap values for the one of the decision-feedback equalizers as a function of the errors for only one of two levels of the digital signal.
The receiver of claim 2, wherein the tap value is one of a plurality of tap values for the equalizer and the tap-value generator generates the tap values as the function of the monitor samples and the one of the two values.
Refer to Claim 1
The receiver of claim 2, wherein the function comprises a least-mean square.
Refer to claim 1
7. The receiver of claim 2, further comprising a second equalizer including a second data sampler to produce second binary data samples of a second signal and second feedback to equalize the second signal responsive to the second data samples and the tap value.
4. The signal receiver of claim 1, wherein the adaptive tap-value generator is coupled to the tap port of more than one of the decision-feedback equalizers.
8. The receiver of claim 7, wherein the tap-value generator is coupled to the second feedback to provide the tap value.
Refer to Claim 4
9. The receiver of claim 2, further comprising a plurality an analog front end to equalize the signal to the equalizer.
5. The signal receiver of claim 1, further comprising a plurality of analog front ends, one for each of the plurality of decision-feedback equalizers, for equalizing the respective digital signals to the decision-feedback equalizers.
10. An integrated circuit for receiving a data signal conveyed from a memory controller, the integrated circuit comprising:a decision-feedback equalizer including a sampler having a sampler input port to receive the data signal from the memory controller, an output port to send data samples, and a tap port to receive a tap value, the decision-feedback equalizer to equalize the data signal responsive to the tap value; andan adaptive tap-value generator coupled to the tap port of the decision-feedback equalizers, the adaptive tap-value generator including a monitor sampler to produce monitor samples of the data signal and generate the tap value for the decision-feedback equalizer as a function of least-mean squares of errors to the sampler input port of the decision-feedback equalizer; the adaptive tap-value generator generating the tap value for the decision-feedback equalizer as a function of the least-mean square of error for only one value of the data samples.
7. An integrated circuit for receiving digital signals conveyed in parallel from a memory controller and timed to a timing-reference signal from the memory controller, the integrated circuit comprising: a plurality of decision-feedback equalizers, each decision-feedback equalizer including a sampler having a sampler input port to receive a respective one of the plurality of digital signals conveyed in parallel from the memory controller, a tap port to receive a respective equalizer-tap value, and a timing port to receive the timing-reference signal from the memory controller, each decision-feedback equalizer to equalize the respective digital signal responsive to the respective equalizer-tap value; and an adaptive tap-value generator coupled to the tap port of one of the decision-feedback equalizers, the adaptive tap-value generator including a monitor sampler, to produce monitor samples of the digital signal to the one of the decision-feedback equalizers, and to generate the respective equalizer-tap value for the one of the decision-feedback equalizers as a function of least-mean squares of errors to the sampler input port of the decision-feedback equalizer; wherein the digital signals are binary signals, the adaptive tap-value generator generating the equalizer-tap values for the one of the decision-feedback equalizers as a function of the least-mean square of error for only one of two levels of the digital signal to the one of the decision-feedback equalizer.
8. The integrated circuit of claim 7, wherein the digital signals conveyed in parallel from the memory controller represent data for storage, the integrated circuit further comprising an array of memory cells to store the data.
9. The integrated circuit of claim 8, further comprising an output port to convey the equalized digital signals from the integrated circuit
11. The integrated circuit of claim 10, further comprising an array of memory cells to store data represented by the data signal
Refer to the limitations of claim 8, incorporated into the limitations of claim 9 above.
14. The integrated circuit of claim 10, wherein the tap value is one of a plurality of tap values for the equalizer and the tap-value generator generates the tap values as the function of the monitor samples and the one value.
Refer to the limitations of claim 7, incorporated into the limitations of claim 9 above.
15. The integrated circuit of claim 10, wherein the function comprises a least-mean square.
Refer to the limitations of claim 7, incorporated into the limitations of claim 9 above.
16. The integrated circuit of claim 10, further comprising a second equalizer including a second data sampler to produce second binary data samples of a second signal and second feedback to equalize the second signal responsive to the second data samples and the tap value.
Refer to the limitations of claim 7, incorporated into the limitations of claim 9 above.
19. The integrated circuit of claim 10, wherein the data samples express data as the one value and one alternative value.
Refer to the limitations of claim 7, incorporated into the limitations of claim 9 above.
20. A module comprising: a module connector to receive data signals, address signals, and an address-timing signal from a memory controller; anda data-buffer component coupled to the module connector to receive the data signals, the data-buffer component including:an equalizer including a data sampler to produce binary data samples of the signal and feedback to equalize the signal responsive to the data samples and a tap value; and a tap-value generator including a monitor sampler to produce monitor samples of the signal, wherein the tap-value generator generates the tap value for the equalizer as a function of the monitor samples and only one of two values of the binary data samples.
15. A memory module comprising: a module connector to receive data signals, a data-timing signal, address signals, and an address-timing signal from a memory controller; a data-buffer component coupled to the module connector to receive the data signals and the data-timing signal, the data-buffer component including: a plurality of decision-feedback equalizers, each decision-feedback equalizer including a sampler having a sampler input port to receive a respective one of the data signals conveyed in parallel from the memory controller, a tap port to receive a respective equalizer-tap value, and a timing port to receive the data-timing signal from the memory controller, each decision-feedback equalizer to equalize the respective data signal responsive to the respective equalizer-tap value; and an adaptive tap-value generator coupled to the tap port of one of the decision-feedback equalizers, the adaptive tap-value generator including a monitor sampler, to produce monitor samples of the data signal to the one of the decision-feedback equalizers, and to generate the respective equalizer-tap value for the one of the decision-feedback equalizers as a function of least-mean squares of errors to the sampler input port of the decision-feedback equalizer; an address-buffer component coupled to the module connector to receive the address signals and the address-timing signal from the memory controller, the address-buffer component including an address-output port to relay the address signals; and a memory component having an array of memory cells, a memory-component data port coupled to the decision-feedback equalizers to receive the equalized data signals, and a memory-component address port coupled to the address-buffer component to receive the relayed address signals.
21. The module of claim 20, further comprising a second equalizer including a second data sampler to produce second binary data samples of a second signal and second feedback to equalize the second signal responsive to the second data samples and the tap value.
Refer to Claim 15
Claim Objections
Claims 9-21 are objected to because of the following informality:
Claim 9 the recited “a plurality of analog front end” should be “a plurality of front ends”.
Claim 10, lines 7-8 the recited “the decision-feedback equalizers” should be “the decision-feedback equalizer”. Claim 10 previously claims “a decision-feedback equalizer” (line 3 of claim 10).
Dependent claims 11-17, 19 are also objected to since they depend on objected claim 10.
Claim 18 the recited “a plurality of analog front end” should be “a plurality of front ends”.
Claim 20, line 6, the recited “of the signal” should be “of the data signals” to match the “data signals” of lines 2 and 4.
Claim 20, lines 7, 9 the recited “the signal” should be “the data signals” to match the “data signals” of lines 2 and 4.
Dependent claim 21 is also objected to since it depends on objected claim 20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10, lines 9-11 recite: “as a function of least-mean squares of errors to the
sampler input port of the decision-feedback equalizer;” It is unclear what the claimed “to the sampler input port” attempts to claim.
Dependent claims 11-19 are also rejected since they depend on rejected claim 10.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 15 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 15 (depends on claim 10) and claims “wherein the function comprises a least-mean square”. However, claim 10 already claims “a function of least-mean squares of errors” (lines 9-10) and “a function of the least-mean square of error” in line 13.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2, 5-6, 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2015/0078430).
With respect to claim 2, Lee et al. disclose: A receiver (refer to the receiver 100 of Fig. 1, [0006]) to sample a signal (e.g. refer to data sampler 155 and the last sentence of [0018] “…data samples Datan” ), the receiver (100) comprising: an equalizer (refer to DFE 125 and 145 and 155 (and their connections and their arrangement to 125) of the Sampling Logic 130, these components correspond to the claimed equalizer because 145 and 155 provide the decision feedback used by DFE 125, Datan corresponds to (or is at least recognized to correspond to) a series of equalized data samples (obtained from the equalized Veq’) refer to [0017]-[0018]) including a data sampler (refer to 145 and 155 corresponding to the claimed data sampler and the approximate second half of [0018] refer to data samples Datan , they are binary “1” or “0” refer the Figures 4A-4D the “1” and “0” values, [0025]) to produce binary data samples (as explained above) of the signal and feedback (Fig. 1, the output of the data sampler Datan is fedback to the DFE portion of the equalizer) to equalize the signal responsive to the data samples (responsive to the feedback the Datan) and a tap value (one of tap values αN, α2 used by 125, [0017]); and a tap-value generator (Fig. 1, refer to Adaptation Engine 135 and 140 and 150 of Sampling Logic, corresponding to the claimed tap-value generator, lines 1-3 of [0019], [0022] generates tap values α[N:2] (e.g. α[3:2] of Fig. 2) and used by the DFE portion of the equalizer) including: a monitor sampler (refer to 140 and 150 of Sampling Logic 130) to produce monitor samples of the signal (refer to the error samples Errn error (monitor) samples, approximate first half of [0018]); the tap-value generator to generate the tap value (one of αN, α2) for the equalizer as a function of the monitor samples (the supplied Errn) and only one of two values of the binary data samples (only one value of the binary data samples (logic one) and determined by use of Dlev, [0026] “The forgoing error comparisons are based upon the upper signal level defined by voltage Dlev and applied via amplifier 140. Adaptation engine 135 only updates the tap values α[N:0] based upon measurements that take place when the current data sample Datan is a logic one...”).
With respect to claim 5, Lee et al. disclose: wherein the tap value is one of a plurality of tap values (one of α[N:2]) for the equalizer and the tap-value generator generates the tap values as the function of the monitor samples and the one of the two values (generated as the function of the monitor samples (Errn)).
With respect to claim 6, Lee et al. disclose: wherein the function comprises a least-mean square (refer to at least lines 1-3 of [0023] the function comprises a sign-sign LMS algorithm).
With respect to claim 9, Lee et al. disclose: further comprising a plurality an analog front end to equalize the signal to the equalizer (Fig. 1, refer to front end equalizer 120 which produces Veq supplied to the equalizer. Fig. 6 shows an embodiment of 120 and refer to at least lines 1-8 of [0029], the equalizer stages 600 and 605 correspond to a plurality of analog front ends).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0078430) in view of Li (US 2010/0241679).
With respect to claim 3, Lee et al. disclose: the tap-value generator including
circuitry (e,g. circuitry of Fig. 3) to (process) differences between the data samples and the monitor samples (refer to the sign-sign LMS used in Fig. 2 and shown in more detail in Fig. 3, the data samples Datan and monitor samples Errn are processed within at least Fig. 3).
Lee et al. do not expressly disclose: accumulate.
Implementing generating of a signed signal (+1/-1), Li et al. disclose: accumulate (Fig. 2, refer to accumulator ACC 248 which receives 256 obtaining from XORing (in 242) signals 130 and signals 228, [0033], and approximate second half of [0041] “…an ACC (accumulator) 248…” and [0042] “…signal 238 can include a signed digital signal, e.g., a signed binary code, having a value "+1", "0", or "-1"...”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. (Fig. 3) based on the teachings of Li regarding sign generation (using an accumulator that accumulates differences of signals out of an XOR gate) and substitute logic block 302 (generates signs +1/-1) with the disclosed accumulator to obtain the predictable result of sign generation.
With respect to claim 4, modified Lee et al. disclose: wherein the circuitry includes an exclusive OR gate to compare the data samples with the monitor samples (XOR gate 300 as shown in Fig. 3).
Claims 10-11, 14-15, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0078430) in view of Hollis et al. (US 2018/0278461).
With respect to claim 10, as best understood, Lee et al. disclose: decision-
feedback equalizer (Fig. 1, refer to DFE 125 and 145 and 155 (of the Sampling Logic) and their arrangement and connection to DFE 125. Because the equalized data samples Datan are feedback to DFE 125 (by 145 and 155), the DFE 125 and 145 and 155 are interpreted as corresponding to the claimed “decision-feedback equalizer”) including a sampler (refer to 145 and 155 corresponding to the claimed data sampler and the approximate second half of [0018] refer to data samples Datan ), having a sampler input port to receive the data signal from (the claimed decision-feedback equalizer receives Veq version of the data signal from a transmitter [0006] and the sampler input port receives Veq’), an output port to send data samples (implicit output port outputting Datan), and a tap port to receive a tap value (implicit tap port receiving one of αN, α2 [0017]), the decision-feedback equalizer to equalize the data signal responsive to the tap value ([0017]); and an adaptive tap-value generator (Fig. 1, adaptation Engine 135 and 140 and 150 (of the Sampling Logic) correspond to the claimed adaptive tap-value generator, approximate second half of [0018], [0019], [0022]) coupled to the tap port of the decision-feedback equalizers (as shown in Fig. 1, supplying one of αN, α2), the adaptive tap-value generator including a monitor sampler (140 and 150) to produce monitor samples of the data signal (refer to the error samples Errn error (monitor) samples, approximate first half of [0018]) and generate the tap value for the decision-feedback equalizer (one of αN, α2) as a function of least-mean squares of errors to the sampler input port of the decision-feedback equalizer ([0022]-[0023], refer to the disclosed sign-sign LMS algorithm used to generate a tap value/values, one of αN, α2 is generated according to errors (differences) between the Datan and Errn , corresponding to the claimed errors to the sampler input port ); the adaptive tap-value generator generating the tap value for the decision-feedback equalizer as a function of the least-mean square of error for only one value of the data samples ([0026], only one value of the binary data samples (logic one) and determined by use of Dlev).
Lee et al. do not disclose: from the memory controller (instead, discloses from a transmitter, as pointed out above).
Implementing DFE equalization at a receiver of a memory device that receives data transmitted from a memory controller , Hollis et al. disclose: from the memory controller ([0017] and Fig. 1, the host is a memory controller and the memory device includes a receiver in each of the data buffers which performs DFE equalization on the received data signals [0033], [0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the transmitter of Lee et al. as a memory controller as taught by Hollis et al. so that the system of Fig. 1 of Lee et al. (comprising a transmitter and receiver) corresponds to a memory system comprising a memory controller and a memory device and has the improved intersymbol interference (ISI) cancellation circuitry of Lee et al., (Lee et al., [0002], [0015] and approximate second half of [0017]) at the receiver (memory)).
With respect to claim 11, modified Lee et al., discloses: further comprising an array of memory cells to store data represented by the data signal (modified Lee et al., the memory device (receiver) includes data buffers and memories and Fig. 2 ([0023]) discloses that within each memory a memory array exists (of memory cells [0026]. The equalizer of modified Lee et al. is location within a data buffer (e.g. within a binary receiver circuit 412, [0033] and data represented by the data signal (equalized data) is processed and transferred to an array of memory cells (included in 212, [0026]) within the memory of Fig. 2, [0023]-[0026]).
Claims 14-15, 18 are rejected based on the reasoning used to reject claims 5-6, 9 above.
With respect to claim 19, modified Lee et al. disclose: wherein the data samples express data as the one value and one alternative value (the data samples Datan are binary logic “1” or “0” refer the Figures 4A-4D the “1” and “0” values, [0025] and [0026] logic one and logic zero).
18. Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0078430) in view of Hollis et al. (US 2018/0278461) and further in view of Li (US 2010/0241679).
With respect to claim 12, modified Lee et al. disclose: the tap-value generator including circuitry (e,g. circuitry of Fig. 3) to (process) differences between the data samples and the monitor samples (refer to the sign-sign LMS used in Fig. 2 and shown in more detail in Fig. 3, the data samples Datan and monitor samples Errn are processed within at least Fig. 3).
Lee et al., Hollis et al. do not expressly disclose: accumulate.
Implementing generating of a signed signal (+1/-1), Li et al. disclose: accumulate (Fig. 2, refer to accumulator ACC 248 which receives 256 obtaining from XORing (in 242) signals 130 and signals 228, [0033], and approximate second half of [0041] “…an ACC (accumulator) 248…” and [0042] “…signal 238 can include a signed digital signal, e.g., a signed binary code, having a value "+1", "0", or "-1"...”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. (Fig. 3) based on the teachings of Li regarding sign generation (using an accumulator that accumulates differences of signals out of an XOR gate) and substitute logic block 302 (generates signs +1/-1) with the disclosed accumulator to obtain the predictable result of sign generation.
With respect to claim 13, modified Lee et al. disclose: wherein the circuitry includes an exclusive OR gate to compare the data samples with the monitor samples (XOR gate 300 as shown in Fig. 3).
19. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hollis et al. (US 2018/0278461) in view of Jeon et al. (US 2018/0174636) and Lee et al. (US 2015/0078430).
With respect to claim 20, Hollis et al. disclose: a module connector (e.g. refer to memory device 104 of Fig. 1 the claimed module connector corresponds to the connector which connects the signals on command/address bus 112 and data bus 114 from the host 102 to 104, [0017]-[0019]. Also refer to Fig. 10 (for example), [0046]-[0047] an embodiment of components of Fig. 1 e.g. the host, memory device and data buffers of Fig. 1) to receive data signals (data signals on the data bus 114 and e.g. refer to the host_side data of Fig. 5), address signals (address signals over command/address bus 114, [0017], optionally refer to [0047]), from a memory controller (the host of Fig. 1, last sentence of [0017]); and a data-buffer component coupled to the module connector to receive the data signals (Fig. 1, refer to at least one of the data buffers 108(x) coupled to the module connector to receive the data signals, also refer to [0047] for example data buffers 1008, “Each of the data buffers 1008 may implemented as one or more of the data buffers 108(1)-(N) of FIG. 1”), the data-buffer component including: an equalizer ([0032]-[0033] an equalizer is included in a binary receiver circuit within the data buffer component).
Hollis et al. do not disclose: and an address-timing signal, an equalizer including a data sampler to produce binary data samples of the signal and feedback to equalize the signal responsive to the data samples and a tap value; and a tap-value generator including a monitor sampler to produce monitor samples of the signal, wherein the tap-value generator generates the tap value for the equalizer as a function of the monitor samples and only one of two values of the binary data samples.
In the same field of endeavor, Jeon et al. disclose: and an address-timing signal (Fig. 3, command/address input buffer 210 ([0042]) receives (from a memory controller [0044]) CMD/ADDR and address-timing signal (CLK) and samples the command CMD and address ADDR based on the clock signal CLK. Block 220 receives the sampled command and address and generates at least CTL signal ([0048]-[0050]. Also refer to Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the module connector of the memory device of Hollis et al. to additionally receive an address-timing signal from the memory controller (host 102) CLK, as taught by Jeon et al. and use the address-timing signal in the C/A buffer to sample the received command and address signals and supply them a control logic (e.g. 220 of Jeon et al.) to generate control signals that set the operating mode of the memory device and generate a control signal that is supplied to the data buffer and used to generate a strobe signal for a data transmitter of the data buffer (Jeon et al., [0044]-[0047], [0050], [0070]-[0071]).
Modified Hollis et al., Jeon et al. do not disclose: an equalizer including a data sampler to produce binary data samples of the signal and feedback to equalize the signal responsive to the data samples and a tap value; and a tap-value generator including a monitor sampler to produce monitor samples of the signal, wherein the tap-value generator generates the tap value for the equalizer as a function of the monitor samples and only one of two values of the binary data samples.
Implementing equalization, Lee et al. disclose: an equalizer (refer to DFE 125 and 145 and 155 (and their connections and their arrangement to 125) of the Sampling Logic 130, these components correspond to the claimed equalizer because 145 and 155 provide the decision feedback used by DFE 125, Datan corresponds to (or is at least recognized to correspond to) a series of equalized data samples (obtained from the equalized Veq’) refer to [0017]-[0018]) including a data sampler (refer to 145 and 155 corresponding to the claimed data sampler and the approximate second half of [0018] refer to data samples Datan , they are binary “1” or “0” refer the Figures 4A-4D the “1” and “0” values, [0025]) to produce binary data samples (as explained above) of the signal and feedback (Fig. 1, the output of the data sampler Datan is fedback to the DFE portion of the equalizer) to equalize the signal responsive to the data samples (responsive to the feedback the Datan) and a tap value (one of tap values αN, α2 used by 125, [0017]); and a tap-value generator (Fig. 1, refer to Adaptation Engine 135 and 140 and 150 of Sampling Logic, corresponding to the claimed tap-value generator, lines 1-3 of [0019], [0022] generates tap values α[N:2] (e.g. α[3:2] of Fig. 2) and used by the DFE portion of the equalizer) including: a monitor sampler (refer to 140 and 150 of Sampling Logic 130) to produce monitor samples of the signal (refer to the error samples Errn error (monitor) samples, approximate first half of [0018]); the tap-value generator to generate the tap value (one of αN, α2) for the equalizer as a function of the monitor samples (the supplied Errn) and only one of two values of the binary data samples (only one value of the binary data samples (logic one) and determined by use of Dlev, [0026] “The forgoing error comparisons are based upon the upper signal level defined by voltage Dlev and applied via amplifier 140. Adaptation engine 135 only updates the tap values α[N:0] based upon measurements that take place when the current data sample Datan is a logic one...”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the equalizer within the binary receiver circuit of Hollis et al. as the equalizer (DFE 125 and 145, 155) and the tap-value generator (135, and 140, 150) of Lee et al. to implement inter-symbol interference (ISI) cancellation (Lee et al., [0002], approximate second half of [0017] and [0023]).
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SOPHIA VLAHOS
Examiner
Art Unit 2633
/SOPHIA VLAHOS/Primary Examiner, Art Unit 2633
10/8/2026
