DETAILED ACTION
This office action is in response to the application filed on 10/16/2009. Claims 1-14 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawing
The drawing submitted on 05/06/2025 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/06/2025, 08/25/2025, and 05/21/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Roh et al. (US Patent or PG Pub. No. 20040113870, hereinafter ‘870).
Claim 1, ‘870 teaches a cascaded converter (e.g., see Fig. 4-6), comprising: four capacitors, comprising a first capacitor (e.g., Cu1), a second capacitor (e.g., Cu2), a third capacitor (e.g., Cd2), and a fourth capacitor (e.g., Cd1) connected in series, wherein the first capacitor and the second capacitor are jointly connected at a first node (e.g., the node connecting Cu1 and Cu2), the second capacitor and the third capacitor are jointly connected at a second node (e.g., the node connecting Cd2 and Cu2), the third capacitor and the fourth capacitor are jointly connected at a third node (e.g., the node connecting Cd1 and Cd2), and the first capacitor is further connected to a first voltage node (e.g., +Vs, see Fig. 4), and the fourth capacitor is further connected to a second voltage node (e.g., GND, see Fig. 4), four switches, comprising a first switch (e.g., the circuit comprising Df2, Du2, Su1), a second switch (e.g., the circuit comprising Du/Dr2), a third switch (e.g., the circuit comprising Dd/ Df1), and a fourth switch (e.g., the circuit comprising Dr1,Dd4, Sd1) connected in series, wherein the first switch and the second switch are jointly connected at a fourth node (e.g., the node connecting Dr2, Du, with Df2m Su1), the second switch and the third switch are jointly connected at the second node, the third switch and the fourth switch are jointly connected at a fifth node (e.g., the node connecting Dr1/Sd1 with Lr1 through Dr1 ), and the first switch is further connected to the first voltage node, and the fourth switch is further connected to the second voltage node (e.g., see Fig. 4), a fifth switch (e.g., Sr2) and a first inductor (e.g., Lr2), jointly connected at a sixth node (e.g., the node connecting Sr2 with Lr2), and the fifth switch further connected to the first node, the first inductor further connected to the fourth node (e.g., Lr2 connecting with Df2/Su1 through Dr2, see Fig. 4), a sixth switch (e.g., Sf1) and a second inductor (e.g., Lf1), jointly connected at a seventh node (e.g., the node connecting Sf1 and Lf1), and the sixth switch (S6) further connected to the third node (N3), the second inductor (L2) further connected to the fifth node (e.g., Lr1 connecting with Dr1/Sd1 through Df1, see Fig. 4), and a seventh switch (e.g., Du3, Dd1), connected between the sixth node (N6) and the seventh node (e.g., see Fig. 4).
Claim 8, ‘870 teaches a cascaded converter (e.g., see Fig. 4-6), comprising: four capacitors, comprising a first capacitor (e.g., Cu1), a second capacitor (e.g., Cu2), a third capacitor (e.g., Cd2), and a fourth capacitor (e.g., Cd1) connected in series, wherein the first capacitor and the second capacitor are jointly connected at a first node (e.g., the node connecting Cu1 and Cu2), the second capacitor and the third capacitor are jointly connected at a second node (e.g., the node connecting Cd2 and Cu2), the third capacitor and the fourth capacitor are jointly connected at a third node (e.g., the node connecting Cd1 and Cd2), and the first capacitor is further connected to a first voltage node (e.g., +Vs, see Fig. 4), and the fourth capacitor is further connected to a second voltage node (e.g., GND, see Fig. 4), four switches, comprising a first switch (e.g., the circuit comprising Df2, Du2, Su1), a second switch (e.g., the circuit comprising Du/Dr2), a third switch (e.g., the circuit comprising Dd/ Df1), and a fourth switch (e.g., the circuit comprising Dr1,Dd4, Sd1) connected in series, wherein the first switch and the second switch are jointly connected at a fourth node (e.g., the node connecting Dr2, Du, with Df2m Su1), the second switch and the third switch are jointly connected at the second node, the third switch and the fourth switch are jointly connected at a fifth node (e.g., the node connecting Dr1/Sd1 with Lr1 through Dr1 ), and the first switch is further connected to the first voltage node, and the fourth switch is further connected to the second voltage node (e.g., see Fig. 4), a fifth switch (e.g., Sr2) and a first inductor (e.g., Lr2), jointly connected at a sixth node (e.g., the node connecting Sr2 with Lr2), and the fifth switch further connected to the first node, the first inductor further connected to the fourth node (e.g., Lr2 connecting with Df2/Su1 through Dr2, see Fig. 4), a sixth switch (e.g., Sf1) and a second inductor (e.g., Lf1), jointly connected at a seventh node (e.g., the node connecting Sf1 and Lf1), and the sixth switch (S6) further connected to the third node (N3), the second inductor (L2) further connected to the fifth node (e.g., Lr1 connecting with Dr1/Sd1 through Df1, see Fig. 4), and a diode (e.g., Du3/Dd1), comprising an anode and a cathode, the cathode connected to the sixth node (e.g., the anode of Du3 connecting with Sr2 and Lr2, see Fig. 4), and the anode connected to the seventh node (e.g., the anode of Dd1 connecting with Sf1 and Lf1, see Fig. 4).
Allowable Subject Matter
Claims 2-7, 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
For claim 2, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the first switch is turned on, the second switch is turned off, the fifth switch is turned on, and the seventh switch is turned off so that a first voltage built on the first capacitor stores energy in the first inductor, during a second time period subsequent to the first time period, the first switch is turned off, the second switch is turned on, the fifth switch is turned on, and the seventh switch is turned off so that the first inductor releases energy to the second capacitor to build a second voltage”.
For claim 3, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the first switch is turned off, the second switch is turned on, the fifth switch is turned on, and the seventh switch is turned off so that a second voltage built on the second capacitor stores energy in the first inductor, during a second time period subsequent to the first time period, the first switch is turned on, the second switch is turned off, the fifth switch is turned on, and the seventh switch is turned off so that the first inductor releases energy to the first capacitor to build a first voltage”.
For claim 4, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the third switch is turned on, the fourth switch is turned off, the sixth switch is turned on, and the seventh switch is turned off so that a third voltage built on the third capacitor stores energy in the second inductor, during a second time period subsequent to the first time period, the third switch is turned off, the fourth switch is turned on, the sixth switch is turned on, and the seventh switch is turned off so that the second inductor releases energy to the fourth capacitor to build a fourth voltage”.
For claim 5, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the third switch is turned off, the fourth switch is turned on, the sixth switch is turned on, and the seventh switch is turned off so that a fourth voltage built on the fourth capacitor stores energy in the second inductor, during a second time period subsequent to the first time period, the third switch is turned on, the fourth switch is turned off, the sixth switch is turned on, and the seventh switch is turned off so that the second inductor releases energy to the third capacitor to build a third voltage”.
For claim 6, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the second switch is turned on, the third switch is turned on, the fifth switch is turned on, the sixth switch is turned off, and the seventh switch is turned on so that a second voltage built on the second capacitor stores energy in the first inductor and in the second inductor, during a second time period subsequent to the first time period, the second switch is turned on, the third switch is turned on, the fifth switch is turned off, the sixth switch is turned on, and the seventh switch is turned on so that the first inductor and the second inductor release energy to the third capacitor to build a third voltage”.
For claim 7, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the second switch is turned on, the third switch is turned on, the fifth switch is turned off, the sixth switch is turned on, and the seventh switch is turned on so that a third voltage built on the third capacitor stores energy in the first inductor and in the second inductor, during a second time period subsequent to the first time period, the second switch is turned on, the third switch is turned on, the fifth switch is turned on, the sixth switch is turned off, and the seventh switch is turned on so that the first inductor and the second inductor release energy to the second capacitor to build a second voltage”.
For claim 9, the prior art does not disclose or suggest, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the first switch is turned on, the second switch is turned off, and the fifth switch is turned on so that a first voltage built on the first capacitor stores energy in the first inductor, during a second time period subsequent to the first time period, the first switch is turned off, the second switch is turned on, and the fifth switch is turned on so that the first inductor releases energy to the second capacitor to build a second voltage”.
For claim 10, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the first switch is turned off, the second switch is turned on, and the fifth switch is turned on so that a second voltage built on the second capacitor stores energy in the first inductor, during a second time period subsequent to the first time period, the first switch is turned on, the second switch is turned off, and the fifth switch is turned on so that the first inductor releases energy to the first capacitor to build a first voltage”.
For claim 11, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the third switch is turned on, the fourth switch is turned off, and the sixth switch is turned on so that a third voltage built on the third capacitor stores energy in the second inductor, during a second time period subsequent to the first time period, the third switch is turned off, the fourth switch is turned on, and the sixth switch is turned on so that the second inductor releases energy to the fourth capacitor to build a fourth voltage”.
For claim 12, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the third switch is turned off, the fourth switch is turned on, and the sixth switch is turned on so that a fourth voltage built on the fourth capacitor stores energy in the second inductor, during a second time period subsequent to the first time period, the third switch is turned on, the fourth switch is turned off, and the sixth switch is turned on so that the second inductor releases energy to the third capacitor to build a third voltage”.
For claim 13, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the second switch is turned on, the third switch is turned off, the fifth switch is turned on, and the sixth switch is turned off so that a second voltage built on the second capacitor stores energy in the first inductor, during a second time period subsequent to the first time period, the second switch is turned on, the third switch is turned off, the fifth switch is turned off, and the sixth switch is turned on so that the first inductor releases energy to the third capacitor to build a third voltage”.
For claim 14, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “during a first time period, the second switch is turned off, the third switch is turned on, the fifth switch is turned off, and the sixth switch is turned on so that a third voltage built on the third capacitor stores energy in the second inductor, during a second time period subsequent to the first time period, the second switch is turned off, the third switch is turned on, the fifth switch is turned on, and the sixth switch is turned off so that the second inductor releases energy to the second capacitor to build a second voltage”.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20030214462 A1, US 20040257308 A1, US 20130314957 A1, and US 20080239772 A1all fail to teach or disclose the limitations indicated above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
