DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 05/06/2025 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 3, 6-8, and 10 are objected to because of the following informalities:
Claim 3: Change to “…first groups GW_j, j being an integer ranging from 1 to N,…” (page 22).
Claim 3: Change to “…second groups GADD_i, i being an integer ranging from 1 to N,…” (page 22).
Claim 6: Change to “6. The method according to claim 3, wherein the number NA is an integer that ranges from 2 to 16.” (page 23).
Claim 7: Change to “7. The method according to claim 3, wherein writing the digital data in the second memory location is performed in one of the first groups GW_j, j being an integer ranging from 1 to N, and wherein no write operation was already performed in each of the memory locations of said [[group]] one of the first groups GW_j.” (page 23).
Claim 8: Change from “…the first memory location in the [[a]] third memory location…” (page 23).
Claim 10: Change both instances of “…in the case where…” to “…when…” (page 24).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the digital data" in page 22. It is unclear as to which digital data is being referred to:
Claim 1: “1. A method for controlling a one-time programmable memory that includes memory locations that are each identified by an address, each memory location configured to store a digital data having a given number of bits,…”
Claim 1: “…in response to a failure of a read operation of digital data in a first memory location of the first memory zone:…”
Because Claims 2-10 depend upon Claim 1, Claims 2-10 are additionally rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 3 recites the limitation "the first group GW_k" in page 22. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the second group GADD_k" in page 22. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the first groups GW_j" in page 23. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites various instances of the limitation "the digital data" in page 23. It is unclear as to which digital data is being referred to, per Claim 1, as mentioned above.
In Claim 11, the variable “k” is undefined.
Claim 11 recites the limitation "the k-th first group" in page 25. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the address" in page 25. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the k-th second group" in page 25. There is insufficient antecedent basis for this limitation in the claim.
Because Claims 12 and 13 depend upon Claim 11, Claims 12 and 13 are additionally rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bosch et al. (U.S. Patent No. US 7,958,390 B2), hereinafter “Bosch.”
With regards to Claim 1, Bosch teaches:
a method for controlling a one-time programmable memory (Fig. 1 and col. 2, lines 33-39.) that includes memory locations (Fig. 1; col. 2, lines 56-64; Fig. 2; col. 3, lines 21-41; and col. 3, lines 53-61.) that are each identified by an address (Fig. 1; Fig. 2; col. 3, lines 53-61; Fig. 3; and col. 4, lines 35-63.), each memory location configured to store a digital data having a given number of bits (Fig. 1; Fig. 2; and col. 3, lines 21-41.), wherein the memory locations are arranged in a first memory zone (Fig. 1; Fig. 2; and col. 3, lines 21-41; regarding, e.g., normal data storage area 126.), a second memory zone (Fig. 1; Fig. 2; and col. 3, lines 21-41; regarding, e.g., repair area 124.), and a third memory zone (Fig. 1; Fig. 2; and col. 3, lines 21-41; regarding, e.g., patch table area 122.), the method comprising:
in response to a failure of a read operation of digital data in a first memory location of the first memory zone (Fig. 1; Fig. 3; and col. 5, lines 30-41.):
writing the digital data in a second memory location of the second memory zone (Figs. 2-4 and col. 5, lines 52-67.); and
writing, in a third memory location of the third memory zone, the address of the first memory location (Figs. 1-4; col. 5, lines 52-67; and col. 4, lines 6-19; regarding, e.g., a target address that is stored in the patch table area 122.) and an identifier of the second memory location (Figs. 2-4 and col. 5, lines 52-67; regarding, e.g., a repair address field designation [see, e.g., the structure in Fig. 2 under “Patch Table”] including a repair address.).
With regards to Claim 2, Bosch teaches the method of Claim 1 as referenced above. Bosch further teaches:
wherein the identifier of the second memory location is equal to the address of the second memory location (Figs. 2-4 and col. 5, lines 52-67.).
With regards to Claim 3, Bosch teaches the method of Claim 1 as referenced above. Bosch further teaches:
wherein the memory locations of the second memory zone are arranged into first groups GW_j, j ranging from 1 to N, comprising each NA consecutive memory locations of the second memory zone (Fig. 1; col. 2, lines 56-64; Fig. 2; and col. 3, lines 21-41.), wherein the memory locations of the third memory zone are arranged into second groups GADD_i, i ranging from 1 to N, comprising each NA consecutive memory locations of the third memory zone (Fig. 1; col. 2, lines 56-64; Fig. 2; and col. 3, lines 21-41.), wherein the second memory location is located in the first group GW_k, k being an integer ranging from 1 to N, (Fig. 1; Fig. 2; and col. 3, lines 21-41.) and wherein the third memory location is located in the second group GADD_k (Fig. 1; Fig. 2; and col. 3, lines 21-41.).
With regards to Claim 6, Bosch teaches the method of Claim 3 as referenced above. Bosch further teaches:
wherein the number NA ranges from 2 to 16 (Fig. 1; Fig. 2; and col. 3, lines 21-41. As interpreted by the Examiner, NA corresponds to a page, and the NA consecutive memory locations correspond to the groups of 2 pages per row.).
With regards to Claim 7, Bosch teaches the method of Claim 3 as referenced above. Bosch further teaches:
wherein writing the digital data in the second memory location is performed in one of the first groups GW_j, j ranging from 1 to N (Figs. 1-4; col. 3, lines 21-41; and col. 5, lines 52-67.), and wherein no write operation was already performed in each of the memory locations of said group (Figs. 1-4; col. 5, lines 52-67; and col. 2, lines 33-39. As interpreted by the Examiner, if data is capable of being written to part of a memory array that comprises OTP memory, then the part of the memory cannot have been previously written to.).
With regards to Claim 8, Bosch teaches the method of Claim 1 as referenced above. Bosch further teaches:
in response to failure to write the digital data in the second memory location, writing the digital data in a next second memory location of the second memory zone (Fig. 4 and col. 6, lines 2-18.), and comprising, in response to failure to write the address of the first memory location in the third memory location, writing the address of the first memory location in the a third memory location of the third memory zone (Fig. 4 and col. 6, lines 2-18.).
With regards to Claim 9, Bosch teaches the method of Claim 1 as referenced above. Bosch further teaches:
wherein starting-up the one-time programmable memory (Fig. 1 and col. 4, lines 44-47.) comprises:
reading the second memory zone (Fig. 1; col. 4, lines 44-47; and col. 4, lines 1-19.); and
when the second memory zone is not empty: copying in a further memory, for each operation of writing a digital data in a first memory location of the first memory zone having failed, the address of the first memory location and the address of the third memory location (Fig. 1 and col. 4, lines 1-19; regarding, e.g., volatile memory [a further memory].).
With regards to Claim 10, Bosch teaches the method of Claim 9 as referenced above. Bosch further teaches:
wherein a read operation in the first memory zone of the one-time programmable memory comprises:
providing an address (Fig. 1 and col. 4, lines 1-19.);
searching the provided address in the further memory (Fig. 1 and col. 4, lines 1-19.);
in the case where the provided address is not present in the further memory, reading the digital data stored in the memory location of the first memory zone at the provided address (Fig. 1 and col. 4, lines 1-19.); and
in the case where the provided address is present in the further memory, reading the digital data stored in the third memory location of the second memory zone (Fig. 1 and col. 4, lines 1-19.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Bosch, and further in view of Dodson et al. (U.S. Patent No. US 10,338,999 B2), hereinafter “Dodson.”
With regards to Claim 4, Bosch teaches the method of Claim 3 as referenced above. Bosch does not explicitly teach:
wherein the identifier of the second memory location is equal to a rank of the second memory location in the first group GW_k in accordance with the method of Claim 3.
However, Dodson teaches:
wherein the identifier of the second memory location is equal to a rank of the second memory location in the first group GW_k (Fig. 2 and col. 3, lines 46-60.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Bosch with the storing of information in a table associated with memory such as a rank as taught by Dodson because a simple substitution and/or addition of one known element (a number of fields including information such as address information – Bosch: Fig. 2 and Bosch: col. 3, lines 53-65) for/with another (rank information) can be performed to obtain predictable results (providing known types of data associated with identifying regions of memory for reliability processing).
With regards to Claim 11, Bosch teaches:
a method for controlling a one-time programmable memory (Fig. 1 and col. 2, lines 33-39.) that includes a first memory zone of memory locations (Fig. 1; Fig. 2; and col. 3, lines 21-41; regarding, e.g., normal data storage area 126.), a second memory zone of memory locations (Fig. 1; Fig. 2; and col. 3, lines 21-41; regarding, e.g., repair area 124.), and a third memory zone of memory locations (Fig. 1; Fig. 2; and col. 3, lines 21-41; regarding, e.g., patch table area 122.), the method comprising:
arranging the second memory zone to include a plurality of first groups, each first group having a same number of consecutive memory locations (Fig. 1; Fig. 2; and col. 3, lines 21-41. As interpreted by the Examiner, ‘a same number’ corresponds to a page, and the consecutive memory locations correspond to the groups of 2 pages per row.);
arranging the third memory zone to include a plurality of second groups, each second group having said same number of consecutive memory locations (Fig. 1; Fig. 2; and col. 3, lines 21-41. As interpreted by the Examiner, ‘a same number’ corresponds to a page, and the consecutive memory locations correspond to the groups of 2 pages per row.); and
in response to a failure of a read operation of digital data in a first memory location of the first memory zone (Fig. 1; Fig. 3; and col. 5, lines 30-41.):
writing the digital data in a second memory location of the second memory zone, wherein the second memory location is located in the k-th first group of the plurality of first groups (Figs. 2-4 and col. 5, lines 52-67.); and
writing, in a third memory location of the third memory zone, the address of the first memory location (Figs. 1-4; col. 5, lines 52-67; and col. 4, lines 6-19; regarding, e.g., a target address that is stored in the patch table area 122.) and an identifier of the second memory location, wherein the third memory location is located in the k-th second group of the plurality of second groups (Figs. 2-4 and col. 5, lines 52-67; regarding, e.g., a repair address field designation [see, e.g., the structure in Fig. 2 under “Patch Table”] including a repair address.).
Bosch does not explicitly teach:
wherein the identifier of the second memory location is equal to a rank of the second memory location in the k-th first group.
However, Dodson teaches:
wherein the identifier of the second memory location is equal to a rank of the second memory location in the k-th first group (Fig. 2 and col. 3, lines 46-60.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Bosch with the storing of information in a table associated with memory such as a rank as taught by Dodson because a simple substitution and/or addition of one known element (a number of fields including information such as address information – Bosch: Fig. 2 and Bosch: col. 3, lines 53-65) for/with another (rank information) can be performed to obtain predictable results (providing known types of data associated with identifying regions of memory for reliability processing).
With regards to Claim 13, Bosch in view of Dodson teaches the method of Claim 11 as referenced above. Bosch in view of Dodson further teaches:
wherein no write operation was already performed in each of the memory locations of the first group (Bosch: Figs. 1-4; Bosch: col. 5, lines 52-67; and Bosch: col. 2, lines 33-39. As interpreted by the Examiner, if data is capable of being written to part of a memory array that comprises OTP memory, then the part of the memory cannot have been previously written to.).
Allowable Subject Matter
Claims 5 and 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Glancy et al. (U.S. Patent No. US 10,671,497 B2); teaching a memory system for storing data, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
Wasserstrom (U.S. Patent No. US 11,392,450 B1); teaching a one-time programmable (OTP) memory programmed over a number of programming sessions in which each programming session writes a different portion of the memory. To provide the OTP memory with data integrity check capability, the OTP memory stores multiple error detection code entries. With each programming session, a new error detection code is stored in a previously unused entry. When the OTP memory is read, the error detection code corresponding to the latest programming session is used to verify the content of the OTP memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH KUDIRKA whose telephone number is (571)270-7126. The examiner can normally be reached M-F 7:30am - 5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH R KUDIRKA/Primary Patent Examiner, Art Unit 2114
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