Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. This communication is responsive to Application No. 19/200,230 filed on May 06, 2025. Claims 1-20 are subject to examination.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
4. The IDS submitted on 05/06/25 has been entered and considered by the Examiner.
Claim Objections/Suggestions
5. Following claims are objected to because of the following informalities:
in claims 1, 4, 12, 15 and 17 the term “using” should be replaced with “utilizing”;
in claim 12 “the DFE circuit” (line 10) should be replaced with “the M-tap DFE circuit”; and
in claim 15 “the N multiplexer circuits” (the last line) should be replaced with “the N chain multiplexer circuits”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites “feed forward equalizer (FFE) circuit configured to equalize a digital signal comprising a plurality of symbols according to a pulse amplitude modulation” (lines 2-3). It is not clear how this limitation should be read (e.g., feed forward equalizer (FFE) circuit configured to equalize a digital signal, comprising a plurality of symbols, according to a pulse amplitude modulation?). Hence, renders claim 1 and its dependent claims indefinite. Similar rejection applies to claim 12. In addition, claim 1 recites the limitation “the value” (line 23). There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites “candidate values of the present symbol” (line 7). It is not clear whether said "candidate values of the present symbol" is different from or the same as recited “candidate values of the present symbol” in line 22 of claim 1.
Claim 9 recites the limitation “the received slicing value” (line 5). There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites “a parallel stage comprising N circuits configured to” (line 16). It is not clear whether said “configured to” is referring to said “parallel stage” or “N circuits”. Similarly, the limitation in line 22 of claim 15 “a chain path comprising N chain multiplexer circuits configured to” (line 22). It is not clear whether said “configured to” is referring to said “chain path” or “N chain multiplexer circuits”. Hence, renders claim 15 and its dependent claims indefinite.
Reason for Allowance
8. Kiran (US 2017/0180002 A1) teaches in Figure 3 a first feed forward equalizer (FFE) circuit configured to equalize a digital signal comprising a plurality of symbols according to a pulse amplitude modulation (PAM) method and to output a first equalization signal (311); a second FFE circuit configured to equalize the digital signal and to output a second equalization signal (312); and a decision feedback equalization (DFE) circuit (315); Kiran further teaches in Figure 4 said DFE circuit comprising multiplexers (“MUX”), slicers (435), delayers (455) and adders (425). Tachibana (US 11,888,496 B2) teaches in Figure 4 a first FFE (51), a second FFE (61) and a DFE (62) and in Figure 10 the DFE including adders (“+”) and multiplexers (623). Yang (US 12,413,457 B1) teaches in Figure 8 FFEs (FFE) and a DFEs (DFE). However, the prior art of record when implemented, would not produce said circuit/receiver as claimed in claims 1, 12 and 15.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to SHAWKAT M. ALI whose telephone number is (571) 270-1639. The Examiner can normally be reached on Monday-Thursday 8:30AM-3:30PM ET.
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If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, SAM K. AHN can be reached on (571) 272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWKAT M ALI/
Primary Examiner, Art Unit 2633
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