0Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application filed on 05/06/2025.
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 05/06/2025, 12/03/2025 and 01/30/2026 has been considered (see form-1449, MPEP 609).
Drawings
The drawings filed on 05/06/2025 are accepted.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The Claim recites the language of “A computing system comprising: a storage medium; and
a processor configured to:
identify first data of a first data structure;
identify a first portion of the first data and a second portion of the first data;
store the first portion of the first data as a second data structure in the
storage medium, and the second portion of the first data as a third data structure in the storage medium;
identify a request for the first data;
based on the request, retrieve from the storage medium the second data
structure including the first portion of the first data;
identify a value associated with the second portion;
generate second data based on the first portion and the value; and
perform a task based on the second data.”
Claim 1 recites the limitation of “identify first data of a first data structure;
identify a first portion of the first data and a second portion of the first data”, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is nothing in the claim element precludes the step from practically being performed in the mind. For example, “identify” in the context of this claim encompasses the user manually identifying data/information. Similarly, the limitation of store the first portion of the first data as a second data structure in the
storage medium, and the second portion of the first data as a third data structure in the storage medium, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. For example, but for the “store” in the context of this claim encompasses the user manually saving information. Similarly, the limitation of identify a request for the first data; based on the request, retrieve from the storage medium the second data structure including the first portion of the first data; identify a value associated with the second portion, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. For example, “identify” in the context of this claim encompasses the user manually identify information. Also Similarly, the limitation of generate second data based on the first portion and the value; and perform a task based on the second data, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. For example, “generate and perform” in the context of this claim encompasses the user manually interact with the information. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Human Activity” and “Gathering Information” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim only recites one additional element – using storage medium and a processor to perform the identify, store, generate and perform steps. The processor and storage medium in those steps is recited at a high-level of generality (i.e., as a generic processor performing a generic computer function of collect information) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of using a processor the perform the identify, store, generate and perform steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim is not patent eligible.
Claim 2 is dependent on independent claim 1 and includes all the limitations of claim 1. Claim 2 recites “identify the first portion of the first data and the second portion of the first data includes the processor being configured to fragment the first data at a truncation point”. The claim language provides only further identify information which is directed towards the abstract idea and does not amount to significantly more. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea.
Claim 3 is dependent on independent claim 1 and includes all the limitations of claim 1. Claim 3 recites “the first portion includes a first set of bits of the first data, and the second portion includes a second set of bits of the first data, wherein the first set of bits have a higher positional value than the second set of bits”. The claim language provides only further data portion which is directed towards the abstract idea and does not amount to significantly more. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea.
Claim 4 is dependent on independent claim 1 and includes all the limitations of claim 1. Claim 4 recites “identify the value associated with the second portion includes the processor being configured to identify an attribute related to the first data”. The claim language provides only further identify the value which is directed towards the abstract idea and does not amount to significantly more. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea.
Claims 5-7 is dependent on independent claim 4 and includes all the limitations of claims 4 and 1. Claims 5-7 recites “identify the value associated with the second portion includes the processor being configured to: identify the attribute related to the first data as being of a first type; and based on identifying the first type of the attribute, retrieve the third data structure storing the second portion of the first data from the storage medium, wherein the value is based on the second portion of the first data”, “identify the value associated with the second portion includes the processor being configured to: identify the attribute related to the first data as being of a first type; and based on identifying the first type of the attribute, set the value to a preset value” and “identify the value associated with the second portion includes the processor being configured to: identify third data; perform a second task based on third data; and identify the value based on performing the second task. The claim language provides only further identify the value which is directed towards the abstract idea and does not amount to significantly more. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea.
Claim 8 is dependent on independent claim 1 and includes all the limitations of claim 1. Claim 8 recites “the value is different than a second value of the first data in the second portion”. The claim language provides only further the value which is directed towards the abstract idea and does not amount to significantly more. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea.
Claim 9 is dependent on independent claim 1 and includes all the limitations of claim 1. Claim 9 recites “identify third data stored in a fourth data structure; identify a third portion of the third data and a fourth portion of the third data; generate a first block of data including the first portion and the third portion; store the first block of data as the second data structure; generate a second block of data including the second portion and the fourth portion; and store the second block of data as the third data structure”. The claim language provides only further identify data which is directed towards the abstract idea and does not amount to significantly more. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea.
Claim 10 is dependent on independent claim 9 and includes all the limitations of claims 9 and 1. Claim 10 recites “a size of the first block of data and a size of the second block of data is based on an amount of data transferred by the storage medium in one transaction”. The claim language provides only further size of data block which is directed towards the abstract idea and does not amount to significantly more. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea.
Regarding claims 11-20: are essentially the same as claims 1-10 except that they set forth the claimed invention as a method rather than a system respectively and correspondingly, therefore are rejected under the same reasons set forth in rejections of claims 1-10.
Accordingly, the claims 1-20 are not patent eligible.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmed et al. (US PGPUB 2014/0331032, hereinafter Ahmed), in view of Wu et al. (US PGPUB 2023/0153240, hereinafter Wu).
As per as claim 1, Ahmed discloses:
A computing system comprising:
a storage medium (Ahmed, e.g., [0007], [0102], “storage medium”); and
a processor (Ahmed, e.g., [0007], “a processor”) configured to:
identify first data of a first data structure (Ahmed, e.g., [0006-007], (first functional united block, data in a first format...” and [0091], “...data in a first format may be provided by a first functional unit block (FUB)...”);
identify a first portion of the first data and a second portion of the first data; store the first portion of the first data as a second data structure in the
storage medium, and the second portion of the first data as a third data structure in the storage medium (Ahmed, e.g., [0038-0040], “...these instructions 204 may be used in video and audio processing where memory holds information in an array of structures (AOS) format but where a SIMD machine or execution unit desires data in a structures-of-arrays (SOA) format. As such, during the load or store instruction the re-formatting or transposition of portions of the data 202 is desirable...” and see [0089-0093], “...access to the data or store bus that includes the data paths... portions of technique 600 may be used on or produce the data structures such as those of FIGS. 2a and/or 2b...”);
identify a request for the first data (Ahmed, e.g., [0096-0097], “...once the data has been stored in the storage buffer, the data may be transposed to a second format...”);
based on the request, retrieve from the storage medium the second data
structure including the first portion of the first data (Ahmed, e.g., [0038-0040], “...load or store instruction the re-formatting or transposition of portions of the data...” and [0096-0097], “...the data in the second format may be transmitted to the second functional unit block, as described above. In various embodiments, transmitting may include arbitrating access to the second functional unit block between two pieces of data. The first piece of data being the data in the second format transmitted via the transposing data path and the second piece of data being a second set of data transmitted via a non-transposing data path...” ;
identify a value associated with the second portion (Ahmed, e.g., [0041-0045], “value of data” and [0096-0097], “...second piece of data being a second set of data transmitted via a non-transposing data path...”);
generate second data based on the first portion and the value (Ahmed, e.g., [0041-0045], [0096-0097], “...transmitting may include writing portions of the data in the second format to the second functional unit blocks via a plurality of write sub-instructions...”); and
perform a task based on the second data (Ahmed, e.g., [0096-0097], “...writing portions of the data in the second format to the second functional unit blocks via a plurality of write sub-instructions... performed by the apparatuses or systems...”) (read/writing = perform tasks).
To make records clearer regarding to the language of “store the first portion of the first data as a second data structure in the storage medium, and the second portion of the first data as a third data structure in the storage medium” (although as stated above Ahmed functional disclose the feature of “store the first portion of the first data as a second data structure in the storage medium, and the second portion of the first data as a third data structure in the storage medium”
However Wu, in an analogous art, discloses “store the first portion of the first data as a second data structure in the storage medium, and the second portion of the first data as a third data structure in the storage medium” (Wu, e.g., [0040-0046], “...extract (e.g., LOAD) the extracted first data structure 410 (that was originally in the first data format) from the interleaved data structure 416, process 400 may start loading by subtracting two bytes from a current address 418 in the data storage 414 and read data directly in the form of Float32. Thus, process 400 may load data in a first data format (e.g., BFloat16) from the data storage 414 with a second data format (e.g., Float32 instructions) and obtain the second data format (e.g., Float32) value to avoid penalties associated with first data format instructions (e.g., first data format to second data format conversions)... stored in a machine- or computer-readable storage medium... identifies a plurality of data that are in a first data format (e.g., BF16) and are to be stored in a second data format ...”). Thus, it would have been obvious to one of ordinary skill in the art BEFORE the effective filling date of the claimed invention to combine the teaching of Wu and Ahmed to store the interleaved data in a data storage in order to reduces or completely avoids a penalty of additional conversions between different data formats (Wu, e.g., [0017-0019]).
As per as claim 2, the combination of Wu and Ahmed discloses:
The computing system of claim 1, wherein the processor being configured to
identify the first portion of the first data and the second portion of the first data includes the processor being configured to fragment the first data at a truncation point (Wu, e.g., [0016], “... first and second data 302, 304 may be in a first data format (e.g., BFloat16 or brain floating-point) that is a truncated (e.g., 16-bit) version of a second data format (e.g., 32-bit, Float32 floating-point)...” and [0040-0046], “...extract (e.g., LOAD) the extracted first data structure 410 (that was originally in the first data format) from the interleaved data structure 416, process 400 may start loading by subtracting two bytes from a current address 418 in the data storage 414 and read data directly in the form of Float32. Thus, process 400 may load data in a first data format (e.g., BFloat16) from the data storage 414 with a second data format (e.g., Float32 instructions) and obtain the second data format (e.g., Float32) value to avoid penalties associated with first data format instructions (e.g., first data format to second data format conversions).
As per as claim 3, the combination of Wu and Ahmed discloses:
The computing system of claim 1, wherein the first portion includes a first set
of bits of the first data, and the second portion includes a second set of bits of the first data, wherein the first set of bits have a higher positional value than the second set of bits (Wu, e.g., [0021-0028], “...the first data 302 may comprise bits 302a-302h. Second data 304 may comprise bits 304a-304h. While a certain number of bits 302a-302h and 304a, 304h .... first data 302 that alternate with bits 304a, 304h of the second data 304 in a continuous and adjacent fashion. Thus, a size of the first data 302 may be approximately half a size of the interleaved data 308, and a size of the second data 304 may be approximately half a size of the interleaved data...”).
As per as claim 4, the combination of Wu and Ahmed discloses:
The computing system of claim 1, wherein the processor being configured to
identify the value associated with the second portion includes the processor being configured to identify an attribute related to the first data (Wu, e.g., [0021-0028]).
As per as claim 5, the combination of Wu and Ahmed discloses:
The computing system of claim 4, wherein the processor being configured to
identify the value associated with the second portion includes the processor being configured to:
identify the attribute related to the first data as being of a first type; and
based on identifying the first type of the attribute, retrieve the third data structure
storing the second portion of the first data from the storage medium, wherein the value is based on the second portion of the first data (Wu, e.g., [0033], [0054-0056], “...storage type into a compiler extension or library... a BFloat16 storage type in the first library 574a to N-library 574n...”).
As per as claim 6, the combination of Wu and Ahmed discloses:
The computing system of claim 4, wherein the processor being configured to
identify the value associated with the second portion includes the processor being configured to:
identify the attribute related to the first data as being of a first type (Ahmed, e.g., [0036-0039], (set and subset of data); and
based on identifying the first type of the attribute, set the value to a preset value (Ahmed, e.g., [0036-0039], various sizes or number of bits).
As per as claim 7, the combination of Wu and Ahmed discloses:
The computing system of claim 4, wherein the processor being configured to
identify the value associated with the second portion includes the processor being configured to:
identify third data (Ahmed, e.g., [0036-0039], (set and subset of data)) and see (Wu, e.g., [0040-46]);
perform a second task based on third data (Ahmed, e.g., [0096-0097], “...writing portions of the data in the second format to the second functional unit blocks via a plurality of write sub-instructions... performed by the apparatuses or systems...”) and (Wu, e.g., [0040-0046]); and
identify the value based on performing the second task (Ahmed, e.g., [0096-0097], “...writing portions of the data in the second format to the second functional unit blocks via a plurality of write sub-instructions... performed by the apparatuses or systems...”) and (Wu, e.g., [0040-0046]).
As per as claim 8, the combination of Wu and Ahmed discloses:
The computing system of claim 1, wherein the value is different than a
second value of the first data in the second portion (Wu, e.g., [0029-0030], [0039-0043], “... a first data structure 402 and a second data structure 404 may be in a first data format (e.g., BFloat 16). Process 400 may interleave data 406 to interleave the first data structure 402 and the second data structure 404 to generate an interleaved data structure 416 that is stored in a data storage 414...”).
As per as claim 9, the combination of Wu and Ahmed discloses:
The computing system of claim 1, wherein the processor is configured to:
identify third data stored in a fourth data structure (Wu, e.g., [0021-0028], “...the first data 302 may comprise bits 302a-302h. Second data 304 may comprise bits 304a-304h. While a certain number of bits 302a-302h and 304a, 304h .... first data 302 that alternate with bits 304a, 304h of the second data 304 in a continuous and adjacent fashion. Thus, a size of the first data 302 may be approximately half a size of the interleaved data 308, and a size of the second data 304 may be approximately half a size of the interleaved data...”) and (Ahmed, e.g., [0038-0043], (store different portions) ;
identify a third portion of the third data and a fourth portion of the third data (Ahmed, e.g., [0049-0053], “... load sub-portions 324 of the accessed data into a buffer or temporary registers 322; perform the transposition via an existing portion of an execution unit (e.g., a shuffle unit common in most floating-point units, etc.) with data read from the buffer/temporary registers 322, and then write the transposed data to the destination architectural registers 304...”);
generate a first block of data including the first portion and the third portion (Ahmed, e.g., [0037-0043]);
store the first block of data as the second data structure (Ahmed, e.g., [0037-0043]);
generate a second block of data including the second portion and the fourth portion (Ahmed, e.g., [0037-0043] and [0091-0093], “...storing may include generating, by the first functional unit block, a series of sub-instructions and executing each sub-instruction, as described above. In such an embodiment, each sub-instruction may be associated with a register of the second functional unit block and a portion of the data, and each sub-instruction when executed may cause the first functional unit block to copy the respective portion of the data to the storage buffer...”); and
store the second block of data as the third data structure (Ahmed, e.g., [0037-0043], “... load or store instruction the re-formatting or transposition of portions of the data...” and further see [0091-0093]).
As per as claim 10, the combination of Wu and Ahmed discloses:
The computing system of claim 9, wherein a size of the first block of data
and a size of the second block of data is based on an amount of data transferred by the storage medium in one transaction (Wu, e.g., [0021-0028], “...the first data 302 may comprise bits 302a-302h. Second data 304 may comprise bits 304a-304h. While a certain number of bits 302a-302h and 304a, 304h .... first data 302 that alternate with bits 304a, 304h of the second data 304 in a continuous and adjacent fashion. Thus, a size of the first data 302 may be approximately half a size of the interleaved data 308, and a size of the second data 304 may be approximately half a size of the interleaved data...”).
Claims 11-20 are essentially the same as claims 1-10 except that they set forth the claimed invention a method rather a system, respectively and correspondingly, therefore is rejected under the same reasons set forth in rejections of claims 1-10.
Additional Art Considered
The prior art made of record and not relied upon is considered pertinent to the Applicants’ disclosure.
The following patents and papers are cited to further show the state of the art at the time of Applicants’ invention with respect to data truncation which to identify first data of a first data structure; identify a first portion of the first data and a second portion of the first data; store the first portion of the first data as a second data structure in the storage medium, and the second portion of the first data as a third data structure in the storage medium; identify a request for the first data; based on the request, retrieve from the storage medium the second data structure including the first portion of the first data.
a. Bharambe et al. (US PGPUB 2022/0365750, hereinafter Bharambe); “Datatype Conversion Technique” disclose “ perform number generation and matrix multiply and accumulate (MMA) operations which cause one or more thirty-two bit floating point numbers to be truncated to generate one or more rounded numbers based, at least in part, on one or more rounding attributes”.
Bharambe also teaches floating point numbers to be truncated [0063-0064], rounding attributes are specified in a set of instructions to perform a matrix operation [0090].
Gharambe further teaches matrix fragments [0182], and perform different types of processing [0294].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A PHAM whose telephone number is (571)270-3173. The examiner can normally be reached M-F 7:45 AM - 6:30 PM.
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/TUAN A PHAM/Primary Examiner, Art Unit 2163