DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-10 and 15-17 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Gorrie et al. (US 11,294,824) in view of Jean et al. (US9,977,623).
With respect to claim 1, Gorrie et al. teaches a memory device (see Fig. 1 and column 6, lines 36-39; non-volatile memory 110); and
a memory sub-system controller, coupled with the memory device (see Fig. 1 and column 7, lines 1-4; controller coupled to NVM 110), configured to perform operations comprising:
receiving a write command that indicates to write data to the memory device (see column 13, lines 66-67 and column 14, lines 1-9; controller receives from a host device a write command for the data including one or more requested logical addresses), wherein a size of the data is smaller than a translation unit size (see column 9, lines 50-67 and column 10, lines 1-7; data lengths 318 and 320 is smaller than the write length of the memory);
generating, based on the write command being associated with the sequential write stream, a read command that indicates to read other data associated with the sequential write stream from the memory device (see column 14, lines 10-33; controller generates/performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read));
executing a read operation associated with the read command to read the other data from the memory device (see column 14, lines 10-33; controller performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read));
merging the data and the other data to form merged data (see column 15, lines 60-65; controller merges the transferred data for the head portion in the buffer allocated to the write command for the host data, and as represented by block 516, the controller merges the transferred data for the tail portion with the host data in the buffer), wherein a size of the merged data is equal to the translation unit size (see column 16, lines 4-9; the controller may write all 4 KB of aligned data (e.g. the head portion, the host data, and the tail portion) to the NVM 110 to complete operation of RMW); and
executing a program operation to write the merged data to the memory device (see column 15, lines 66-67 and column 16, lines 1-9; the controller may write the merged data (e.g. the buffer 128) to the memory).
Gorrie et al. does not teach determining that the write command is associated with a sequential write stream.
However, Jean et al. teaches determining that the first command, the second command, and the third command correspond to a sequential command stream (see Fig. 10, and column 13, lines 17-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Gorrie et al. to include the above mentioned to improve the performance of the data storage device (see Jean, column 3, lines 8-25).
With respect to claim 2, Gorrie et al. does not explicitly teach wherein the memory sub-system controller is further configured to perform operations comprising identifying the other data associated with the sequential write stream using a read look-ahead operation.
However, Jean et al. teaches in the case of a sequential read stream, read look ahead (RLA) operations may be performed to prefetch data corresponding to a “next,” LBA or range of LBAs that is sequential with respect to a “current” LBA (see column 3, lines 20-25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Gorrie et al. to include the above mentioned to increase read throughput at the data storage device (see Jean, column 24-35).
With respect to claim 3, Gorrie et al. does not explicitly teach wherein determining that the write command is associated with the sequential write stream comprises determining that the write command is associated with the sequential write stream based on a logical block address of the write command, a number of logical block addresses in the write command, and a queue depth.
However, Jean et al. teaches after receiving the first command, receive a second command and a third command from the access device, at 1004. The second command may be associated with a second LBA that precedes the first LBA and the third command may be associated with a third LBA that succeeds the first LBA (see column 12, lines 66-67 and column 13, lines 1-4); and wherein command size, queue depth, etc. may also be adaptively varied to tune the stream detection algorithm (see column 9, lines 22-24)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Gorrie et al. to include the above mentioned to improve the performance of the data storage device (see Jean, column 3, lines 8-25).
With respect to claim 8, Gorrie et al. teaches receiving a write command that indicates to write data to a memory device (see column 13, lines 66-67 and column 14, lines 1-9; controller receives from a host device a write command for the data including one or more requested logical addresses), wherein a size of the data is smaller than a translation unit size (see column 9, lines 50-67 and column 10, lines 1-7; data lengths 318 and 320 is smaller than the write length of the memory);
generating, based on the write command being associated with the sequential write stream, a read command that indicates to read other data associated with the sequential write stream from the memory device (see column 14, lines 10-33; controller generates/performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read));
executing a read operation associated with the read command to read the other data from the memory device (see column 14, lines 10-33; controller performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read));
merging the data and the other data to form merged data (see column 15, lines 60-65; controller merges the transferred data for the head portion in the buffer allocated to the write command for the host data, and as represented by block 516, the controller merges the transferred data for the tail portion with the host data in the buffer), wherein a size of the merged data is equal to the translation unit size (see column 16, lines 4-9; the controller may write all 4 KB of aligned data (e.g. the head portion, the host data, and the tail portion) to the NVM 110 to complete operation of RMW); and
executing a program operation to write the merged data to the memory device (see column 15, lines 66-67 and column 16, lines 1-9; the controller may write the merged data (e.g. the buffer 128) to the memory).
Gorrie et al. does not teach determining that the write command is associated with a sequential write stream.
However, Jean et al. teaches determining that the first command, the second command, and the third command correspond to a sequential command stream (see Fig. 10, and column 13, lines 17-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gorrie et al. to include the above mentioned to improve the performance of the data storage device (see Jean, column 3, lines 8-25).
With respect to claim 9, Gorrie et al. does not teach identifying the other data associated with the sequential write stream using a read look-ahead operation.
However, Jean et al. teaches in the case of a sequential read stream, read look ahead (RLA) operations may be performed to prefetch data corresponding to a “next,” LBA or range of LBAs that is sequential with respect to a “current” LBA (see column 3, lines 20-25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gorrie et al. to include the above mentioned to increase read throughput at the data storage device (see Jean, column 24-35).
With respect to claim 10, Gorrie et al. does not teach wherein determining that the write command is associated with the sequential write stream comprises determining that the write command is associated with the sequential write stream based on a logical block address of the write command, a number of logical block addresses in the write command, and a queue depth.
However, Jean et al. teaches after receiving the first command, receive a second command and a third command from the access device, at 1004. The second command may be associated with a second LBA that precedes the first LBA and the third command may be associated with a third LBA that succeeds the first LBA (see column 12, lines 66-67 and column 13, lines 1-4); and wherein command size, queue depth, etc. may also be adaptively varied to tune the stream detection algorithm (see column 9, lines 22-24)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gorrie et al. to include the above mentioned to improve the performance of the data storage device (see Jean, column 3, lines 8-25).
With respect to claim 15, Gorrie et al. teaches receiving a write command that indicates to write data to a memory device (see column 13, lines 66-67 and column 14, lines 1-9; controller receives from a host device a write command for the data including one or more requested logical addresses), wherein a size of the data is smaller than a translation unit size (see column 9, lines 50-67 and column 10, lines 1-7; data lengths 318 and 320 is smaller than the write length of the memory);
generating, based on the write command being associated with the sequential write stream, a read command that indicates to read other data associated with the sequential write stream from the memory device (see column 14, lines 10-33; controller generates/performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read));
executing a read operation associated with the read command to read the other data from the memory device (see column 14, lines 10-33; controller performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read));
merging the data and the other data to form merged data (see column 15, lines 60-65; controller merges the transferred data for the head portion in the buffer allocated to the write command for the host data, and as represented by block 516, the controller merges the transferred data for the tail portion with the host data in the buffer), wherein a size of the merged data is equal to the translation unit size (see column 16, lines 4-9; the controller may write all 4 KB of aligned data (e.g. the head portion, the host data, and the tail portion) to the NVM 110 to complete operation of RMW); and
executing a program operation to write the merged data to the memory device (see column 15, lines 66-67 and column 16, lines 1-9; the controller may write the merged data (e.g. the buffer 128) to the memory).
Gorrie et al. does not teach determining that the write command is associated with a sequential write stream.
However, Jean et al. teaches determining that the first command, the second command, and the third command correspond to a sequential command stream (see Fig. 10, and column 13, lines 17-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gorrie et al. to include the above mentioned to improve the performance of the data storage device (see Jean, column 3, lines 8-25).
With respect to claim 16, Gorrie et al. does not teach wherein the instructions, when executed by the processing device, further cause the processing device to perform operations comprising identifying the other data associated with the sequential write stream using a read look-ahead operation.
However, Jean et al. teaches in the case of a sequential read stream, read look ahead (RLA) operations may be performed to prefetch data corresponding to a “next,” LBA or range of LBAs that is sequential with respect to a “current” LBA (see column 3, lines 20-25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gorrie et al. to include the above mentioned to increase read throughput at the data storage device (see Jean, column 24-35).
With respect to claim 17, Gorrie et al. does not teach teaches wherein determining that the write command is associated with the sequential write stream comprises determining that the write command is associated with the sequential write stream based on a logical block address of the write command, a number of logical block addresses in the write command, and a queue depth.
However, Jean et al. teaches after receiving the first command, receive a second command and a third command from the access device, at 1004. The second command may be associated with a second LBA that precedes the first LBA and the third command may be associated with a third LBA that succeeds the first LBA (see column 12, lines 66-67 and column 13, lines 1-4); and wherein command size, queue depth, etc. may also be adaptively varied to tune the stream detection algorithm (see column 9, lines 22-24)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gorrie et al. to include the above mentioned to improve the performance of the data storage device (see Jean, column 3, lines 8-25).
Claim(s) 5, 12 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gorrie et al. (US 11,294,824) and Jean et al. (US 9,977,623) as applied to claim 1, 8 and 15 above, and further in view of Cariello et al. (US 11,507,518)
With respect to claim 5, Gorrie et al. teaches wherein the memory sub-system controller is further configured to perform operations comprising: sending, to a central processing unit of the memory device, a read message that includes the one or more logical block addresses (see column 14, lines 10-33; controller generates/performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read)).
Gorrie et al. and Jean et al. do not teach wherein the memory sub-system controller is further configured to perform operations comprising: identifying, based on performing a logical block address table lookup, one or more logical block addresses for the other data associated with the sequential write stream.
However, Cariello et al. teaches wherein in response to determining that a stream is open (e.g., that at least a first entry of a terminal L2P table has been written to the terminal L2P table or that data has been written to a user data block at a physical address corresponding to the first entry of the terminal table), at 630 the memory device may determine whether the stream is being continued (e.g., is related to one or more previous processes or operations, such as access operations). For example, the memory device may determine whether the LBA in the write command received at 605 is associated with storing data sequentially (e.g., at a consecutive physical address) relative to data written (see column 14, lines 4-16).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Gorrie et al. and Jean et al. to include the above mentioned to improve read latency (see Cariello, column 3, lines 39-41).
With respect to claim 12, Gorrie et al. teaches sending, to a central processing unit of the memory device, a read message that includes the one or more logical block addresses (see column 14, lines 10-33; controller generates/performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read)).
Gorrie et al. and Jean et al. do not teach identifying, based on performing a logical block address table lookup, one or more logical block addresses for the other data associated with the sequential write stream.
However, Cariello et al. teaches wherein in response to determining that a stream is open (e.g., that at least a first entry of a terminal L2P table has been written to the terminal L2P table or that data has been written to a user data block at a physical address corresponding to the first entry of the terminal table), at 630 the memory device may determine whether the stream is being continued (e.g., is related to one or more previous processes or operations, such as access operations). For example, the memory device may determine whether the LBA in the write command received at 605 is associated with storing data sequentially (e.g., at a consecutive physical address) relative to data written (see column 14, lines 4-16).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gorrie et al. and Jean et al. to include the above mentioned to improve read latency (see Cariello, column 3, lines 39-41).
With respect to claim 19, Gorrie et al. teaches wherein the instructions, when executed by the processing device, further cause the processing device to perform operations comprising: sending, to a central processing unit of the memory device, a read message that includes the one or more logical block addresses (see column 14, lines 10-33; controller generates/performs a first read of data associated with a head portion including at least one preceding logical address, and as represented by block 606, the controller performs a second read of data associated with a tail portion including at least one following logical address (i.e., preceding data and following data comprising the sequential data is read)).
Gorrie et al. and Jean et al. do not teach wherein the instructions, when executed by the processing device, further cause the processing device to perform operations comprising: identifying, based on performing a logical block address table lookup, one or more logical block addresses for the other data associated with the sequential write stream.
However, Cariello et al. teaches wherein in response to determining that a stream is open (e.g., that at least a first entry of a terminal L2P table has been written to the terminal L2P table or that data has been written to a user data block at a physical address corresponding to the first entry of the terminal table), at 630 the memory device may determine whether the stream is being continued (e.g., is related to one or more previous processes or operations, such as access operations). For example, the memory device may determine whether the LBA in the write command received at 605 is associated with storing data sequentially (e.g., at a consecutive physical address) relative to data written (see column 14, lines 4-16).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gorrie et al. and Jean et al. to include the above mentioned to improve read latency (see Cariello, column 3, lines 39-41).
Allowable Subject Matter
Claims 4, 6-7, 11, 13-14, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jacobson et al. (US2008/0028147) teaches prefetching additional sequential blocks of data, which may be useful when a data operation is a stream of sequential reads or sequential write.
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/ARACELIS RUIZ/ Primary Examiner, Art Unit 2139
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