DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-9 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, 7 and 8 of U.S. Patent No. 10854139. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims correspond as follows:
Application No. 19/200,516
U.S. Patent No. 10854139
Claim 1
Claim 1
Claim 3
Claim 7
Claim 4
Claim 7
Claim 5
Claim 8
Claim 6
Claim 5
Claim 7
Claim 1
Claim 8
Claim 1
Claim 9
Claim 1
Claim 16
Claim 1
Claims 1, 3, 5-8, 10 and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 4, 7 and 10 of U.S. Patent No. 11257426. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims correspond as follows:
Application No. 19/200,516
U.S. Patent No. 11257426
Claim 1
Claim 4
Claim 3
Claim 7
Claim 5
Claim 1 initialization transistor
Claim 6
Claim 1
Claim 7
Claim 1 and Claim 3
Claim 8
Claim 1
Claim 10
Claim 10
Claim 16
Claims 1 and 3
Claim 17
Claim 7
Claim 18
Claim 3
Claims 16-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 12 of U.S. Patent No. 11823621. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims correspond as follows:
Application No. 19/200,516
U.S. Patent No. 11823621
Claim 16
Claim 1
Claim 17
Claim 12
Claim 18
Claim 1
Claim 19
Claim 1
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9, 10 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 2016/0063921) in view of Osawa et al. (US 2015/0055051).
In regard to claim 1, Tsai et al. teach a display pixel comprising: a light-emitting diode (fig. 3 element 304); a silicon drive transistor coupled to the light-emitting diode (paragraph 25 and element T2); a capacitor coupled between the silicon drive transistor and the light-emitting diode (C1); and a first transistor coupled across two terminals of the silicon drive transistor (T3) but does not teach using both a silicon transistor and semiconducting-oxide transistor in the same pixel.
Osawa et al. teach using both a silicon transistor and semiconducting-oxide transistor in the same pixel (paragraph 45).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Tsai et al. with the hybrid pixel of Osawa et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Tsai et al. with the hybrid pixel of Osawa et al. because different types of transistors have different characteristics (i.e. size, parasitic capacitance, leakage current). One of ordinary skill in the art would recognize that the use of two types of transistors in a pixel would allow for the optimization of parameters by the selective use of the two types of transistors in different areas of the pixel.
In regard to claim 2, Tsai et al. teach wherein the capacitor has a first terminal coupled to a gate terminal of the drive transistor (C1 connected to gate of T2) and a second terminal coupled to an anode of the light-emitting diode (C1 connected to anode of 504 at drain of T6).
In regard to claim 3, Tsai et al. teach a first emission transistor coupled between the silicon drive transistor and the light-emitting diode (T5).
In regard to claim 4, Tsai et al. teach a second emission transistor coupled between the silicon drive transistor and a power supply line (T4).
In regard to claim 5, Tsai et al. teach an initialization transistor coupled between an initialization line and a node disposed between the capacitor and the light-emitting diode (T6).
In regard to claim 6, Tsai et al. teach a switching transistor coupled between a data line and a node disposed between the silicon drive transistor and the first emission transistor (T1).
In regard to claim 7, Tsai et al. teach a transistor directly coupled to the light-emitting diode (T6).
Osawa et al. teach a second semiconducting-oxide transistor (paragraph 51, Osawa et al. teach using multiple semiconducting-oxide transistors).
In regard to claim 9, Tsai et al. teach the first transistor has a gate terminal configured to receive a scan signal; and the second transistor has a gate terminal configured to receive the scan signal (T3 and T6 both receive SCAN2).
Osawa et al. teach a first and second semiconducting-oxide transistors (paragraph 51).
In regard to claim 10, Tsai et al. teach wherein: the first transistor is coupled to a first terminal of the capacitor; and the second transistor is coupled to a second terminal of the capacitor (T3 and T6 coupled to both electrodes of the capacitor).
Osawa et al. teach a first and second semiconducting-oxide transistors (paragraph 51).
In regard to claim 16, Tsai et al. teach a display pixel comprising: a light-emitting diode (fig. 3 elemetn 304); a silicon drive transistor coupled in series with the light-emitting diode (Paragraph 25 and element T2); and a transistor coupled to an anode of the light-emitting diode (T6).
Osawa et al. teach using both a silicon transistor and semiconducting-oxide transistor in the same pixel (paragraph 45).
In regard to claim 17, Tsai et al. teach one or more silicon emission transistors coupled in series with the silicon drive transistor (T4 and T5).
In regard to claim 18, Tsai et al. teach a second transistor coupled across two terminals of the silicon drive transistor (T3).
Osawa et al. teach a first and second semiconducting-oxide transistors (paragraph 51).
In regard to claim 19, Tsai et al. teach a switching transistor (T1) configured to load a data signal onto the display pixel during a first time period and to load a reset voltage onto the display pixel during a second time period (Fig. 4, paragraphs 45 and 47. Lin et al. show the transistor T1 loading a max voltage (reset) onto the pixel during the reset period and a data signal during the second time period).
In regard to claim 20, Tsai et al. teach wherein the switching transistor comprises a silicon transistor (paragraph 25).
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 2016/0063921) in view of Kim (US 2015/0109278).
In regard to claim 11, Tsai et al. teach a method of operating a display pixel having a drive transistor, a light-emitting diode, and a switching transistor, the method comprising: during an emission period, using the drive transistor to pass a drive current through the light-emitting diode (paragraph 49, T2, T4 and T5 are all on during emission state); and during a blanking period, performing a reset operation by using the switching transistor to load a reset voltage into the display pixel (paragraph 45, maximum reference voltages applied to data lines during reset period) but does not specifically teach a vertical blanking period.
Kim teaches performing a reset operation during a vertical blanking period (paragraph 62).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Tsai et al. with the vertical blanking period of Kim. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Tsai et al. with the vertical blanking period of Kim because performing operations in the vertical blanking time, as shown in Kim, would allow the device to more accurately control the display current during an inactive time when display operations are not conducted.
In regard to claim 12, Tsai et al. teach during a refresh operation, using the switching transistor to load a data signal into the display pixel (paragraph 47, data signals loaded through T1).
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. in view of Kim further considered with Qian (US 2015/0356916).
In regard to claim 13, Tsai et al. and Kim teach during the reset operation, activating an emission transistor (fig. 4, in the reset period EM1 is active which activates the emission transistor T4) but does not teach activating the emission transistor coupled between the drive transistor and the light-emitting diode.
Qian teaches activating the emission transistor coupled between the drive transistor and the light-emitting diode (figs. 2, 3 and paragraph 33).
The three are analogous art because they all deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Tsai et al. and Kim with the circuit reset of Qian. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Tsai et al. and Kim with the circuit reset of Qian because it would prevent the data of the previous frames from influencing the current frame.
In regard to claim 14, Qian teaches before the reset operation, performing an on-bias stress operation by using the switching transistor to load a data voltage into the display pixel (paragraph 34, signal load phase. The signal load phase of Qian comes after the reset phase in one frame but it comes before the reset phase of the next frame).
In regard to claim 15, Qian teaches during the on-bias stress operation, deactivating the emission transistor (paragraph 34).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm.
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/JOSEPH R HALEY/ Primary Examiner, Art Unit 2621
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