Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 2-21 are pending in the application under prosecution and have been examined. Claim 1 has been canceled.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-27 of U.S. Patent No. 12,299,325.
Claim 2 (Application 19/200,523)
Claim 15 (U.S. Patent 12,299,325)
A memory device, comprising: one or more memory dies; non-volatile storage; and one or more controllers coupled with the one or more memory dies and the non- volatile storage, the one or more controllers configured to cause the memory device to: store, at the non-volatile storage, an indication of a duration of operating the memory device within an operating frequency range;
modify one or more operational parameters of the memory device based at least in part on the stored indication of the duration of operating the memory device within the operating frequency range; and
perform one or more operations of the memory device based at least in part on the modification of the one or more operational parameters of the memory device.
A memory device, comprising: an array of memory cells configured to operate in response to a command received at the memory device; at least one sensor configured to output an indication of an operating frequency of the array; a non-volatile storage component; and
logic configured to cause the memory device to: determine a first duration of operating the array within a first operating frequency range and a second duration of operating the array within a second operating frequency range based at least in part on whether the indication of the operating frequency of the array corresponds to the first operating frequency range or the second operating frequency range; and
write, to the non-volatile storage component, an indication of the first duration and an indication of the second duration based at least in part on whether the indication of the operating frequency of the array corresponds to the first operating frequency range or the second operating frequency range.
Claim 2 the current application recite similar features … “store, at the non-volatile storage, an indication of a duration of operating the memory device within an operating frequency range; modify one or more operational parameters of the memory device based at least in part on the stored indication of the duration of operating the memory device within the operating frequency range,” similar to claim 15 of the U.S. Patent 12,299,325, reciting … write, to the non-volatile storage component, an indication of the first duration and an indication of the second duration based at least in part on whether the indication of the operating frequency of the array corresponds to the first operating frequency range or the second operating frequency range.
Independent Claims 2 and 17 corresponds to independent claims 1 and 15. The features of claims 3-16 and 18-21 are obviously modified in language but cover the same as the features of claims 2-14 and 16-26 of U.S. Patent 12,299,325.
Application 19/200,523
U.S. Patent 12,299,325
(New) The memory device of claim 2, further comprising: one or more operating frequency sensors, wherein the one or more controllers are configured to store the indication of the duration of operating the memory device within the operating frequency range based at least in part on an output of the one or more operating frequency sensors.
20. (New) The memory die of claim 17, wherein the one or more sensors comprise: a first sensor configured to output a first indication of the memory die operating in accordance with a first operating frequency range; and a second sensor configured to output a second indication of the memory die operating in accordance with a second operating frequency range that is different from the first operating frequency range.
one or more sensors configured to output an indication of operation of the memory die in accordance with a respective operating frequency range
The apparatus of claim 16, wherein the non-volatile storage component is configured to be accessed by the host device to communicate an indication of operating the array within one or more of the first operating frequency range or the second operating frequency range.
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Langi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus)." ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-21 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190172510 (KIM et al) in view of US 20200132749 (RYU et al).
With respect to claim 2, KIM teaches a memory device (memory system, Fig. 2, Fig. 3), comprising: one or more memory dies (bank of memory arrays 120, Fig. 2; 280, Fig. 3) [Par. 0045-0046]; non-volatile storage; and one or more controllers coupled with the one or more memory dies and the non- volatile storage (memory controller 110, Fig. 2; bank of control logic 230, Fig. 3: Par. 0035), the one or more controllers configured to cause the memory device to: store, at the non-volatile storage, operating the memory device within an operating frequency range (control operation performing training operation on a plurality of operating frequencies; perform training operation on the plurality of operating frequencies to obtain, as a configurable operating parameter for each of the plurality of operating frequencies) [Par. 0035-0039; Par. 0022-0023]; modify one or more operational parameters of the memory device based at least in part on the stored parameters operating the memory device within the operating frequency range (store optimized configurable operating parameter frequencies as training data; obtain, as a configurable operating parameter for each of the plurality of operating frequencies, at least one of a plurality of operating parameters of the memory device, store, as training data, the obtained configurable operating parameter for each of the plurality of operating frequencies)[Par. 0032; Par. 0041; Par. 0022-0023]; and perform one or more operations of the memory device based at least in part on the modification of the one or more operational parameters of the memory device (used optimized operating parameters based on training data of obtained configurable operating parameter for each of the plurality of operating frequencies) [Par. 0041; Par. 0004-0006; Par. 0022-0023].
KIM teaches data valid windows measured for an operating frequency among the plurality of operating frequencies of the memory device [Par. 0060-0068] fails to specifically teach an indication of a duration of the operating frequencies. However, RYU teaches frequency sensor to sense an operating frequency of each of a plurality of cores the sensor used to collect information about a condition or parameter associated with operating frequencies of learning device on test indicating operation performed at a given period, i.e., operations be performed at a time point when an operation of the electronic device starts and at a time point when the operation of the electronic device ends [Fig. 5; Par. 0079-0082; Par. 0074-0076; Par. 0063-0068]; (the sensor to output a signal for providing the obtained parameter values to the core circuit; the sensor to provide the cores with the parameter values which are obtained in real time and the values stored in memory) [Par. 0047-0049Par. 0066-0068]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing data of the current application, to combine the training operation on a plurality of operating frequencies, as taught by KIM with the reference performance parameter values of RYU, in order to measure minimum operating levels of trained core, therefore calculating expected degradation level of the trained core device, as taught by RYU [Par. 0070].
With respect to claim 17, KIM teacehs memory die, comprising: an array of memory cells (memory system arranged as a plurality of bank of memory arrays Fig. 2; Fig. 3) [Par. 0045-0046; Par. 0035); one or more sensors configured to output an indication of operation of the memory die in accordance with a respective operating frequency range (sensor couple to the corresponding bank array to receive data values via data paths and measure plurality of operating parameters of the memory device include a plurality of drive strengths of the memory device) [Par. 0055; Par. 0060-0064]; and circuitry coupled with the array of memory cells and the one or more sensors, the circuitry configured to cause the memory die to: increment a value of one or more counters based at least in part on the output of the one or more sensors (values of the drive strengths being increases as in an order of drive strengths measuring first ranges of the plurality of data valid windows may be measured based on the data signal DQ) [Par. 0063-0066; Par. 0080-0086]; and modify one or more operational parameters of the memory die based at least in part on the incremented value of the one or more counters (store optimized configurable operating parameter frequencies as training data; obtain, as a configurable operating parameter for each of the plurality of operating frequencies, at least one of a plurality of operating parameters of the memory device, store, as training data, the obtained configurable operating parameter for each of the plurality of operating frequencies)[Par. 0032; Par. 0041; Par. 0022-0023; Par. 0061-0064].
KIM teaches data valid windows measured for an operating frequency among the plurality of operating frequencies of the memory device [Par. 0060-0068] fails to specifically teach storing an indication of a duration of the operating frequencies. However, RYU teaches frequency sensor to sense an operating frequency of each of a plurality of cores the sensor used to collect information about a condition or parameter associated with operating frequencies of learning device on test indicating operation performed at a given period, i.e., operations be performed at a time point when an operation of the electronic device starts and at a time point when the operation of the electronic device ends [Fig. 5; Par. 0079-0082; Par. 0074-0076; Par. 0063-0068]; (the sensor to output a signal for providing the obtained parameter values to the core circuit; the sensor to provide the cores with the parameter values which are obtained in real time and the values stored in memory) [Par. 0047-0049Par. 0066-0068]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing data of the current application, to combine the training operation on a plurality of operating frequencies, as taught by KIM with the reference performance parameter values of RYU, in order to measure minimum operating levels of trained core, therefore calculating expected degradation level of the trained core device, as taught by RYU [Par. 0070].
With respect to claim 3, KIM and RYU, combined, teach the memory device, further comprising: one or more operating frequency sensors, wherein the one or more controllers are configured to store the indication of the duration of operating the memory device within the operating frequency range based at least in part on an output of the one or more operating frequency sensors
(the sensor to provide the cores with the parameter values which are obtained in real time and the values stored in memory) [RYU’s Par. 0066-0068]
(obtain, as a configurable operating parameter for each of the plurality of operating frequencies, at least one of a plurality of operating parameters of the memory device, store, as training data, the obtained configurable operating parameter for each of the plurality of operating frequencies) [KIM’s Par. 0032; Par. 0041; Par. 0061-0064].
With respect to claim 4, KIM and RYU, combined, teach the memory device, wherein at least one of the one or more operating frequency sensors is included in a memory die of the one or more memory dies
(the sensor to obtain parameter values indicating the sensed factors, a level of an operating voltage, and/or an operating frequency value of the cores , and output a signal for providing the obtained parameter values to the core circuit) [RYU’s Par. 0047-0049].
With respect to claim 5, KIM and RYU, combined, teach the memory device, wherein the modification to the one or more operational parameters of the memory device comprises a modification to a timing parameter
(obtaining data over predetermined time interval, the time measured and optimized such that configurable operating parameter frequencies change) [KIM’s Par. 0066-0067].
With respect to claim 6, KIM and RYU, combined, teach the memory device, wherein the modification to the one or more operational parameters of the memory device comprises a modification to a voltage parameter
(the sensor to provide the cores with the parameter values which are obtained in real time and the values stored in memory, where the cores may obtain the parameter values provided from the sensor and obtain a level of an operating voltage and/or an operating frequency value of each of the cores) [RYU’s Par. 0066-0068].
With respect to claim 7, KIM and RYU, combined, teach the memory device, wherein the modification to the one or more operational parameters of the memory device comprises a modification to an access rate parameter
(the sensor to obtain parameter values indicating the sensed factors, a level of an operating voltage, and/or an operating frequency value of the cores, and output a signal for providing the obtained parameter values to the core circuit) {RUYYU’s Par. 0047-0049].
With respect to claim 8, KIM and RYU, combined, teach the memory device, wherein the one or more controllers are configured to cause the memory device to: store, at the non-volatile storage, a second indication of a second duration of operating the memory device within a second operating frequency range; and modify the one or more operational parameters of the memory device based at least in part on the stored second indication of the second duration of operating the memory device within the second operating frequency range
(store optimized configurable operating parameter frequencies as training data; obtain, as a configurable operating parameter for each of the plurality of operating frequencies, at least one of a plurality of operating parameters of the memory device, store, as training data, the obtained configurable operating parameter for each of the plurality of operating frequencies) [KIM’s Par. 0032; Par. 0041; Par. 0022-0023; Par. 0061-0064];
(parameter value associated with a lifetime of a first core and an operating level associated with an operation of first core) [RYU’s Par. 0008-0009; Par. 0030-0032].
With respect to claim 9, KIM and RYU, combined, teach the memory device, wherein the modification to the one or more operational parameters of the memory device comprises a die-specific modification to one of the one or more memory dies based on the indication of the duration of operating the memory device within the operating frequency range being a die-level indication of the one of the one or more memory dies
(memory device operating based on one of a plurality of operating frequencies, and the training operation performed on the plurality of operating frequencies of the memory device, at least one of a plurality of operating parameters of the memory device is obtained as a configurable operating parameter for each of the plurality of operating frequencies) [KIM’s Par. 0022-0025];
(sensing parameter value associated with a lifetime of a first core and an operating level associated with an operation of first core, each having predicted level under control of the core, and the sensor to generate signal indicating an operating frequency value of the sensed operating frequency) [RYU’s Par. 0008-0009; Par. 0030-0032].
.
With respect to claim 10, KIM and RYU, combined, teach the memory device, wherein, to perform the one or more operations of the memory device, the one or more controllers are configured to cause the memory device to: select a memory die of the one or more memory dies for the one or more operations based at least in part on the modification of the one or more operational parameters of the memory device
(after training data, the optimized operating parameter for the memory device is used based on the training data TDAT, the current operation mode of the memory device, and the operating frequency of the memory device 120 is changed according to the DVFS scheme) [KIM’s Par. 0090-0093].
With respect to claim 11, KIM and RYU, combined, teach the memory device, wherein the one or more controllers are configured to cause the memory device to: store, at the non-volatile storage, an indication of an operating condition violation at the memory device; and modify the one or more operational parameters of the memory device based at least in part on the stored indication of the operating condition violation
(calculate a function value based on values of an operating parameters result in predicted value with respect to each of the cores) [RYU’s Par. 0056-0059].
With respect to claim 12, KIM and RYU, combined, teach the memory device, wherein, to store the indication of the operating condition violation, the one or more controllers are configured to cause the memory device to: increment a counter of operating condition violation
(calculate drive operating values and replace parameter values based on associated condition of each of the cores) [RYU’s Par. 0059-0061].
With respect to claim 13, KIM and RYU, combined, teach the memory device, wherein the operating condition violation comprises an operating frequency associated with the memory device satisfying a threshold (the sensor configured to measure first operating level, and the processor configured to obtain the first degree of degradation by calibrating the predicted degree of degradation based on the first operating level) [RYU’s Par. 0076-0078; Par. 0082-0084].
With respect to claim 14, KIM and RYU, combined, teach the memory device, wherein the one or more controllers are configured to cause the memory device: output the indication of the duration of operating the memory device within the operating frequency range; receive a command based at least in part on the output of the indication of the duration of operating the memory device within the operating frequency range; and modify the one or more operational parameters of the memory device based at least in part on the command
(storing the training data TDAT where the optimized operating parameter for the memory device is used based on the training data TDAT, the current operation mode of the memory device, and the operating frequency of the memory device 120 is changed according to the DVFS scheme) [KIM’s Par. 0090-0093]
(the sensor to output a signal for providing the obtained parameter values to the core circuit; the sensor to provide the cores with the parameter values which are obtained in real time and the values stored in memory) [RYU’s Par. 0047-0049; Par. 0055; Par. 0066-0068].
With respect to claim 15, KIM and RYU, combined, teach the memory device, wherein the non-volatile storage is configured to be accessed by a host device
(sensor to output a signal for providing the obtained parameter values to the core circuit) [RYU’s Par. 0047-0049];
(the sensor to provide the cores with the parameter values which are obtained in real time and the values stored in memory) [KIM’s Par. 0066-0068].
With respect to claim 16, KIM and RYU, combined, teach the memory device, wherein the non-volatile storage is separate from the one or more memory dies
(the sensor to provide the cores with the parameter values which are obtained in real time and the values stored in memory) [Par. 0066-0068].
With respect to claim 18, KIM and RYU, combined, teach the memory die, wherein the modification to the one or more operational parameters of the memory die comprises a modification to a timing parameter, a modification to a voltage parameter, a modification to an access rate parameter, or a combination thereof (performing training where the configurable operating parameter for each of the plurality of operating frequencies is stored as the training data TDAT in the internal memory, the training being based on operating frequency parameter, measured reference) [KIM’s Par. 0072-0073].
measuring the plurality of data valid windows (e.g., in operation S210), first ranges of the plurality of data valid windows may be measured based on the data signal DQ and the data strobe signal DQS, and second ranges of the plurality of data valid windows may be measured based on the reference voltage VREF.
With respect to claim 19, KIM and RYU, combined, teach the memory die,, wherein the circuitry is further configured to cause the memory die to: output an indication of the value of the counter; and receive a command based at least in part on the indication of the value of the counter, wherein the modification to the one or more operational parameters of the memory die is based at least in part on the command
(each core to calculate the operating frequency values where each core to request the parameter values of each of the cores from the sensor, the sensor to provide the parameter values in response to the request of the cores and calculate the operating levels measured by operations) [RYU’s Par. 0082-0085].
With respect to claim 20, KIM and RYU, combined, teach the memory die,, wherein the one or more sensors comprise: a first sensor configured to output a first indication of the memory die operating in accordance with a first operating frequency range; and a second sensor configured to output a second indication of the memory die operating in accordance with a second operating frequency range that is different from the first operating frequency range
(performing a training operation on a plurality of operating frequencies of the memory device to obtain configurable operating parameters for each of the plurality of operating frequencies; storing the obtained configurable operating parameter for each of the plurality of operating frequencies comprises: storing, as the training data, a relationship between the plurality of operating frequencies and configurable drive strengths for the plurality of operating frequencies, based on the at least one selected data valid window) [KIM’s Par. 0090-0093];
(frequency sensor to sense an operating frequency of each of the cores based on a clock received from a clock the frequency sensor to generate a signal indicating an operating frequency value of the sensed operating frequency) [RYU’s Par. 0055].
With respect to claim 21, KIM and RYU, combined, teach the memory die,, wherein, to increment the value of the counter, the circuitry is configured to cause the memory die to: scale counts of a clock signal based at least in part on the respective operating frequency of the memory die
(each of the operating frequencies of the memory device being changed according to the measured training data measured for operating frequencies based on clock signal associated with respective frequency range) [KIM’s Par. 0082-0084; Par. 0066-0069];
(frequency sensor to sense an operating frequency of each of the cores based on a clock received from a clock the frequency sensor to generate a signal indicating an operating frequency value of the sensed operating frequency) [RYU’s Par. 0055].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220035535 A1 (Van De Graaff et al) teaching methods, systems, and devices for life expectancy monitoring for memory devices, the system to include components configured for monitoring health or life expectancy of the memory device, such as components that perform comparisons between signals or other operating characteristics resulting from operating at the memory device and one or more threshold values that may be indicative of a life expectancy of the memory device, a memory device to perform a subsequent operation based on such a comparison, or may provide an indication of a life expectancy to a host device based on one or more comparisons or determinations about health or life expectancy.
US 20210089230 A1 (MAYER et al) teaching memory device or an apparatus that includes a memory device having circuitry configured to heat the memory device activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device) or based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device).
US 20200387422 A1 (BELL et al) teaching methods, systems, and devices for persistent health monitoring for volatile memory devices , a memory device to determine that an operating condition associated with an array of memory cells on the device, such as a temperature, current, voltage, or other metric of health status is outside of a range associated with a risk of device degradation, the memory device to monitor a duration over which the operating condition is outside of the range, and may determine whether the duration satisfies a threshold, the memory device to store an indication of when (e.g., each time) the duration satisfied the threshold.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached at (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
Prosecution Insights