DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the response to election filed 8/10/2026. Claims 1-6 have been elected for further examination. Claims 7-8 have been canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2014-171334 in view of Ballarin et al. (US 2019/0146532).
Regarding claim 1, JP’334 figure 4 discloses A power supply circuit (100B, figure 4) providing power to a system on chip (20, figure 4), comprising: a power generation circuit (100B) adjusting an input voltage (10) according to a first feedback voltage (VFB4) to generate an output voltage (Vout1); a first feedback circuit (188, 189) coupled to the power generation circuit and generating the first feedback voltage (VFB4) according to the output voltage (VOUT1); a conducting wire (wire coupled between Vout1 and Vout2) coupled between the power generation circuit and the SOC to receive the output voltage, using the output voltage as a load voltage and providing the load voltage (Vout2) to the SOC; a second feedback circuit (182) coupled to the conducting wire and generating a second feedback voltage (VFB3) according to the load voltage; and a compensation circuit (185, 186) adjusting the first feedback voltage according to the second feedback voltage and comprising: an operational amplifier (OP2) comprising a non-inverting input terminal (+), an inverting input terminal (-) and an output terminal (output of OP2); a third resistor coupled between the output terminal and the first feedback circuit.
JP334 reference does not disclose the non-inverting input terminal receives the second feedback voltage, and the inverting terminal is coupled to a reference voltage; a first resistor coupled between the output terminal and the node; a second resistor coupled between the node and a ground terminal; and a third resistor coupled between the output terminal and the first feedback circuit, wherein: in response to the second feedback voltage being higher than a first reference voltage, the compensation circuit increases the first feedback voltage, in response to the first feedback voltage being higher than a second reference voltage, the power generation circuit reduces the output voltage, in response to the second feedback voltage being lower than the first reference voltage, the compensation circuit reduces the first feedback voltage, in response to the first feedback voltage being lower than the second reference voltage, the power generation circuit increases the output voltage as called for in claim 1.
Ballarin et al.’s figure 2 discloses an operational amplifier (210) comprising a non-inverting input terminal (+), an inverting input terminal (-) and an output terminal (240);
the non-inverting input terminal receives a feedback voltage (250), and the inverting terminal is coupled to a reference voltage (230); a first resistor (222) coupled between the output terminal and the node (junction of 222 and 224); a second resistor (224) coupled between the node and a ground terminal. This arrangement allows the output of operational amplifier stable and constant over unwanted signals (see paragraphs 0030, 0041). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the present invention to replace JP334’s operational amplifier configuration with Ballarin et al.’s operational amplifier for the purpose of providing a stable output signal as taught by Ballarin et al. reference.
Regarding the limitation of “ wherein: in response to the second feedback voltage being higher than a first reference voltage, the compensation circuit increases the first feedback voltage, in response to the first feedback voltage being higher than a second reference voltage, the power generation circuit reduces the output voltage, in response to the second feedback voltage being lower than the first reference voltage, the compensation circuit reduces the first feedback voltage, in response to the first feedback voltage being lower than the second reference voltage, the power generation circuit increases the output voltage” is also seen present as results of the combination of references.
Regarding claim 2, wherein the second feedback circuit (the substituted operational amplifier) is closer to the SOC (20) than the first feedback circuit (188 and 189).
Regarding claim 3, the first feedback circuit is a first voltage-division circuit (188, 189) which divides the output voltage to generate the first feedback voltage, and the second feedback circuit is a second voltage-division circuit (183, 184) which divides the load voltage to generate the second feedback voltage.
Regarding claim 4, wherein the first reference voltage is lower than the second reference voltage.
Regarding claim 5, in response to the second feedback voltage being higher than the first reference voltage, a current passing from the output terminal through the third resistor and into the first feedback circuit increases, and in response to the second feedback voltage being lower than the first reference voltage, the current passing from the output terminal through the third resistor and into the first feedback circuit reduces is seen to be present in the combination references.
Regarding claim 6, wherein the compensation circuit is integrated into the SOC.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, applicant’s cited prior art has been carefully considered.
Zhang et al. (USP 7,576,527), discloses a converter (200) has resistive voltage dividers (212, 216) including four resistive elements coupled to ends of an inductive load. An amplifier (220) is responsive to a feedback voltage and a reference voltage, where the feedback voltage represents voltage at one of the ends of the elements. A comparator (204) is responsive to output voltage of the amplifier, where the comparator generates output voltage applied to a control line of the converter. A voltage combiner (228) combines output voltage of the amplifier with another reference voltage and supplies combined voltage to the comparator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN T LAM/Primary Examiner, Art Unit 2836 9/15/2026
Prosecution Insights