Non-Final Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 19-23 and 29-33 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12,321,233 B2 (hereinafter ‘233). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-3 of U.S. Patent No. 12,321,233 B2 contain(s) every element of claim(s) 19-23 and 29-33 of the instant application and as such anticipate(s) claim(s) 19-23 and 29-33 of the instant application.
The following is a mapping of claim 19:
Claim 19 of Instant Application
Claim 1 of 12,321,233 B2
A memory system capable of communicating with a host and one or more external memory systems
A host; a plurality of memory systems, the host transmits requests to a memory system, the controller of a memory system transmits data to another memory system, Figure 1 defines the memory systems are external
the memory system comprising: a nonvolatile memory; and a controller electrically connected to the nonvolatile memory
each memory system includes a controller and a nonvolatile memory
a controller configured to: store first data in the nonvolatile memory
the controller of the second memory system is configured to store second data in a second nonvolatile memory
a controller configured to: receive, from the host, a first request and first update data updated from the first data
the host is configured to, in a case where the second data are updated: transmit, to the second memory system, a second request and second update data updated from the second data (i.e. the controller receives a request)
a controller configured to: receive, from a first memory system that is one of the one or more external memory systems, first exclusive-logical-OR data
the controller of the first memory system is further configured to: generate first exclusive-logical-OR data by performing an exclusive-logical-OR operation on at least the first data and the first update data; transmit the first exclusive-logical-OR data to the second memory system (i.e. the controller at the second memory system receives the XOR data from the first memory system)
and in response to receiving the first request: generate second exclusive-logical-OR data by performing an exclusive-logical-OR operation on the first data, the first update data, and the first exclusive-logical-OR data
the controller of the second memory system is further configured to, in response to receiving the second request: generate second exclusive-logical-OR data by performing an exclusive-logical-OR operation on the second data, the second update data, and the first exclusive-logical-OR data
transmit, to the host, a first response to the first request
transmit a second response to the second request to the host
transmit, to a second memory system that is another one of the one or more external memory systems, the second exclusive-logical-OR data
transmit the second exclusive-logical-OR data to the third memory system
Regarding claim 20, claim 1 of ‘233 discloses wherein a first controller of the first memory system is configured to store second data in a first nonvolatile memory of the first memory system, and the first data and the second data constitute at least a part of an error correction code frame (the controller of the first memory system is configured to store first data in a first nonvolatile memory, the first data and the second data constitute at least a part of an error correction code frame).
Regarding claim 21, claim 2 of ‘233 discloses wherein a second controller of the second memory system is configured to store a parity in a second nonvolatile memory of the second memory system, and the first data, the second data, and the parity constitute at least a part of the error correction code frame (wherein the controller of the third memory system is configured to store a parity in a third nonvolatile memory, and the first data, the second data, and the parity constitute at least a part of the error correction code frame).
Regarding claim 22, claim 1 of ‘233 discloses wherein the first exclusive-logical-OR data is generated in the first memory system by performing an exclusive-logical-OR operation on at least the second data and second update data updated from the second data ( the controller of the first memory system is further configured to, in response to receiving the first request: generate first exclusive-logical-OR data by performing an exclusive-logical-OR operation on at least the first data and the first update data).
Regarding claim 23, claim 3 of ‘233 discloses wherein an update parity is generated in the second memory system by performing an exclusive-logical-OR operation on the parity and the second exclusive-logical-OR data (the controller of the third memory system is further configured to, in response to receiving the third request, generate an update parity by performing an exclusive-logical-OR operation on the parity and the second exclusive-logical-OR data), and the first update data, the second update data, and the update parity constitute at least a part of the error correction code frame that is updated (the first update data, the second update data, and the update parity constitute at least a part of the error correction code frame that is updated).
Regarding claim 29, claim 1 of ‘233 discloses all of the limitations of claim 29 for similar reasons as claim 19 above (see table mapping limitations). Further, the controller of claim 1 of ‘233 performs the method of controlling a nonvolatile memory.
Regarding claims 30-33, claims 1-3 of ‘233 anticipate the limitations of claims 30-33 for the same reasons as claims 20-23 above.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Allowable Subject Matter
Claims 19-23 and 29-33 would be allowable if the non-statutory double patenting rejection was overcome.
Claims 24-28 and 34-38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Patterson et al. disclose in N+1 RAID, new parity = (old data xor new data) xor old parity.
US 11,442,661 B2 (on IDS) discloses offloading parity generation operations and performing XOR operations on the current primary data, the updated primary data, the current parity data, and the interim parity data, in order to generate the updated parity data.
US 11,175,984 B1 (on IDS) discloses that a first drive forwards data (or EC info) to next drive, next drive “combines” received info with its own (e.g. own data or parity) {e.g., XOR operation} and forwards the result on. The last drive stores EC information.
With respect to claim 19, the prior art does not teach or reasonably suggest, in combination with the remaining limitations, a memory system comprising a controller configured to: store first data; receive, from a host, a first request and first update data to update the first data; receive, from a first memory system that is one of the external memory systems, first exclusive-logical-OR data; and in response to receiving the first request: generate second exclusive-logical-OR data by performing an exclusive-logical-OR operation on the first data, the first update data, and the first exclusive-logical-OR data; and transmit, to a second memory system that is one of the external memory systems, the second exclusive-logical-OR data.
With respect to claim 29, the prior art does not teach or reasonably suggest, in combination with the remaining limitations, a method of controlling a nonvolatile memory comprising: storing first data; receiving, from a host, a first request and first update data to update the first data; receiving, from a first memory system that is one of the external memory systems, first exclusive-logical-OR data; and in response to receiving the first request: generating second exclusive-logical-OR data by performing an exclusive-logical-OR operation on the first data, the first update data, and the first exclusive-logical-OR data; and transmitting, to a second memory system that is one of the external memory systems, the second exclusive-logical-OR data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C MASKULINSKI whose telephone number is (571)272-3649. The examiner can normally be reached Monday-Friday 8:00 am-5:00 pm.
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/MICHAEL MASKULINSKI/Primary Examiner, Art Unit 2113
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