Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-3 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,680,596 to Sun et al. (“Sun”) (cited in an IDS).
With respect to claim 1, Sun discloses in Fig. 1A a system, comprising:
a bootstrap circuit having an input (e.g., Vin) and an output (e.g., ckout), comprising:
a boost capacitor (e.g., C3) having a first terminal and a second terminal;
a first transistor (e.g., P2) coupled between the first terminal of the boost capacitor and the output (e.g., ckout) of the bootstrap circuit;
a second transistor (e.g., M4) coupled between a gate of the first transistor (e.g., P2) and the second terminal of the boost capacitor (e.g., C3);
a first switch (e.g., M10) coupled between (e.g., when Md is on) the output (e.g., ckout) of the bootstrap circuit and a ground (e.g., Vdac); and
a timing circuit (e.g., Fig. 1B circuit providing clk_buffer in an inverted form to the gate of M10 via P4 and M11 and providing phi to the gate of M4), comprising:
a logic gate (e.g., 140) having a first input, a second input, and an output, wherein the first input of the logic gate (e.g., 140) is coupled to an input (e.g., clkin) of the timing circuit (e.g., the Fig. 1B circuit), and the output (e.g., output of 140) of the logic gate is coupled to a gate of the second transistor (e.g., output of 140 is provided as phi to the gate of M4 through intervening element 145 and 150); and
a clock path (e.g., the first inverter in Fig. 1B receiving clkin and providing clkinb coupled between the input (e.g., clkin) of the timing circuit and the second input (e.g., the input of 140 which is not coupled to receive a signal through “delays”) of the logic gate, wherein a control input of the first switch (e.g., M10) is coupled to (e.g., clk_buffer output from Fig. 1B is provided as the gate signal of M10 after an inversion through P4 and M11) the clock path (e.g., the first inverter in Fig. 1B receiving clkin and providing clkinb); and
a switch transistor (e.g., Min), wherein a gate of the switch transistor (e.g., Min) is coupled to the output (e.g., ckout) of the bootstrap circuit, and a terminal of the switch transistor (e.g., Min) is coupled to the input (e.g., Vin) of the bootstrap circuit.
With respect to claim 2, the bootstrap circuit further comprises a third transistor (e.g., P1) coupled between the gate of the first transistor (e.g., P2) and a supply rail; and a gate of the third transistor (e.g., P1) is coupled to the output (e.g., phi) of the logic gate (e.g., phi output from 140 via 145 and 150 in Fig. 1B).
With respect to claim 3, the second transistor (e.g., M4) comprises an n-type field effect transistor (NFET); and the third transistor e.g., P1) comprises a p-type field effect transistor (PFET).
With respect to claim 6, a second switch (e.g., M2) is coupled between the first terminal of the boost capacitor (e.g., C3) and a supply rail; a third switch (e.g., M6) is coupled between the second terminal of the boost capacitor (e.g., C3) and the ground; and a fourth switch (e.g., M12) is coupled between the second terminal of the boost capacitor (e.g., C3) and the input (e.g., Vin) of the bootstrap circuit.
With respect to claim 7, the clock path (e.g., the inverter outputting clkinb, the inverter receiving clkinb and outputting a signal to “delays”, and delays) comprises one or more drivers (e.g., the inverter outputting cliinb and/or the inverter receiving clkinb) and a delay circuit (e.g., “delays”) coupled in series, the control input of the first switch (e.g., M10) and a control input of the third switch (e.g., M6) are coupled to (e.g., M10 is coupled to clk_buffer output of the Fig. 1B after an inversion through P4 and M11 and M6 is coupled to phib, wherein cll_buffer and phib in Fig. 1B are coupled to clkinb) a node (e.g., clkinb output of the first inverter receiving clkin) on the clock path located before the delay circuit (e.g., “delays”).
With respect to claim 8, a voltage boost circuit (e.g., 120) is coupled to a control input of the second switch (e.g., S2), and the voltage boost circuit (e.g., 120) is configured to boost a voltage at the node (e.g., clkinb in Fig. 1B is output as phib and phi via intervening elements in Fig. 1B) on the clock path to generate a boosted control signal (e.g., ckboostn), and output the boosted control signal (e.g., ckboostn) to the control input of the second switch (e.g., S2).
With respect to claim 9, a control input of the fourth switch (e.g., M12) is coupled to (e.g., 120 outputting clkoutx via 110) the output of the bootstrap circuit (e.g., 120 and/or 110).
With respect to claim 10, the bootstrap circuit further comprises a voltage boost circuit (e.g., 120) coupled to a control input of the second switch (e.g., M2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Sun.
With respect to claim 4, the logic gate (e.g., 140) discloses an AND gate and fails to disclose a NAND gate. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that an AND gate may be implemented with a NAND gate and an inverter receiving the output of the NAND gate; an official notice of the foregoing fact is hereby taken. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to replace the AND gate 140 in Fig. 1B of Sun using a NAND gate and an inverter receiving the output of the NAND gate because such a modification performs the same required function of an AND gate 140 in Fig. 1B of Sun.
With respect to claim 5, the clock path (e.g., the inverter outputting clkinb, the inverter receiving clkinb and outputting a signal to “delays”, and delays) comprises one or more drivers (e.g., the inverter outputting clkinb and/or the inverter receiving clkinb) and a delay circuit (e.g., “delays”) coupled in series, and the control input of the first switch (e.g., M10) is coupled to (e.g., M10 is coupled to clk_buffer output of the Fig. 1B after an inversion through P4 and M11) a node (e.g., output of the first inverter receiving clkin and outputting clkinb) on the clock path located before the delay circuit (e.g., “delays”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2836
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