Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/07/2025 was filed after the mailing date of the non-final rejection on 06/17/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 11 objected to because of the following informalities: Change the period after "…generate a first output signal." to a semicolon and add an "and" before "…a second conversion circuit…". Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al (US 20240179434 A1, hereinafter, "Han") in view of Fronczak et al (US 11647310 B1, hereinafter, "Fronczak").
Regarding Claim 1, Han teaches An image sensing device comprising: a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines and configured to output a plurality of pixel signals through the plurality of column lines (Han, Fig. 1, 110); a ramp generator configured to generate a first ramp signal and a second ramp signal (Han, Fig. 6A, LS1 & LS2); an analog-to-digital converter (ADC) configured to convert the plurality of pixel signals into digital signals in response to the first ramp signal and the second ramp signal (Han, Fig. 1, 150). Han does not teach a column line controller configured to selectively connect the plurality of column lines to the ADC. However, Fronczak teaches a column line controller configured to selectively connect the plurality of column lines to the ADC (Fronczak, Fig. 9, [0028], ln. 9-10, "…a scrambling block 38 is arranged which is configured to randomize the connection between the columns 14 and further columns 37 and the ADCs 16, 17 per row of the pixel array 11."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Han with those of Fronczak because it is well known in the art to connect a plurality of column lines to an ADC with a controller.
Claims 2-4 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Fronczak and Kobinata et al (US 20190035832 A1, hereinafter, "Kobinata").
Regarding Claim 2, Han and Fronczak teach the limitations of dependent Claim 1 as noted above. Kobinata teaches the plurality of pixels includes: a first pixel connected to a first row line of the plurality of row lines (Kobinata, Fig. 6, 30 & 47A) and a first column line of the plurality of column lines (Kobinata, Fig. 6, 30 & 45B); and a second pixel consecutive with the first pixel and connected to a second row line of the plurality of row lines (Kobinata, Fig. 6, 30 & 47B) and a second column line of the plurality of column lines (Kobinata, Fig. 6, 30 & 45A); wherein the first pixel and the second pixel are arranged in a first column (Kobinata, Fig. 6, 30). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Kobinata with those of Han and Fronczak because it is well known in the art to arrange two consecutive pixels in a column to be connected to first and second row column lines.
Regarding Claim 3, Han, Fronczak, and Kobinata teach the limitations of dependent Claim 2 as noted above. Kobinata teaches the first column line is arranged on a first side of the plurality of pixels to output a first pixel signal (Kobinata, Fig. 6, 45B); and the second column line is arranged on a second side of the plurality of pixels to output a second pixel signal (Kobinata, Fig. 6, 45A). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Kobinata with those of Han, Fronczak, and Kobinata because it is well known in the art to arrange column lines on both sides of a column of pixels.
Regarding Claim 4, Han and Fronczak teach the limitations of dependent Claim 1 as noted above. Kobinata teaches the plurality of pixels includes: a first pixel connected to a first row line of the plurality of row lines (Kobinata, Fig. 6, 30 & 47A) and a first column line of the plurality of column lines (Kobinata, Fig. 6, 30 & 45B); and a second pixel consecutive with the first pixel and connected to the first row line (Kobinata, Fig. 6, 30 & 47A) and a second column line of the plurality of column lines (Kobinata, Fig. 6, 30 & 46A), wherein the first pixel and the second pixel are arranged in a first row (Kobinata, Fig. 6, 30). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Kobinata with those of Han and Fronczak because it is well known in the art to connect consecutive pixels in a first row to first and second column and row lines.
Claims 5 & 7-9 are rejected under 35 U.S.C. as being unpatentable over Han in view of Fronczak and Choi et al (US 20240147089 A1, hereinafter, "Choi").
Regarding Claim 5, Han and Fronczak teach the limitations of dependent Claim 1 as noted above. Choi teaches the ramp generator includes: a first ramp generator configured to generate the first ramp signal (Choi, Fig. 1, 130A); and a second ramp generator configured to generate the second ramp signal (Choi, Fig. 1, 130B). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Choi with those of Han and Fronczak because it is well known in the art to use a first and second ramp generator.
Regarding Claim 7, Han and Fronczak teach the limitations of dependent Claim 1 as noted above. Choi teaches the ADC includes: a first ADC configured to sample and hold column lines of a first group selected by the column line controller from among the plurality of column lines and output signals output by the first group (Choi, [0006], ln. 5-8, "The ADC circuit includes a first comparator group and a second comparator group. The first comparator group is for comparing the first ramp signal with a first pixel signal received from a first column line group, among the plurality of column lines."); a second ADC configured to sample and hold column lines of a second group selected by the column line controller from among the plurality of column lines and output signals output by the second group (Choi, [0006], ln. 8-10, "The second comparator group is for comparing the second ramp signal with a second pixel signal received from a second column line group, among the plurality of column lines."); and a counter that counts instances of a feature within the signals output by the first group and the signals output by the second group, and outputs the counted features as digital signals (Choi, Fig. 1, 142). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Choi with those of Han and Fronczak because it is well known in the art to use a first ADC to sample and hold column lines of a first group selected by a column line controller and output signals as well as use a second ADC to sample and hold column lines of a second group selected by a column line controller and use a counter to count each group.
Regarding Claim 8, Han, Fronczak, and Choi teach the limitations of dependent Claim 7 as noted above. Choi teaches the column line controller includes a plurality of switching circuits that selectively connects the column lines of the first group to the first ADC (Choi, [0008], ln. 6-8, "The ADC circuit includes a first comparator and a second comparator. The first comparator is for comparing a first pixel signal received from the first column line and the third column line with the first ramp signal.") and selectively connects the column lines of the second group to the second ADC (Choi, [0008], ln. 8-10, "The second comparator is for comparing a second pixel signal received from the second column line and the fourth column line with the second ramp signal.") based on a plurality of switching control signals (Choi, [0008], ln. 10-11, "The comparing of the first pixel signal occurs at a comparison time point different from a comparison time point during which the comparing of the second pixel signal occurs."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Choi with those of Han, Fronczak, and Choi because it is well known in the art to use a plurality of switching circuits to connect first and second ADCs to column lines based on a plurality of switching control signals.
Regarding Claim 9, Han, Fronczak, and Choi teach the limitations of dependent Claim 8 as noted above. Choi teaches a column selection controller configured to generate the plurality of switching control signals (Choi, Fig. 11B, [0104], ln. 1-3, "…the image processing device 1210 may further include a selection unit [or a Mux] 1213 selecting outputs from the sub-image processors 1212a, 1212b, and 1212c and transferring the selected output to the image generator 1214."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Choi with those of Han, Fronczak, and Choi because it is well known in the art to generate a plurality of switching control signals using a controller.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Fronczak, Choi, and Kim (KR 20230023381 A, hereinafter, "Kim").
Regarding Claim 6, Han, Fronczak, and Choi teach the limitations of dependent Claim 5 as noted above. Choi teaches each of the first ramp generator and the second ramp generator includes: a current generator configured to generate a reference current (Choi, Fig. 1, [0041], ln. 1-3, "The first ramp signal generator 130a may include a first current source Tramp 1 and first variable resistor Rramp1. The second ramp signal generator 130b may include a second current source Iramp2 and a second variable resistor Rramp2."). Choi does not teach a current controller configured to generate a digital-to-analog conversion (DAC) current based on the reference current; a voltage converter configured to generate a bias voltage based on the DAC current; a ramp signal generator configured to generate a ramp signal based on the bias voltage and a switch control signal; and a resistor circuit configured to control loading of the ramp signal generator. However, Kim teaches a current controller configured to generate a digital-to-analog conversion (DAC) current based on the reference current (Kim, pg. 4, para. 4, ln. 1-2, "In the conventional ramp signal generator, the number of unit current cells [I-Cell] is generated by the same current control digital converter [I-DAC] in the conversion step…"); a voltage converter configured to generate a bias voltage based on the DAC current (Kim, pg. 4, para. 4, ln. 2-3, "…the total current of the unit current cells is applied to the first resistor [R_FR]."); a ramp signal generator configured to generate a ramp signal based on the bias voltage and a switch control signal (Kim, pg. 4, para. 4, ln. 3-4, "Then, the first output voltage [A/D ramp signal, V_FR] will be supplied to all columns…"); and a resistor circuit configured to control loading of the ramp signal generator (Kim, pg. 4, para. 4, ln. 4, "…through the column buffer."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Choi and Kim with those of Han, Fronczak, and Choi because it is well known in the art for ramp generators to include a current generator configured to generate a reference current, a current controller configured to generate a DAC current based on the reference current, a voltage converter configured to generate a bias voltage based on the DAC current, a ramp signal generator configured to generate a ramp signal based on the bias voltage and a switch control signal, and a resistor circuit configured to control loading of the ramp signal generator.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Fronczak and Oh et al (US 20230335175 A1, hereinafter, "Oh").
Regarding Claim 10, Han and Fronczak teach the limitations of dependent Claim 1 as noted above. Oh teaches a plurality of row decoders configured to generate a row line selection signal that activates two consecutive row lines from among the plurality of row lines (Oh, [0053], ln. 1-4, "…even when two rows are simultaneously activated due to a paired row repair scheme at a random sampling moment, it may be possible to efficiently defend against a row hammering attack by randomly selecting and sampling one among the two activated rows."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Oh with those of Han and Fronczak because it is well known in the art to use a plurality of row decoders to generate a selection signal that activates two consecutive row lines.
Claims 11, 12, 14 & 17-20 are rejected under 35 U.S.C. as being unpatentable over Choi in view of Kobinata.
Regarding Claim 11, Kobinata teaches An image sensing device comprising: a first pixel configured to output a first pixel signal through a first column line (Kobinata, Fig. 6, 30 & 45B); a second pixel configured to output a second pixel signal through a second column line (Kobinata, Fig. 6, 30 & 45A). Kobinata does not teach a switching circuit that selectively connects, based on a switching control signal, the first column line to one of a first node and a second node and selectively connects, based on the switching control signal, the second column line to one of the first node and the second node; a first ramp generator configured to generate a first ramp signal; a second ramp generator configured to generate a second ramp signal; a first conversion circuit configured to compare the first ramp signal with a signal applied to the first node, amplify a result of the comparison, and generate a first output signal; and a second conversion circuit configured to compare the second ramp signal with a signal applied to the second node, amplify a result of the comparison, and generate a second output signal. However, Choi teaches a switching circuit that selectively connects, based on a switching control signal, the first column line to one of a first node and a second node and selectively connects, based on the switching control signal, the second column line to one of the first node and the second node (Choi, Fig. 11B, [0104], ln. 1-3, "…the image processing device 1210 may further include a selection unit [or a Mux] 1213 selecting outputs from the sub-image processors 1212a, 1212b, and 1212c and transferring the selected output to the image generator 1214."); a first ramp generator configured to generate a first ramp signal (Choi, Fig. 1, 130A); a second ramp generator configured to generate a second ramp signal (Choi, Fig. 1, 130B); a first conversion circuit configured to compare the first ramp signal with a signal applied to the first node, amplify a result of the comparison, and generate a first output signal (Choi, Fig. 10, [0034], ln. 8-10, "For example, the two comparators may be implemented by an operational transconductance amplifier [OTA] [or a differential amplifier]."); and a second conversion circuit configured to compare the second ramp signal with a signal applied to the second node, amplify a result of the comparison, and generate a second output signal (Choi, Fig. 10, [0034], ln. 8-10, "For example, the two comparators may be implemented by an operational transconductance amplifier [OTA] [or a differential amplifier]."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Choi with those of Kobinata because it is well known in the art to use a switching control signal to connect a first column line to one of a first or second node and connect a second column line to one of a first or second node, a first and second ramp generator to generate first and second ramp signals, and a first and second conversion circuit to compare first and second ramp signals with a signal applied to the first and second nodes, amplify the result of the comparison, and generate first and second output signals.
Regarding Claim 12, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Kobinata teaches the first pixel is consecutively arranged with the second pixel in a first row (Kobinata, Fig. 6, 30).
Regarding Claim 14, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Kobinata teaches the first pixel is consecutively arranged with the second pixel in a first column (Kobinata, Fig. 6, 30).
Regarding Claim 17, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Choi teaches each of the first conversion circuit and the second conversion circuit includes: a first capacitor arranged to receive a pixel signal (Choi, Fig. 10, C1) and a second capacitor arrange to receive a ramp signal to reduce a band of noise (Choi, Fig. 10, C2); a comparator configured to compare a first output from the first capacitor with a second output from the second capacitor, amplify a result of the comparison, and generate an output signal (Choi, Fig. 10, 141_1); and a plurality of switches configured to control an auto-zeroing operation of the comparator (Choi, Fig. 10, [0071], ln. 5-6, "The comparator 141a′ may be initialized in response to an auto-zero signal in an auto-zero period before performing a comparison operation…"). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Choi with those of Choi and Kobinata because it is well known in the art to use capacitors to receive pixel signals and reduce noise from ramp signals.
Regarding Claim 18, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Choi teaches a counter that counts instances of a feature within the first output signal and the second output signal, and outputs the counted features as digital signals (Choi, Fig. 10, 142a').
Regarding Claim 19, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Kobinata teaches a column selection controller configured to generate the switching control signal (Kobinata, Fig. 6, 52A & 52B).
Regarding Claim 20, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Kobinata teaches a row driver configured to generate a row line selection signal that selects the first pixel and the second pixel (Kobinata, Fig. 6, 53A & 53B). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Kobinata with those of Choi and Kobinata because it is well known in the art to use a row driver to select multiple pixels.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Kobinata and Oh.
Regarding Claim 13, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Kobinata teaches the first pixel is connected to a first row line (Kobinata, Fig. 6, 45B); the second pixel is connected to a second row line (Kobinata, Fig. 6, 45A). Kobinata does not teach and the first row line and the second row line are activated simultaneously. However, Oh teaches and the first row line and the second row line are activated simultaneously (Oh, [0053], ln. 1-4, "…even when two rows are simultaneously activated due to a paired row repair scheme at a random sampling moment, it may be possible to efficiently defend against a row hammering attack by randomly selecting and sampling one among the two activated rows.").
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Kobinata and Chao et al (US 20170280086 A1, hereinafter, "Chao").
Regarding Claim 15, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Chao teaches the first pixel and the second pixel are activated simultaneously when the first row line is selected (Chao, Fig. 1, [0088], ln. 5-8, "A first pixel 10a coupled to the first column-out signal path 16a in the associated column 6a is activated by the row driver circuit 12. Simultaneously, a second pixel 10b coupled to the second column-out signal path 16b and a third pixel 10c coupled to the third column-out signal path 16c in the associated column 6a are activated by the row driver circuit 12."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Chao with those of Choi and Kobinata because it is well known in the art to activate multiple pixels simultaneously when a row line is selected.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Kobinata and Kim.
Regarding Claim 16, Choi and Kobinata teach the limitations of dependent Claim 11 as noted above. Choi teaches each of the first ramp generator and the second ramp generator includes: a current generator configured to generate a reference current (Choi, Fig. 1, [0041], ln. 1-3, "The first ramp signal generator 130a may include a first current source Tramp 1 and first variable resistor Rramp1. The second ramp signal generator 130b may include a second current source Iramp2 and a second variable resistor Rramp2."). Choi does not teach a current controller configured to generate a digital-to-analog conversion (DAC) current based on the reference current; a voltage converter configured to generate a bias voltage based on the DAC current; a ramp signal generator configured to generate a ramp signal based on the bias voltage and a switch control signal; and a resistor circuit configured to control loading of the ramp signal generator. However, Kim teaches a current controller configured to generate a digital-to-analog conversion (DAC) current based on the reference current (Kim, pg. 4, para. 4, ln. 1-2, "In the conventional ramp signal generator, the number of unit current cells [I-Cell] is generated by the same current control digital converter [I-DAC] in the conversion step…"); a voltage converter configured to generate a bias voltage based on the DAC current (Kim, pg. 4, para. 4, ln. 2-3, "…the total current of the unit current cells is applied to the first resistor [R_FR]."); a ramp signal generator configured to generate a ramp signal based on the bias voltage and a switch control signal (Kim, pg. 4, para. 4, ln. 3-4, "Then, the first output voltage [A/D ramp signal, V_FR] will be supplied to all columns…"); and a resistor circuit configured to control loading of the ramp signal generator (Kim, pg. 4, para. 4, ln. 4, "…through the column buffer.").
Conclusion
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/STEVEN DANIEL BARRY/Examiner, Art Unit 2638
/LIN YE/Supervisory Patent Examiner, Art Unit 2638
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