Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/07/2025 & 10/10/2025 were filed after the mailing date of the non-final rejection on 06/22/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Regarding Claim 6, it is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 5. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 & 7-12 are rejected under U.S.C. 102(a)(1) as being anticipated by Gomi et al (US 20140139713 A1, hereinafter, "Gomi").
Regarding Claim 1, Gomi teaches a photoelectric conversion apparatus (Gomi, Fig. 1) comprising at least two substrates including: a first substrate including a pixel unit in which a plurality of pixels each including a photoelectric conversion element and an amplification transistor are arranged in an array (Gomi, Fig. 4, [0104], ln. 5-6, "The photoelectric conversion element 101…the first amplifying transistor 105…"); and a second substrate including a memory unit configured to hold an analog signal output by the pixel unit (Gomi, Fig. 4, [0104], ln. 8, "…the analog memory 110…"), wherein a current source, and a transistor connected to a node through which signals output from the current source and the amplification transistor pass are arranged on a substrate different from the first substrate out of the at least two substrates (Gomi, Fig. 4, 106 & 109), and wherein the transistor can switch an operation of resetting a potential of the node, and an operation of clipping a potential of the node (Gomi, [0114], ln. 3, & [0116], ln. 4, "…the analog memories 110 of all the pixels are reset…the clamp capacitor 107 clamps an amplified signal…").
Regarding Claim 7, Gomi teaches the limitations of dependent Claim 1 as noted above. Gomi teaches a pixel included in the pixel unit includes a floating diffusion (Gomi, Fig. 4, 103) configured to convert a charge generated by the photoelectric conversion element into a signal, wherein the amplification transistor includes an amplification transistor (Gomi, Fig. 4, 105) configured to amplify the signal, and wherein the analog signal output by the pixel unit is a signal output by the amplification transistor (Gomi, [0765], ln. 5-7, "…a signal period in which a subject signal which is the pixel signal output from the amplification section in accordance with the signal charge transferred to the accumulation section by the transfer section is output to the signal line.").
Regarding Claim 8, Gomi teaches the limitations of dependent Claim 7 as noted above. Gomi teaches the amplification transistor is a source follower transistor (Gomi, Fig. 4, 105).
Regarding Claim 9, Gomi teaches the limitations of dependent Claim 7 as noted above. Gomi teaches the memory unit includes a plurality of pixel memories arranged in an array, and wherein each of the plurality of pixel memories holds the analog signal output from each of the plurality of pixels (Gomi, Fig. 39, [0375], ln. 1-3, "The pixel signal processing chip vertical scanning circuit 321 controls each of the unit pixel memories 323 within the pixel memory array section 322, and outputs a pixel memory signal of each unit pixel memory 323 to the pixel signal processing chip vertical signal line 325.").
Regarding Claim 10, Gomi teaches the limitations of dependent Claim 9 as noted above. Gomi teaches the first substrate includes a first metal portion and a first insulating film, wherein the second substrate includes a second metal portion and a second insulating film, and wherein, on a bonded surface of the first substrate and the second substrate, a bonded portion of the first metal portion and the second metal portion and a bonded portion of the first insulating film and the second insulating film are arranged (Gomi, Fig. 37, [0365], ln. 1-5, "The chip connection portion 2033 is a connection portion for electrically connecting the pixel chip 2031 and the pixel signal processing chip 2032. In the chip connection portion 2033, a bump or the like created by, for example, an evaporation method or a plating method is used. An insulating member such as an adhesive may be filled in a space existing between the pixel chip 2031 and the pixel signal processing chip 2032.").
Regarding Claim 11, Gomi teaches the limitations of dependent Claim 1 as noted above. Gomi teaches an optical device configured to guide light to the photoelectric conversion apparatus (Gomi, Fig. 1, 201); a control device configured to control the photoelectric conversion apparatus (Gomi, Fig. 1, 207); a processing device configured to process a signal output from the photoelectric conversion apparatus (Gomi, Fig. 1, 203); a display device configured to display information obtained by the photoelectric conversion apparatus (Gomi, Fig. 1, 204); a storage device configured to store information obtained by the photoelectric conversion apparatus (Gomi, Fig. 1, 209); and a mechanical device configured to operate based on information obtained by the photoelectric conversion apparatus (Gomi, [075], ln. 2-4, "The imaging device according to an aspect of the present invention may be an electronic device having an imaging function, and may be a digital video camera, an endoscope or the like besides a digital camera.").
Regarding Claim 12, Gomi teaches the limitations of dependent Claim 1 as noted above. Gomi teaches the photoelectric conversion apparatus according to claim 1 (Gomi, [075], ln. 2-4, "The imaging device according to an aspect of the present invention may be an electronic device having an imaging function, and may be a digital video camera, an endoscope or the like besides a digital camera."); and a control unit configured to control a movement of the movable body using a signal output by the photoelectric conversion apparatus (Gomi, Fig. 1, 208).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Gomi in view of Takemoto (US 20130092820 A1, hereinafter, "Takemoto").
Regarding Claim 2, Gomi teaches the limitations of dependent Claim 1 as noted above. Takemoto teaches the at least two substrates further include a third substrate including a signal processing circuit configured to process an analog signal from the memory unit, wherein the second substrate is arranged between the first substrate and the third substrate, and wherein the current source and the transistor are arranged in the third substrate (Takemoto, Fig. 8, [0111], ln. 6-10, "The first vertical scanning circuit 160, the second vertical scanning circuit 161, the first horizontal scanning circuit 170, the second horizontal scanning circuit 171, the first column-processing circuit 180, the second column-processing circuit 181, the vertical signal line current source 210, and the output amplifiers 230 and 231 are formed in the third substrate 13. The disposition positions of the illustrated circuit constituent elements do not necessarily accord with the actual disposition positions of the circuit constituent elements."). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Takemoto with those of Gomi because it is well known in the art to use three substrates with a processing circuit, current source, and transistor on the third substrate.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Gomi in view of Takemoto and Sakaguchi (WO 2014123029 A1), hereinafter, "Sakaguchi").
Regarding Claim 3, Gomi teaches the limitations of dependent Claim 1 as noted above. Takemoto teaches the at least two substrates further include a third substrate including a signal processing circuit configured to process an analog signal from the memory unit, wherein the second substrate is arranged between the first substrate and the third substrate (Takemoto, Fig. 8, [0109], ln. 4, "…a first substrate 10, a second substrate 11, and a third substrate 13 are stacked."), wherein the second substrate includes a second amplification transistor (Takemoto, Fig. 2, [0068], ln. 7, "…the output amplifiers 230 and 231 are disposed in the second substrate 11."). Takemoto does not teach in the third substrate, a second current source, and a second transistor configured to clip a potential second node through which signals output from the second current source and the second amplification transistor pass are arranged, the second transistor being connected to the second node. However, Sakaguchi teaches in the third substrate (Sakaguchi, Fig. 4 shows the separable circuit on a single substrate. The substrate number is irrelevant. See MPEP 2144.04 para. V, sec. C), a second current source (Sakaguchi, Fig. 4, pg. 5, para. 2, ln. 10, "…a current source 130 [second output]…"), and a second transistor configured to clip a potential (Sakaguchi, Fig. 4, pg. 5, para. 2, ln. 8, "…a clip transistor 265 is provided…") of a second node through which signals output from the second current source and the second amplification transistor (Sakaguchi, Fig. 4, pg. 5, para. 2, ln. 7, "…second amplification transistors 241, 242, 243, 244…") pass are arranged, the second transistor being connected to the second node (Sakaguchi, Fig. 4). It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Takemoto and Sakaguchi with those of Gomi because it is well known in the art to arrange three substrates in a stack and make separable circuits on each substrate.
Allowable Subject Matter
Claims 4 & 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 4, the prior art of record – taken alone or in combination – fails to teach or render obvious drive capability of the second transistor is larger than the drive capability of the transistor.
Regarding Claim 6, it is allowable because it is dependent on Claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN DANIEL BARRY whose telephone number is (571)270-0432. The examiner can normally be reached M-Th 0730-1630.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 517-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN DANIEL BARRY/Examiner, Art Unit 2638
/LIN YE/Supervisory Patent Examiner, Art Unit 2638
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