DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-11, 19-22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Muthiah (US 2020/0301606 A1) hereinafter Muthiah in view of Walsh (US 2019/0324658 A1) hereinafter Walsh.
Regarding claim 1, Muthiah teaches a method by a memory system, comprising:
receiving, at a command queue of the memory system, a second access command based on receiving one or more first access commands (a command latency estimation process receives a command from a host device Paragraph [0045]);
determining an estimated duration for completing the second access command based on a quantity of previously received access commands in the command queue when the second access command is received (estimate latency for executing a command sent from a host device which includes an estimated time to complete the command itself as well as additional latency incurred through tasks not explicitly commanded, but performed during command execution Paragraph [0016] includes the outstanding workload is assessed and incorporated into the latency estimate determined utilizing the workload estimation process Paragraph [0047]); and
transmitting … the estimated duration based on determining the estimated duration for completing the second access command (a total latency estimate is returned to the host device Paragraph [0049]).
Muthiah does not appear to explicitly teach, however, Walsh teaches transmitting a status indicator associated with the estimated duration based on determining the estimated duration for completing the second access command (the command processor predicts the time needed to complete one or more new input/output commands and sends the host latency QoS status information under predetermined conditions or in response to an explicit QoS status request from the host Paragraph [0044]).
Muthiah and Walsh, hereinafter MW, both teach IO command processing, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of MW before the effective filing date of the invention, to modify the teachings of Muthiah by including transmitting a status indicator associated with the estimated duration based on determining the estimated duration for completing the second access command, as taught by Walsh.
One of ordinary skill in the art would have been motivated to include transmitting a status indicator associated with the estimated duration such that the host can utilize the information dynamically adjust the queue depth and prevent oversaturation of the drive (see Paragraphs [0004], [0006] of Walsh).
Regarding claim 2, MW teaches all of the features with respect to claim 1 as outlined above.
Walsh further teaches receiving one or more third access commands based on transmitting the status indicator, wherein a quantity of the one or more third access commands is based on the estimated duration for completing the second access command indicated by the status indicator (the host device may dynamically adjust the data-QD limit of the storage device in response to the QoS feedback by continuing to submit commands to the drive as needed while keeping the data-QD under the current data-QD limit to maintain the desired latency QoS Paragraph [0046], [0050]).
Regarding claim 5, MW teaches all of the features with respect to claim 1 as outlined above.
Muthiah further teaches performing a quantity of the one or more first access commands, wherein the estimated duration is based on a remaining quantity of the previously received access commands (the outstanding (i.e., remaining) workload is assessed and incorporated into the latency estimate determined utilizing the workload estimation process Paragraph [0047]).
Regarding claim 6, MW teaches all of the features with respect to claim 1 as outlined above.
Walsh further teaches receiving one or more memory management operation commands based on transmitting the status indicator; and performing one or more memory management operations based on receiving the one or more memory management operation commands (in response to receiving the latency QoS status from the command processor, the host driver may dynamically adjust the data QD-limit Paragraph [0038]).
Regarding claim 7, MW teaches all of the features with respect to claim 1 as outlined above.
Walsh further teaches updating a value of the status indicator based on performing an access command of the one or more first access commands; and transmitting, for a second time, the status indicator based on updating the value of the status indicator (command processor may automatically send latency QoS status feedback to the host based on the occurrence of one or more predetermined conditions taking place, such as a QD limit being exceeded Paragraph [0045]).
Regarding claim 8, MW teaches all of the features with respect to claim 7 as outlined above.
Walsh further teaches wherein the value of the status indicator is updated at a predefined cadence, based on an expiration of a timer, based on a value of a counter satisfying a threshold, after each access command of the previously received access commands is completed being executed, or any combination thereof (the command processor may automatically send latency QoS status feedback to the host upon the occurrence of one or more predetermined conditions taking place. Such predetermined conditions may include, but are not limited to: a period rate; a specific submission queue QD limit being exceeded; a specific QD limit across a specific set of submission queues, or across all submission queues, being exceeded; a specific data-QD limit for a specific submission queue being exceeded; a specific data-QD limit across a specific set of submission queues, or across all submission queues, being exceeded; a specific threshold of fast fail events being exceeded; a specific threshold of fast fail events being exceeded within a specific period of time; a specific threshold of the average command latency being exceeded; a specific threshold of the processing time of a command being exceeded; a specific threshold of a number of write buffers full being exceeded; and/or a specific threshold of a number of read buffers full being exceeded Paragraph [0045]).
Regarding claim 9, MW teaches all of the features with respect to claim 1 as outlined above.
Walsh further teaches wherein the status indicator is based on a mean duration to complete the previously received access commands, a median duration to complete the previously received access commands, an instantaneous duration to complete the previously received access commands, a maximum duration to complete executing the previously received access commands, a metric associated with one or more memory management operations, a depth of the command queue, or any combination thereof (the QoS status feedback and information can include a variety of factors, such as an indication that a fast fail event has occurred; a value indicating the total number of fast fail events that have occurred, or the number that have occurred since the last reported number, or other variations; a value indicating the number of submitted commands that exceed a specific QD limit or data-QD limit; a value indicating the average command latency per data-DQ unit over the time since the last reported value, or per a fixed time interval; and/or an indication that the average command latency has exceeded a specific threshold Paragraph [0042]).
Regarding claim 10, Muthiah teaches a method by a host device, comprising:
transmitting one or more first access commands (a host device sends a prior workload, which are prior commands either in process or queued for processing in a command queue Paragraph [0029]);
transmitting a second access command based on transmitting the one or more first access commands (the host sends commands to a command latency estimation process based on the prior workload Paragraph [0045]);
receiving, from a memory system, … an estimated duration to complete the second access command (a total latency estimate is returned to the host device Paragraph [0049], wherein estimate latency for executing a command sent from a host device which includes an estimated time to complete the command itself as well as additional latency incurred through tasks not explicitly commanded, but performed during command execution Paragraph [0016]).
Muthiah does not appear to explicitly teach, however, Walsh teaches receiving a status indicator associated with an estimated duration to complete the second access command (the command processor predicts the time needed to complete one or more new input/output commands and sends the host latency QoS status information under predetermined conditions or in response to an explicit QoS status request from the host Paragraph [0044]) and transmitting one or more third access commands based on the estimated duration satisfying a threshold value (the host device may dynamically adjust the data-QD limit of the storage device in response to the QoS feedback by continuing to submit commands to the drive as needed while keeping the data-QD under the current data-QD limit to maintain the desired latency QoS Paragraph [0046], [0050]).
Muthiah and Walsh, hereinafter MW, both teach IO command processing, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of MW before the effective filing date of the invention, to modify the teachings of Muthiah by including transmitting a status indicator associated with the estimated duration based on determining the estimated duration for completing the second access command, as taught by Walsh.
One of ordinary skill in the art would have been motivated to include transmitting a status indicator associated with the estimated duration such that the host can utilize the information dynamically adjust the queue depth and prevent oversaturation of the drive (see Paragraphs [0004], [0006] of Walsh).
Regarding claim 11, MW teaches all of the features with respect to claim 10 as outlined above.
Walsh further teaches further comprising: comparing the estimated duration to the threshold value; and determining that the estimated duration satisfies the threshold value based on comparing the estimated duration to the threshold value (a latency QoS based on the predicted time is compared with a target latency QoS for the storage system Paragraphs [0037], [0052]-[0055]).
Regarding claim 19, MW teaches all of the features with respect to claim 10 as outlined above.
Walsh further teaches requesting an updated status indicator at a predefined cadence, based on an expiration of a timer, based on a value of a counter satisfying a threshold, or any combination thereof (the command processor sends the latency QoS information to the host at predetermined conditions that include a period rate, a QD limit being exceeded, a specific threshold of fast fail rates being exceeded, a specific threshold of the processing time of a command being exceeded Paragraphs [0044]-[0045]).
Regarding claim 20, MW teaches all of the features with respect to claim 10 as outlined above.
Walsh further teaches wherein the status indicator is based on a mean duration to complete the one or more first access commands, a median duration to complete the one or more first access commands, an instantaneous duration to complete the one or more first access commands, a maximum duration to complete the one or more first access commands, a metric associated with one or more memory management operations, a depth of a command queue of the memory system, or any combination thereof (the command processor predicts the time needed to complete each of the one or more IO commands Paragraph [0052] and an QoS status feedback is sent to the host based on the predicted time to complete the commands Paragraph [0048]).
Claim 21 is rejected under 35 U.S.C. 103 for the same reasons as claim 1, as outlined above.
Claim 22 is rejected under 35 U.S.C. 103 for the same reasons as claim 2, as outlined above.
Claim 25 is rejected under 35 U.S.C. 103 for the same reasons as claim 5, as outlined above.
Claim(s) 3, 12 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over MW in further view of Kachare et al. (US 2018/0095675 A1) hereinafter Kachare et al.
Regarding claim 3, MW teaches all of the features with respect to claim 1 as outlined above.
Muthiah does not appear to explicitly teach, however, Karchare et al. teaches receiving a command to abort the second access command based on transmitting the status indicator (based on if an operation takes longer than a latency threshold to complete, the solid state drive may abort the operation Paragraph [0048], [0063]); and receiving a fourth access command corresponding to the second access command based on receiving the command to abort the second access command (the host may then send the same read command to another solid state drive to be processed Paragraph [0063]).
MW and Kachare et al., hereinafter MWK, both teach IO command processing, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of MWK before the effective filing date of the invention, to modify the teachings of MW by including to abort the second access command based on transmitting the status indicator and receiving a fourth access command corresponding to the second access command based on receiving the command to abort the second access command, as taught by Kachare et al.
One of ordinary skill in the art would have been motivated to include to abort the second access command based on transmitting the status indicator and receiving a fourth access command corresponding to the second access command based on receiving the command to abort the second access command to mitigate the effect of a long execution time by transferring the command to another drive, instead of delaying the completion of the command by an exceptionally long time (see [0063]).
Regarding claim 12, MW teaches all of the features with respect to claim 10 as outlined above.
Muthiah does not appear to explicitly teach, however, Karchare et al. teaches transmitting a command to abort the second access command based on determining that the estimated duration fails to satisfy a second threshold value; and transmitting a fourth access command corresponding to the second access command based on transmitting the command to abort the second access command (based on if an operation takes longer than a latency threshold to complete, the solid state drive may abort the operation Paragraph [0048], [0063]. The host may then send the same read command to another solid state drive to be processed Paragraph [0063]).
MW and Kachare et al., hereinafter MWK, both teach IO command processing, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of MWK before the effective filing date of the invention, to modify the teachings of MW by including to abort the second access command based on the estimated duration failing to satisfy a threshold, as taught by Kachare et al.
One of ordinary skill in the art would have been motivated to include to abort the second access command based on the estimated duration failing to satisfy a threshold to mitigate the effect of a long execution time by transferring the command to another drive, instead of delaying the completion of the command by an exceptionally long time (see [0063]).
Claim 23 is rejected under 35 U.S.C. 103 for the same reasons as claim 3, as outlined above.
Claim(s) 4 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over MW in further view of Mirichigni et al. (US 2015/0100744 A1) hereinafter Mirichigni et al.
Regarding claim 4, MW teaches all of the features with respect to claim 1 as outlined above.
MW does not appear to explicitly teach, however, Mirichigni et al. teaches further comprising: storing the status indicator to a register of the memory system (a queue status register 152 stores variable latency information for the plurality of memory access requests as well as for the entire memory access queue Paragraphs [0051]-[0052]) based on determining the estimated duration for completing the second access command (Muthiah teaches the command processor predicts the time needed to complete one or more new input/output commands and transmits latency QoS status information Paragraph [0044]).
MW and Mirichigni et al., hereinafter MWM, both teach IO command processing, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of MWM before the effective filing date of the invention, to modify the teachings of MW by including storing status information in a register, as taught by Mirichigni et al.
One of ordinary skill in the art would have been motivated to include storing the status information in a register so that other system components, such as the host, can the status of the memory access queue Paragraph [0052].
Claim 24 is rejected under 35 U.S.C. 103 for the same reasons as claim 4, as outlined above.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over MW in further view of Wilson et al. (US 2015/0269043 A1) hereinafter Wilson et al.
Regarding claim 16, MW teaches all of the features with respect to claim 10 as outlined above.
MW does not appear to explicitly teach, however, Wilson et al. teaches determining that a third threshold value is satisfied, the third threshold value associated with a timeout condition of the second access command; and transmitting a request for an updated status indicator based on determining that the third threshold value is satisfied (the controller may determine that the storage device has a degraded health status based upon an I/O timeout or an I/O latency that exceeds a latency threshold and identifies a health status change, which is then sent to and stored in a health status registry Paragraph [0046]).
MW and Wilson et al., hereinafter MWW, both teach IO command processing, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of MWW before the effective filing date of the invention, to modify the teachings of MW by updating the status indicator based on determining that a timeout threshold is satisfied, as taught by Wilson et al.
One of ordinary skill in the art would have been motivated to include updating the status indicator based on determining that a timeout threshold is satisfied to maintain accurate health status of its components/devices.
Allowable Subject Matter
Claims 13-15 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, “receiving an updated status indicator associated with an updated estimated duration to complete the second access command; and comparing the updated estimated duration with the estimated duration based on receiving the updated status indicator,” is not taught by the prior art. Claims 14-15 depend upon claim 13 and would be allowable for at least the same reasons as claim 13. The closest prior art is Muthiah and Walsh, and while the Walsh prior art teaches updating a status indicator when the predicted latency has been updated, Walsh is silent with regards to comparing the predicted latency with the previously predicted latency value when the status has changed. Thus, neither Muthiah nor Walsh, individually nor in combination, teaches the entirety of the claim.
Regarding claim 17, “receiving the updated status indicator associated with an updated estimated duration to complete the second access command based on transmitting the request for the updated status indicator; determining that the updated estimated duration is greater than the estimated duration; and refraining from transmitting a command to abort the second access command based on determining that the updated estimated duration is greater than the estimated duration,” is not taught by the prior art. The closest prior art is Muthiah and Walsh, and while the Walsh prior art teaches updating a status indicator when the predicted latency has been updated, Walsh is silent with regards to comparing the predicted latency with the previously predicted latency value when the status has changed, determining that the updated predicted latency is greater than the previously predicted latency and refrain from aborting the command. Thus, neither Muthiah nor Walsh, individually nor in combination, teaches the entirety of the claim.
Regarding claim 18, “receiving the updated status indicator associated with an updated estimated duration to complete the second access command based on transmitting the request for the updated status indicator; determining that the updated estimated duration is less than the estimated duration; and transmitting a command to abort the second access command based on determining that the updated estimated duration is less than the estimated duration,” is not taught by the prior art. The closest prior art is Muthiah and Walsh, and while the Walsh prior art teaches updating a status indicator when the predicted latency has been updated, Walsh is silent with regards to comparing the predicted latency with the previously predicted latency value when the status has changed, determining that the updated predicted latency is less than the previously predicted latency and aborting the access command based on this comparision. Thus, neither Muthiah nor Walsh, individually nor in combination, teaches the entirety of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bennett et al. (US 2008/0091871 A1) teaches in a command to write host data, the host specifies a timeout or write latency designed to accommodate the worst-case situation for completing the command.
Norrie et al. (US 8321627 B1) teaches determining a cumulative latency estimate for I/O requests of a queue and determining whether this estimate is above a latency threshold.
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139
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