DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by this Examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8 May 2025 is in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609. Accordingly, the IDS is being considered by this Examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Per claim 17, the claim has been interpreted under 35 U.S.C. 112(f). Although it does not use the word “means,” it is nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitation (“a routing module”) use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited functions and the generic placeholder is not preceded by a structural modifier. Because this claim limitation is being interpreted under 35 U.S.C. 112(f), it is being interpreted to cover the corresponding structures described in the specification as performing the claimed function, and equivalents thereof. Accordingly, the claimed “routing module” has been interpreted to include the hardware circuitry performing the corresponding unit’s function or a processing unit that executes the algorithm for performing the router module’s functions (as commonly understood by one ordinarily skilled in the art, a router or routing module in the computer arts includes hardware circuitry for receiving and transmitting data and commands over a network. Instant application’s specification discloses in paragraph [0045] that the routing module 111 communicates with memories 120 through an interface and transmits a command input by the external device 200 to memories 120, indicating the routing module is a hardware circuit or a processor programmed for performing the claimed functions). As such, the claim is determined to be compliant with 35 U.S.C 112(a) and 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Per claim 1, line 6, “a command from a plurality of external devices” is indefinite because it is unclear how a single command can be issued by more than one device. If the Applicant intended for the command to be issued by one of the plurality of external devices, then it would be more appropriate to amend the claim accordingly.
Per claim 3, line 4, “the data prefetched” is indefinite as the instant claim recites “data stored in the first storage block is prefetched”, while claim 1 recites “to prefetch data stored in at least one of the plurality of storage blocks”. It is unclear whether these are the same prefetching step, and if not, which prefetched data is “the data prefetched” on line 4.
Per claim 4, lines 5-6, “the command for at least one of the first area or the second area” lacks sufficient antecedent basis.
Per claim 7, lines 3-4, “the command by the first external device” lacks sufficient antecedent basis.
Per claim 11, lines 6-7, “a command … by a plurality of external devices” is indefinite because it is unclear how a single command can be issued by more than one device. If the Applicant intended for the command to be issued by one of the plurality of external devices, then it would be more appropriate to amend the claim accordingly. Line 8, “the at least one of the plurality of storage blocks” is indefinite as lines 4-5 teaches at least one of the plurality of storage blocks in each of a plurality of memories, implying multiple “at least one of the plurality of storage blocks”. Lines 12-13, “the command for the first area” and “the command for the second area” both lack sufficient antecedent basis.
Per claim 14, line 4, “the command by the first external device” lacks sufficient antecedent basis.
Per claim 17, lines 2 and 5, each of “the command by the plurality of external devices” is indefinite for the same reason set forth above for claim 11. Lines 7 and 8, each of “the command” is indefinite, as claim 11 recites “a command” on line 6, “the command for the first area” on line 12 and “the command for the second area” on line 13.
Per claim 18, line 2, “external devices” is indefinite as they are comprised within a computing system, which makes them internal to the computing system. It is unclear what the devices are external in reference to. Line 8, “a command from the plurality of external devices” is indefinite because it is unclear how a single command can be issued by more than one device. If the Applicant intended for the command to be issued by one of the plurality of external devices, then it would be more appropriate to amend the claim accordingly. Line 10, “the plurality of storage blocks” is indefinite as line 5 teaches a plurality of storage blocks in each of a plurality of memories, implying multiple “the plurality of storage blocks”. Line 11, “the command” is indefinite for the same reason set forth above for line 8.
Per claim 20, line 2, “the plurality of storage blocks” is indefinite for the same reason set forth above for claim 18. Lines 5-6, “the command for the first area” and “the command for the second area” both lack sufficient antecedent basis.
All dependent claims are rejected as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-4, 10 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pierson et al. [Pub.No.: US 2020/0117603 A1] (hereinafter “Pierson”).
Independent Claims:
Per independent claim 1, Pierson teaches:
A storage device (see Fig. 1 and paragraph [0052], storage system 100) comprising:
a plurality of memories comprising a plurality of storage blocks (see Fig. 1 and paragraph [0052], external memories 114); and
a switching controller (see Fig. 1-2 and paragraphs [0052]-[0053], MSMC 200) comprising a buffer memory (see Fig. 1, internal memory 112, see Fig. 2, RAM banks 218 and cache tag banks 216; also see paragraphs [0104] and [0116] for L3 cache implemented by RAM banks 218), and configured to communicate with the plurality of memories, to transmit a command from a plurality of external devices to at least one of the plurality of memories (see paragraphs [0053]-0054], [0065], [0080] and [0116], a requested read from a master is received by MSMC 200, and the request read is performed by external memory after missing the cache in MSMC 200), and to prefetch data stored in at least one of the plurality of storage blocks to the buffer memory based on the command for a predetermined period (see paragraph [0088], prefetching memory blocks into cache memory of MSMC implemented by RAM banks 218 based on memory addresses received. Note that the term “predetermined period” does not have a corresponding description in the specification, as such the claim does not specify what constitutes a period or how it is predetermined. Because Pierson teaches in paragraph [0088] that “the next N set of sequential memory blocks” are to be prefetched, then the claimed “predetermined period” can be reasonably interpreted as the operational period during which the next N set of sequential memory blocks are prefetched).
Per independent claim 18, Pierson teaches:
A computing system (see Fig. 1 and paragraph [0052], storage system 100) comprising:
a plurality of external devices (see Fig. 1 and paragraphs [0052]-[0053], masters such as processors 104); and
a storage device (see paragraph [0052], MSMC 110 is considered as a controller that manages the access and sharing of external memories 114, as such MSMC 110 and memory 114 may be construed as a single storage device) comprising a plurality of memories (see Fig. 1 and paragraph [0052], external memories 114) and a switching controller located outside of the plurality of memories (see Fig. 1-2 and paragraphs [0052]-[0053], MSMC 200), and each of the plurality of memories comprises a plurality of storage blocks (the external memories 114 each comprise blocks, see paragraph [0088] for prefetching memory blocks) and the switching controller comprises a buffer memory (see Fig. 1, internal memory 112, see Fig. 2, RAM banks 218 and cache tag banks 216; also see paragraphs [0104] and [0116] for L3 cache implemented by RAM banks 218),
wherein the switching controller is configured to communicate with the plurality of memories, to transmit a command from the plurality of external devices to at least one of the plurality of memories (see paragraphs [0053]-0054], [0065], [0080] and [0116], a requested read from a master is received by MSMC 200, and the request read is performed by external memory after missing the cache in MSMC 200), and to prefetch data stored in at least one of the plurality of storage blocks to the buffer memory based on the command for a predetermined period (see paragraph [0088], prefetching memory blocks into cache memory of MSMC implemented by RAM banks 218 based on memory addresses received. Note that the term “predetermined period” does not have a corresponding description in the specification, as such the claim does not specify what constitutes a period or how it is predetermined. Because Pierson teaches in paragraph [0088] that “the next N set of sequential memory blocks” are to be prefetched, then the claimed “predetermined period” can be reasonably interpreted as the operational period during which the next N set of sequential memory blocks are prefetched).
Dependent Claims:
Per claim 2, Pierson further teaches each of the plurality of storage blocks included in each of the plurality of memories is allocated for one or more of the plurality of external devices (see paragraph [0052], the processors 104 share the external memories 114 and each block of external memories 114 can be read or written to by a processor 104. As such each block is considered to be allocated for at least one processor 104), and the buffer memory is accessible by all of the plurality of external devices (see paragraph [0052], the MSMC internal memory 112 is shared by processors 104).
Per claim 3, Pierson further teaches a first storage block is allocated for a first external device, data stored in the first storage block is prefetched in the buffer memory (one of the prefetched N blocks is construed as the claimed first storage block), and a second external device is accessible to the data prefetched in the buffer memory (see paragraph [0052], the MSMC internal memory 112 is shared by processors 104).
Per claim 4, Pierson further teaches the at least one of the plurality of storage blocks comprises a first area allocated for a first external device and a second area allocated for a second external device (see paragraph [0052], the processors 104 share the external memories 114, as such a block that is read or written to by a processor 104 is considered to be allocated for that processor 104. Any two different blocks of memories 114 accessed by two different processors 104 may be viewed as the claimed first and second areas), and data stored in the first area and data stored in the second area are prefetched in the buffer memory based on the command for at least one of the first area or the second area (see paragraph [0088], any two different blocks of memories 114 accessed by two different processors 104 that are also included in the N blocks to be prefetched due to accesses by the two different processors 104).
Per claim 10, Pierson further teaches the switching controller is located outside of the plurality of memories (see Fig. 1, MSMC 110 is outside of external memories 114).
Per claim 19, Pierson further teaches each of the plurality of storage blocks included in each of the plurality of memories is allocated for one or more of the plurality of external devices (see paragraph [0052], the processors 104 share the external memories 114 and each block of external memories 114 can be read or written to by a processor 104. As such each block is considered to be allocated for at least one processor 104), and the buffer memory is accessible by all of the plurality of external devices (see paragraph [0052], the MSMC internal memory 112 is shared by processors 104).
Per claim 20, Pierson further teaches the at least one of the plurality of storage blocks includes a first area allocated for a first external device and a second area allocated for a second external device (see paragraph [0052], the processors 104 share the external memories 114, as such a block that is read or written to by a processor 104 is considered to be allocated for that processor 104. Any two different blocks of memories 114 accessed by two different processors 104 may be viewed as the claimed first and second areas), and data stored in the first area and data stored in the second area are prefetched in the buffer memory based on at least one of the command for the first area or the command for the second area (see paragraph [0088], any two different blocks of memories 114 accessed by two different processors 104 that are also included in the N blocks to be prefetched due to accesses by the two different processors 104).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7, 9, 11-14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson, and further in view of Guim Bernat et al. [Pub.No.: US 20190042437 A1] (hereinafter “Guim Bernat”).
Per claim 5, Pierson does not specifically teach the data stored in the first area is prefetched in the buffer memory with the data stored in the second area based on an access frequency or a read request frequency for the second area. However, Pierson teaches prefetching based on detected sequential access pattern in paragraph [0088], and an analogous prior art reference Guim Bernat further teaches prefetching based on access frequency (see Guim Bernat, paragraph [0020], last five lines). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to combine Pierson with Guim Bernat to prefetch data based on access frequency to improve performance (the claimed second area), and further prefetch data that is falls within a sequential pattern (the claimed first area) with the already prefetched data to further improve performance.
Per claim 6, following the rationale set forth above for claim 5, the combined teaching of Pierson and Guim Bernat further render obvious: the access frequency or the read request frequency for the second area is equal to or greater than a preset reference value (see Guim Bernat, paragraph [0020], last five lines, the claimed second area is a memory area or block with access rate equal to or greater than a threshold), and an access frequency or a read request frequency for the first area is less than the preset reference value (the claimed first area is a memory area or block with access rate less than the threshold but forms a sequential access pattern with the claimed second block).
Per claim 7, Pierson further teaches the switching controller provides the data prefetched from the first area in the buffer memory to the first external device according to the command by the first external device (the prefetched cache is provided to a processor 104 if a request by that processor hits the cache, see paragraphs [0104]-[0107]).
Per claim 9, applying the same rationale for combining the teachings of Pierson and Guim Bernat as set forth above for claim 5, the combined teachings of Pierson with Guim Bernat render obvious: the switching controller determines, based on an access frequency or a read request frequency for the first area is equal to or greater than a preset reference value, or whether an access frequency or a read request frequency for
the second area is equal to or greater than the preset reference value, whether to prefetch the data in the first area and the data in the second area, in the buffer memory (see Guim Bernat, paragraph [0020], last five lines for prefetching based on access rate).
Per independent claim 11, Pierson teaches:
A switching controller (see Fig. 1-2 and paragraphs [0052]-[0053], MSMC 200) comprising:
at least one buffer memory (see Fig. 1, internal memory 112, see Fig. 2, RAM banks 218 and cache tag banks 216; also see paragraphs [0104] and [0116] for L3 cache implemented by RAM banks 218); and
a buffer memory control module (see Fig. 4, prefetch controller 416) configured to select data stored in at least one of a plurality of storage blocks and to prefetch the selected data into the at least one buffer memory, based on a command for a predetermined period by a plurality of external devices (see paragraph [0088], prefetching memory blocks into cache memory of MSMC implemented by RAM banks 218 based on memory addresses received. Note that the term “predetermined period” does not have a corresponding description in the specification, as such the claim does not specify what constitutes a period or how it is predetermined. Because Pierson teaches in paragraph [0088] that “the next N set of sequential memory blocks” are to be prefetched, then the claimed “predetermined period” can be reasonably interpreted as the operational period during which the next N set of sequential memory blocks are prefetched), and
wherein the at least one of the plurality of storage blocks includes a first area allocated for a first external device and a second area allocated for a second external device (see paragraph [0052], the processors 104 share the external memories 114, as such an area that is written to by a processor 104 is considered to be allocated for that processor 104), and data stored in the first area and data stored in the second area are prefetched in the at least one buffer memory based on at least one of the command for the first area or the command for the second area (each of the first and second areas/blocks may be prefetched if they form a sequential access pattern with another block that is accessed by a processor 104, see Pierson, paragraph [0088]).
Pierson fail to teach or render obvious selecting at least one of a plurality of storage blocks included in each of a plurality of memories to prefetch into the buffer memory.
Guim Bernat teaches prefetching based on access frequency exceeding a threshold (see Guim Bernat, paragraph [0020], last five lines). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to combine Pierson with Guim Bernat to prefetch more frequently accessed data (hot data) to improve performance. Based on this rationale, it would be further obvious that any block of each memory may be prefetched if that block is accessed frequently with an access rate exceeding a certain threshold depending on data access demands. Therefore, the combined teachings of Pierson and Guim Bernat render obvious “selecting at least one of a plurality of storage blocks included in each of a plurality of memories to prefetch into the buffer memory”.
Per claim 12, the switching controller performs the same functional steps in claim 5. As such the instant claim rejected on the same ground as claim 5.
Per claim 13, the switching controller performs the same functional steps in claim 6. As such the instant claim rejected on the same ground as claim 6.
Per claim 14, the switching controller performs the same functional steps in claim 7. As such the instant claim rejected on the same ground as claim 7.
Per claim 16, the switching controller performs the same functional steps in claim 9. As such the instant claim rejected on the same ground as claim 9.
Per claim 17, Pierson further teaches the switching controller of claim 11, further comprising:
a routing module (see Fig. 2 for components responsible for interfacing with masters and external memories, such as CBA 4 SOC switch 208, arbitration and data path 204, external memory interleave 220; also see Fig. 4 for MSMC bridge) configured to transmit the command by the plurality of external devices to the plurality of memories or the at least one buffer memory (see paragraphs [0053]-0054], [0065], [0080] and [0116], a requested read from a master is received by MSMC 200, and the request read is performed by external memory after missing the cache in MSMC 200, or performed in the cache after a cache hit, see paragraphs [0104]-[0107]), and
wherein the routing module transmits the command by one of the plurality of external devices to the at least one buffer memory, and if data corresponding to the command is stored in the at least one buffer memory, the data corresponding to the command and stored in the at least one buffer memory is transmitted to the one of the plurality of external devices through the routing module (a cache hit in the MSMC cache implemented by RAM banks 218 results in the requested data being returned to the requesting processor 104, see paragraphs [0104]-[0107]).
Potential Allowable Subject Matter
Claims 8 and 15 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of potential allowable subject matter:
Per claim 8, the combined teachings of Pierson and Guim Bernat render obvious prefetching the data in the at least one of the plurality of storage blocks in the buffer memory based on access frequency as set forth above in the rejection of claim 5. However, the cited prior art references fail to teach or render obvious that the prefetching is based on the switching controller determining a sum of at least one of an access frequency or a read request frequency for the first area and at least one of an access frequency or a read request frequency for the second area.
Per claim 15, the claim is potentially allowable for the same reason set forth above for claim 8 (claim 15’s buffer memory control module performs the same function as claim 8’s switching controller).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN X GU whose telephone number is (571)272-0703. The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN X GU/
Primary Examiner
Art Unit 2138
25 June 2026
Prosecution Insights