DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been presented and pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1-2;
The similar unclarity nature discussed below for a claim 8 relating to who or what performs the claimed functions/steps/operations are similarly applied.
In claim 8;
In line 4, it is unclear & unstated as to who or what performs “receiving” step function; in addition, it is unclear as to who or what sends the instruction.
In line 5, it is unclear & unstated as to who or what supports the “mounting of a second PCIe device to a second server”; it is further unclear as to who or what supports mounting of a first device/server (i.e., does a human performs the mounting? If so, how does the human perform the receiving step? Claiming a second device/server without the first device/server causes confusion in the claimed invention).
In claim 9;
In line 3, the phrase “second device needs to be allocated” lacks proper and clear antecedent basis
In claim 11;
In line 2, the phrase “first instruction received from a first serve” lacks functional antecedent basis (i.e., the claimed invention is confusing as how and whether operational recitations with respect to a first server” interacting with the second device/server; in addition, it is unclear and unsupported as whether the first & second server are connected to the management device).
In claim 12;
In line 2, it is unclear and unstated as to who or what performs “hot-unplug operation (i.e., who actually performs/supports the claimed unplugging function?).
In claim 13;
In line 3, the phrase “correspondence between the second PCIe device and the first server” lacks proper functional antecedent basis.
In claim 14;
The correspondence between the “at least one PCIE device connected to the management device and at least one server connected to the transfer circuit” lacks proper and functional antecedent basis (i.e., what is the functional, operational and/or structural correspondences between the PCIe device and/or the server of the claims 8 and claim 14?).
In claim 17;
In line 13-14, the phrase “server” lacks proper and clear antecedent basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bass et al. (US 2015/0234768 A1).
Examiner notes that, before discussing the claimed rejection details, the recited functions of resources releasement & establishment performed by hot swapping (i.e., function of replacing, adding, removing computer system components such as the claimed PCIe device) are well-known in the art of claimed system such as configuration of system. The examiner takes official notice on such well-known establishment of art of the teachings of the resources releasement & establishment (i.e., abundant support can be found on US Patent Database).
The examiner relies on the entire teachings of the Bass reference for this rejection; hence, the examiner advises the applicant to carefully consider the entire teachings of the Bass reference to better understand the examiner’s position and interpretations applied to the claimed invention. In addition, the examiner further advises the applicant to carefully consider the prior art of record cited by the examiner that teaches and supports the teachings of the well-known teachings that are commonly practiced in the art/industry.
The Bass reference teaches, when the examiner applies Broadest Reasonable Interpretations, functionally equivalent limitations/recitations of the claimed invention, as follows:
CLAIMS 1-20
Bass REF TEACNINGS
1.A peripheral component interconnect express (PCIe) device management method, applied to a management device, wherein the management device comprises a transfer circuit, a hot-swap control circuit, and a PCIe configuration circuit, and the method comprises:
Fig 1 with accompanying description
receiving a resource release instruction, wherein the resource release instruction is configured to direct release of resources of a first PCIe device mounted on a first server; based on the resource release instruction, controlling, by the hot-swap control circuit, the transfer circuit to perform a hot-unplug operation with the first server; and
Par 23, “Hot remove function 130 operates to hot remove…After receiving a single indication…hot remove function 130 may cause the operating system of server 20, each of HPC 150A-150C, and other necessary software and/or hardware components to hot remove PCIe cards located on PCIe slots 160A-160C…remove function 130 has caused all cards to be put into a reset state, hot remove function 130 may also cause the power to be removed…”…par 24, I/O module 30 may be a module component configured to attach to server 20”; par 34, “request for host removal to a register accessible by the OS of server 20”; & par 36, “server 20 will stop applicable device driver to the PCIe adapter located in the respective slot of PCIe slots”
controlling, by the hot-swap control circuit, the PCIe configuration circuit to release the resources of the first PCIe device, wherein resource release represents termination of a correspondence between the first PCIe device and the first server.
par 36, “server 20 will stop applicable device driver to the PCIe adapter located in the respective slot of PCIe slots…the respective HPC of HPCs 150A-150C to turn off power to the respective PCI slot of PCIe slots 160A-160C”; par 37, “an FPGA…asserts a signal preventing the OS of server 20 from seeing, or otherwise recognizing, the respective PCIe adapter…”
2. The method according to claim 1, wherein after the hot-swap control circuit controls the PCIe configuration circuit to release the resources of the first PCIe device, the method further comprises:
par 36, “server 20 will stop applicable device driver to the PCIe adapter located in the respective slot of PCIe slots…the respective HPC of HPCs 150A-150C to turn off power to the respective PCI slot of PCIe slots 160A-160C”; par 37, “an FPGA…asserts a signal preventing the OS of server 20 from seeing, or otherwise recognizing, the respective PCIe adapter…”
receiving a resource allocation instruction, wherein the resource allocation instruction directs mounting of the first PCIe device on a second server;
par 29, “receiving the indication,…generate a hot add event for each respective PCIe slot of PCIe slots…server” (examiner notes that having more than one server for connecting PCIe device is abundantly well-known practices in the industry, especially for simply hot plugging purposes/functions)
based on the resource allocation instruction, controlling, by the hot-swap control circuit, the transfer circuit and the second server to perform a hot-plug operation; and
par 22, “After receiving a signal indication…hot add function 120 may cause each of PCI slots 160A-160C, and associate PCIe cards, within PCIe slots 160A-160C, to be hot added…”
controlling, by the hot-swap control circuit, the PCIe configuration circuit to allocate the resources of the first PCIe device, wherein resource allocation represents establishment of a correspondence between the first PCIe device and the second server.
Par 29, instructions configure and load application drivers for devices on each respective slot of PCIe slots 160A-160C…may perform steps associated with the hot add event…to the operating system (OS) of server 20”
3. The method according to claim 1, wherein the management device further comprises management software, and the hot-swap control circuit controlling the PCIe configuration circuit to release the resources of the first PCIe device further comprises: notifying the management software that the first server has completed the hot-unplug operation; and terminating, by the management software, the correspondence between the first PCIe device and the first server in the PCIe configuration circuit.
Obvious functional step from the teachings of par 36, “server 20 will stop applicable device driver to the PCIe adapter located in the respective slot of PCIe slots…the respective HPC of HPCs 150A-150C to turn off power to the respective PCI slot of PCIe slots 160A-160C”; par 37, “an FPGA…asserts a signal preventing the OS of server 20 from seeing, or otherwise recognizing, the respective PCIe adapter…”
4. The method according to claim 1, wherein the PCIe configuration circuit maintains a correspondence between at least one PCIe device connected to the management device and at least one server connected to the transfer circuit.
Obvious from the teachings of Par 35, “OS of server 20 will retrieve one request for hot removal at a time…”
5. The method according to claim 1, wherein the management device further comprises a power supply, and the method further comprises: supplying, by the power supply, power to the first PCIe device.
Par 36, “PCIe adapter in any of PCIe slots 160A-160C that has the power enabled”
6. The method according to claim 1, wherein the management device further comprises a heat dissipation unit, at the method further comprises: dissipating, by the heat dissipation unit, heat from the first PCIe device.
This is not taught by Bass, but well-known and/or common practices in the industry, the examiner advises the applicant to search the US Patent Database to verify the common practices
7. The method according to claim 1, wherein when the hot-swap control circuit controls the transfer circuit to perform the hot-unplug operation with the first server, a slot of the first PCIe device remains powered on.
This is not taught by Bass, but well-known and/or common practices in the industry, the examiner advises the applicant to search the US Patent Database to verify the common practices; in addition, this is also obvious variations of functions for the teachings of: Par 36, “PCIe adapter in any of PCIe slots 160A-160C that has the power enabled” & Obvious from the above teachings of Par 35, “OS of server 20 will retrieve one request for hot removal at a time…” (having power on or off is an applicational choices for the designer that can be easily chosen without adding an inventive concept)
8. A peripheral component interconnect express (PCIe) device management method, applied to a management device, wherein the management device comprises a transfer circuit, a hot-swap control circuit, and a PCIe configuration circuit, and the method comprises: receiving a resource allocation instruction, wherein the resource allocation instruction directs mounting of a second PCIe device to a second server; and controlling, by the hot-swap control circuit, the PCIe configuration circuit to allocate resources of the second PCIe device, wherein the resource allocation represents an establishment of a correspondence between the second PCIe device and the second server.
The teachings of the claim 2 are similarly applied
9. The method according to claim 8, wherein the management device further comprises management software, and the method further comprises: determining, by the management software, the second server to which the second PCIe device needs to be allocated
par 29, “receiving the indication,…generate a hot add event for each respective PCIe slot of PCIe slots…server”
sending, by the management software, the resource allocation instruction to the hot-swap control circuit.
par 22, “After receiving a signal indication…hot add function 120 may cause each of PCI slots 160A-160C, and associate PCIe cards, within PCIe slots 160A-160C, to be hot added…”
10. The method according to claim 9, wherein before the determining, by the management software, the second server to which the second PCIe device needs to be allocated, the method further comprises: sending, by the management software, a resource release instruction to the hot-swap control circuit, to release the second PCI device.
par 36, “server 20 will stop applicable device driver to the PCIe adapter located in the respective slot of PCIe slots…the respective HPC of HPCs 150A-150C to turn off power to the respective PCI slot of PCIe slots 160A-160C”; par 37, “an FPGA…asserts a signal preventing the OS of server 20 from seeing, or otherwise recognizing, the respective PCIe adapter…”
11. The method according to claim 10, wherein the management software sends the resource release instruction based on a first instruction received from a first server.
Par 23, “Hot remove function 130 operates to hot remove…After receiving a single indication…hot remove function 130 may cause the operating system of server 20, each of HPC 150A-150C, and other necessary software and/or hardware components to hot remove PCIe cards located on PCIe slots 160A-160C…remove function 130 has caused all cards to be put into a reset state, hot remove function 130 may also cause the power to be removed…”…par 24, I/O module 30 may be a module component configured to attach to server 20”; par 34, “request for host removal to a register accessible by the OS of server 20”; & par 36, “server 20 will stop applicable device driver to the PCIe adapter located in the respective slot of PCIe slots”
12. The method according to claim 10, wherein the method further comprises: controlling, by the hot-swap circuit, the transfer circuit to perform a hot-unplug operation with a first server based on the resource release instruction.
Par 23, “Hot remove function 130 operates to hot remove…After receiving a single indication…hot remove function 130 may cause the operating system of server 20, each of HPC 150A-150C, and other necessary software and/or hardware components to hot remove PCIe cards located on PCIe slots 160A-160C…remove function 130 has caused all cards to be put into a reset state, hot remove function 130 may also cause the power to be removed…”…par 24, I/O module 30 may be a module component configured to attach to server 20”; par 34, “request for host removal to a register accessible by the OS of server 20”; & par 36, “server 20 will stop applicable device driver to the PCIe adapter located in the respective slot of PCIe slots”
13. The method according to claim 12, wherein the hot-swap control circuit controls the PCIe configuration circuit to release the resources of the second PCIe device and wherein resource release represents termination of a correspondence between the second PCIe device and the first server.
par 36, “server 20 will stop applicable device driver to the PCIe adapter located in the respective slot of PCIe slots…the respective HPC of HPCs 150A-150C to turn off power to the respective PCI slot of PCIe slots 160A-160C”; par 37, “an FPGA…asserts a signal preventing the OS of server 20 from seeing, or otherwise recognizing, the respective PCIe adapter…”
14. The method according to claim 8, wherein the PCIe configuration circuit maintains a correspondence between at least one PCIe device connected to the management device and at least one server connected to the transfer circuit.
The teachings of the claim 4 are similarly applied
15. The method according to claim 8, wherein the management device further comprises a power supply, and the method further comprises: supplying, by the power supply, power to the second PCIe device.
The teachings of the claim 5 are similarly applied
16. The method according to claim 8, wherein the management device further comprises a heat dissipation unit, at the method further comprises: dissipating, by the heat dissipation unit, heat from the second PCIe device.
The teachings of the claim 6 are similarly applied
17. A management device, comprising a transfer circuit, a hot-swap control circuit, and a peripheral component interconnect express (PCIe) configuration circuit, wherein the management device is connected to at least one server through the transfer circuit, wherein the transfer circuit is connected to the hot-swap control circuit, and the hot-swap control circuit is connected to the PCIe configuration circuit; the hot-swap control circuit receives a resource release instruction or a resource allocation instruction, and based on the resource release instruction or the resource allocation instruction, controls the transfer circuit and the PCIe configuration circuit, wherein the resource release instruction directs release of resources of a PCIe device mounted on a server, and the resource allocation instruction directs mounting of the PCIe device to a designated server; and the PCIe configuration circuit performs resource release or resource allocation of the PCIe device, wherein resource release represents terminating a correspondence between the PCIe device and the server, and resource allocation represents establishing a correspondence between the PCIe device and the server.
The teachings of the claims 1 with 2 are similarly applied
18. The management device according to claim 17, wherein the management device further comprises a power supply powering the PCIe device.
The teachings of the claim 5 are similarly applied
19. The method according to claim 8, wherein the management device further comprises a heat dissipation unit.
The teachings of the claim 6 are similarly applied
20. A server, connected to at least one peripheral component interconnect express (PCIe) device through the management device of claim 17.
The examiner notes that the Bass reference does not expressly or identically disclose the labeling of the claimed “management device comprises a transfer circuit, a hot-swap control circuit, and a PCIe configuration”; however, the Bass reference does teach the functional equivalences of such not expressly disclosed labeling of the claimed limitations (i.e., the figure 1 with accompanying description of the following combined teachings of: SERVER 20, MULTIPLE SLOT HOT PLUG PROGRAM 110, HOT ADD FUNCTION 120, HOT REMOVE FUNCTION 130, ROOT COMPLEX 135, ROOT PPORTs 140 A-C, HPC 150A-C, POIE SLOT 160A-C, I/O MODULE 30, ATTEMTION BUTTON 170, INDICATOR(S) 180, MRL 190 & OS of the SERVER 20), as discussed in detailed above. Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the teachings of the Bass reference for the detailed teachings and reasons discussed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181
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