Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 28 July 2025 for application number 19/202,854. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claim 1 is canceled.
Claims 2 – 21 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 12 September 2022 (CON 17/931,416).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10 September 2025 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2 – 16 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 17 of U.S. Patent No. 12,314,566. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the conflicting application disclose the limitations required of the claims in the instant application.
Claims 2 – 16 and 21 of the instant application are compared to claims 1 – 17 of U.S. Patent No. 12,314,566 in the following table:
Instant Application
U.S. Patent No. 12,314,566
A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
read data from a first page of a virtual block of the one or more memory devices;
determine that the data read from the first page of the virtual block comprises one or more errors, wherein the one or more errors of a second page are associated with a shift in a threshold voltage of one or more memory cells of the second page, wherein the shift in the threshold voltage is in accordance with reading the data from the first page;
determine that data stored to a plurality of pages of the virtual block comprises one or more errors in accordance with determining that the data read from the first page of the virtual block comprises one or more errors;
postpone refreshing the plurality of pages of the virtual block in accordance with a quantity of the plurality of pages satisfying a threshold quantity of pages; and
refresh a second page of the virtual block in accordance with postponing refreshing the plurality of pages of the virtual block. (claim 2)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
refresh the first page of the virtual block in accordance with determining that the
data stored to the first page of the virtual block comprises one or more errors. (claim 3)
The memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to:
determine that the one or more errors associated with the data stored to the first page of the virtual block satisfies a first threshold, wherein refreshing the first page of the virtual block is in accordance with determining that one or more errors associated with the first page of the virtual block satisfies the first threshold. (claim 4)
The memory system of claim 4, wherein the first threshold is associated with a bit error rate, a quantity of errors, or both. (claim 5)
The memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to:
determine that a quantity of access operations performed on the first page of the virtual block satisfies a second threshold, wherein refreshing the first page of the virtual block is in accordance with determining that the quantity of access operations performed on the first page of the virtual block satisfies the second threshold. (claim 6)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
refresh, after postponing refreshing the plurality of pages of the virtual block, the plurality of pages of the virtual block. (claim 7)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
read a value stored to a component of the one or more memory devices, wherein the value indicates whether the data stored to the second page of the virtual block comprises one or more errors. (claim 8)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
read the data from the second page of the virtual block in accordance with determining that the data read from the second page of the virtual block comprises one or more errors; and
write the data associated with the second page of the virtual block to a third page of a second virtual block. (claim 9)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
refrain from refreshing a third page of the virtual block in accordance with determining that data stored to the third page of the virtual block does not comprise one or more errors. (claim 10)
The memory system of claim 2, wherein:
the first page is adjacent to the second page. (claim 11)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a third page of the virtual block comprises one or more errors; and
refresh the third page of the virtual block in accordance with determining that the data stored to the third page of the virtual block comprises one or more errors. (claim 12)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a fourth page of the virtual block comprises a bit error rate that satisfies a third threshold; and
refresh the fourth page of the virtual block in accordance with determining that the bit error rate satisfies the third threshold. (claim 13)
The memory system of claim 13, wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a fifth page of the virtual block comprises a bit error rate that does not satisfy the third threshold; and
refrain from refreshing the fifth page of the virtual block in accordance with determining that the bit error rate of the fifth page of the virtual block does not satisfy the third threshold. (claim 14)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
read the data from the second page of the virtual block in accordance with determining that the data read from the first page of the virtual block comprises one or more errors; and
determine that the data stored to the second page of the virtual block comprises one or more errors in accordance with reading the data from the second page of the virtual block. (claim 15)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
determine that the data read from the first page of the virtual block comprises one or more errors in accordance with reading the data from the first page; and
determine that the data stored to the second page of the virtual block comprises one or more errors in accordance with determining that the data read from the first page of the virtual block comprises one or more errors. (claim 16)
A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:
read data from a first page of a virtual block of one or more memory devices;
determine that the data read from the first page of the virtual block comprises one or more errors, wherein the one or more errors of a second page are associated with a shift in a threshold voltage of one or more memory cells of the second page, wherein the shift in the threshold voltage is in accordance with reading the data from the first page;
determine that data stored to a plurality of pages of the virtual block comprises one or more errors in accordance with determining that the data read from the first page of the virtual block comprises one or more errors;
postpone refreshing the plurality of pages of the virtual block in accordance with a quantity of the plurality of pages satisfying a threshold quantity of pages; and
refresh a second page of the virtual block in accordance with postponing refreshing the plurality of pages of the virtual block. (claim 21)
A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
read data from a first page of a virtual block of the one or more memory devices, wherein the virtual block comprises a plurality of pages that comprises the first page and a second page;
determine whether data stored to the second page of the virtual block comprises one or more errors based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors, wherein the one or more errors of a second page are associated with a shift in a threshold voltage of one or more memory cells of the second page, wherein the shift in the threshold voltage is in accordance with reading the data from the first page;
determine that data stored to the plurality of pages of the virtual block comprises one or more errors based at least in part on determining that the data stored to the second page of the virtual block comprises one or more errors, wherein the plurality of pages comprises the second page;
postpone refreshing the plurality of pages of the virtual block based at least in part on a quantity of the plurality of pages satisfying a threshold quantity of pages; and
refresh a second page of the virtual block in accordance with postponing refreshing the plurality of pages of the virtual block. (claim 1)
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
refresh the first page of the virtual block in accordance with determining that the
data stored to the first page of the virtual block comprises one or more errors. (claim 2)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
determine that the one or more errors associated with the data stored to the first page of the virtual block satisfies a first threshold, wherein refreshing the first page of the virtual block is in accordance with determining that one or more errors associated with the first page of the virtual block satisfies the first threshold. (claim 3)
The memory system of claim 3, wherein the first threshold is associated with a bit error rate, a quantity of errors, or both. (claim 4)
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
determine that a quantity of access operations performed on the first page of the virtual block satisfies a second threshold, wherein refreshing the first page of the virtual block is in accordance with determining that the quantity of access operations performed on the first page of the virtual block satisfies the second threshold. (claim 5)
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
refresh, after postponing refreshing the plurality of pages of the virtual block, the plurality of pages of the virtual block. (claim 6)
The memory system of claim 1, wherein determining whether data stored to the second page of the virtual block comprises one or more errors comprises the processing circuitry is further configured to cause the memory system to:
read a value stored to a component of the one or more memory devices, wherein the value indicates whether the data stored to the second page of the virtual block comprises one or more errors. (claim 7)
The memory system of claim 1, wherein determining whether data stored to the second page of the virtual block comprises one or more errors comprises the processing circuitry is further configured to cause the memory system to:
read the data from the second page of the virtual block in accordance with determining that the data read from the second page of the virtual block comprises one or more errors; and
write the data associated with the second page of the virtual block to a third page of a second virtual block. (claim 8)
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
refrain from refreshing a third page of the virtual block in accordance with determining that data stored to the third page of the virtual block does not comprise one or more errors. (claim 9)
The memory system of claim 1, wherein:
the first page is adjacent to the second page. (claim 10)
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a third page of the virtual block comprises one or more errors based on at least determining that the data read from the second page of the virtual block comprises one or more errors; and
refresh the third page of the virtual block based at least in part on determining that the data stored to the third page of the virtual block comprises one or more errors. (claim 11)
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a fourth page of the virtual block comprises a bit error rate that satisfies a third threshold; and
refresh the fourth page of the virtual block in accordance with determining that the bit error rate satisfies the third threshold. (claim 12)
The memory system of claim 12, wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a fifth page of the virtual block comprises a bit error rate that does not satisfy the third threshold; and
refrain from refreshing the fifth page of the virtual block in accordance with determining that the bit error rate of the fifth page of the virtual block does not satisfy the third threshold. (claim 13)
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
read the data from the second page of the virtual block in accordance with determining that the data read from the first page of the virtual block comprises one or more errors, wherein determining whether the data stored to the second page of the virtual block comprises one or more errors is based at least in part on reading the data from the second page of the virtual block. (claim 14)
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
determine that the data read from the first page of the virtual block comprises one or more errors based at least in part on reading the data from the first page, wherein determining whether the data stored to the second page of the virtual block comprises one or more errors is based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors. (claim 15)
A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:
read data from a first page of a virtual block of one or more memory devices, wherein the virtual block comprises a plurality of pages that comprises the first page and a second page;
determine whether data stored to the second page of the virtual block comprises one or more errors based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors, wherein the one or more errors of a second page are associated with a shift in a threshold voltage of one or more memory cells of the second page, wherein the shift in the threshold voltage is in accordance with reading the data from the first page;
determine that data stored to the plurality of pages of the virtual block comprises one or more errors based at least in part on determining that the data stored to the second page of the virtual block comprises one or more errors, wherein the plurality of pages comprises the second page;
postpone refreshing the plurality of pages of the virtual block based at least in part on a quantity of the plurality of pages satisfying a threshold quantity of pages; and
refresh a second page of the virtual block in accordance with postponing refreshing the plurality of pages of the virtual block. (claim 16)
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 17 – 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 17 recites in the last two limitations “setting an initial page index to a first value in accordance with determining that the quantity of errors satisfies the first threshold…” It is unclear what value the initial page index is set to in accordance with the determined satisfied error threshold. It is unclear if the initial page index value is set to the quantity of errors, first threshold, or another value. Claims 18 – 20 depend from claim 17 and are rejected based upon their dependency.
Claim 17 recites in the last two limitations “setting an initial page index to a first value in accordance with determining that the quantity of errors satisfies the first threshold; and
refresh a second page of the virtual block in accordance with setting the initial page index to the first value, wherein the first page is adjacent to the second page.” It is unclear if refreshing occurs immediately when the initial page index is set to the first value, or it occurs later. Claims 18 – 20 depend from claim 17 and are rejected based upon their dependency.
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 2 – 21 have received a first action on the merits and are subject of a first action non-final. Claims 2 – 16 and 21 are rejected under a Double Patenting rejection. Claims 17 – 20 are rejected under a 112 rejection.
Allowable Subject Matter
Claims 2 – 21 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) and Double Patenting rejection set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: for independent claims 2 and 21 the prior art of record, neither anticipates, nor renders obvious postponing the refreshing of a plurality of pages of a virtual block based on the number of pages satisfying a threshold number of pages to be refreshed. Claims 2 – 16 depends from claim 1 and would be allowable based upon their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for independent claim 17 the prior art of record, neither anticipates, nor renders obvious setting an initial page index to a first value based on determining that the number of errors from a data read from a first page of a virtual block satisfies a first threshold, and refreshing a second page that is adjacent to a first page of the virtual block based on setting the initial page index to the first value. Claims 18 – 20 depends from claim 17 and would be allowable based upon their dependency.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Venkitachalam et al., US Pub. No. 2014/0029336 A1 – teaches “Each read point error count may correspond to a particular logical page of the multiple logical pages and each read point error may be determined based on page data associated with one or more other logical pages of the multiple logical pages.” [para. 0043]
Hyun et al., US Pub. No. 2015/0193299 A1 – teaches “embodiments where the refresh module 304 is configured to refresh data on a page by page basis, and a physical or logical page comprises multiple ECC code words or chunks, the refresh module 304 and/or the data factor module 322 may read and/or decode a subset of one or more ECC code words and determine whether or not to refresh the entire physical or logical page based on the results of reading the subset of ECC code words, such as an error rate, a number of errors, a quality-of-service or priority level indicated by metadata stored with the data, or the like. For example, if the refresh module 304 and/or the data factor module 322 determines that a sample ECC code word from a logical or physical page does not have any errors, does not have any uncorrectable errors, has a number of errors that do not satisfy a predetermined error threshold, or the like, the refresh module 304 may determine that the copyback module 306 may internally copy or move the logical or physical page back to a second, destination set of storage cells (e.g., a page of TLC storage cells) without refreshing the data.” [para. 0100]
Hummier et al., US Pub. No. 2008/0313494 A1 – teaches “A method of determining refresh intervals for a memory device, comprising: refreshing a first page of a memory array; determining whether a data error occurred when the first page was refreshed; establishing a first refresh interval for the first page in response to determining whether a data error occurred when the first page was refreshed; refreshing a second page of the memory array; determining whether a data error occurred in when the second page was refreshed; and establishing a second refresh interval for the second page in response to determining whether a data error occurred when the second page was refreshed.” [claim 28]
Chen et al., US Pub. No. 2016/0253112 A1 – teaches “The memory system according to claim 2, wherein the first data includes data designated by the write request and a logical address corresponding to the data, and the controller is configured to in a case where an abnormal power interruption occurs, after power restoration, sequentially read data in a block from a page in the next write order of the pages in the block where the writing operation is performed at the last among target pages of the first process to perform a first error correction, in a case where the first error correction is failed, determine whether there is data which is of a second page sharing the word line with a first page failed in the error correction and already subjected to the first process, in a case where there is the data, read the data of the second page to perform a second error correction, in a case where the second error correction is failed, acquire the first physical address associated to the physical address of the second page from the third information, read the first data stored in the first physical address based on the acquired first physical address, and update the first information with information in which a logical address contained in the read-out first data and a physical address of the second page are associated.” [claim 3]
Hung et al., US Pub. No. 2022/0137842 A1 – teaches “The host device, for example, host 120, reads the error threshold flag value and determines whether to perform a data refresh operation to prevent the data in the memory page from being irrevocably corrupted.” [para. 0061]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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