DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 05/08/2025 are acceptable for examination purposes.
Information Disclosure Statement
The reference(s) listed in the disclosure statement (IDS) submitted on 12/10/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97.
Claim Objections
Claim 6 and 15 is objected to because of the following informalities:
Claim 6 recitation that “computing how many codewords in the first portion is associated with a bit error count” is a grammatical/clarity problem. It should grammatically be something like “are associated” as the same for“ A quantity of the codewords in the first portion that is associated with the bit error count.”
Claim 15 states “number of errors represent” which grammatically be “represents.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 and 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “The system of claim 5, the operations comprising: computing how many codewords in the first portion is associated with a bit error count that transgresses a bit error count threshold or have uncorrectable errors; and incrementing the first count based on a quantity of the codewords in the first portion that is associated with the bit error count that transgresses the bit error count threshold or have uncorrectable errors.”
Claim 8 recites the limitation “The system of claim 7, the operations comprising: updating the first count and the second count based on a quantity of errors that transgresses an error threshold associated with reading data from a second portion of the individual stripe.”
It is unclear what the recited “first count” represents. Claim 3, from which claim 6 and 8 depends, recites that the first count represents a “total number of errors in the data stored across the individual stripe.” Claim 6 and 8, however, recites incrementing and updating the first count and second count based on a “quantity of the codewords” having bit error counts that transgress a threshold or having uncorrectable errors. It is therefore unclear whether the first count represents a total number of individual bit errors or a total number of codewords satisfying an error criterion.
Claim 15 recites the limitation “The system of claim 1, wherein the number of errors represent an uncorrectable bit error associated with one or more portions of the data stored in the individual memory component.”
“number of errors represent an uncorrectable bit error” mixes a numerical quantity with a singular error. A number of errors ordinarily represents a count/quantity. An uncorrectable bit error sounds like an error classification or condition. Claim 14 makes conceptual sense as number of errors represents a bit error count.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 14 , 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tehrani et al (US 20220301637 A1), herein Tehrani, in view of Palmer (US 20200303019 A1).
As per claim 1, Tehrani teaches a system comprising:
a set of memory components of a memory sub-system (The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such; Tehrani p. 0021);
and a processing device operatively coupled to the set of memory components, the processing device being configured to perform operations comprising (A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations…The memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in a local memory; Tehrani p. 0031-0032)::
receiving a request to read data from an individual memory component of the set of memory components (receiving a request to perform a set of read operations; selecting a random read operation of the set of read operations, wherein the random read operation is performed on a first wordline located on a first portion of a first data block on a memory device; Tehrani Claim 1)(the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices; Tehrani p. 0034);
in response to receiving the request to read the data, reading the data from the individual memory component (The first read operation R249 can be performed on a first location on the memory device…The first data integrity scan operation 270 can include two read operations, one read operation R271 on victim wordline WLn−1 to determine a reliability statistic 272 and another read operation R273 on victim wordline WLn+1 to determine a reliability statistic; Tehrani p. 0048-0049);
computing a number of errors associated with reading the data from the individual memory component (The RBER (also referred to as “error rate” herein) corresponds to a number of bit errors per sample size (e.g., per page or per code word) that the data stored at the data block experiences…the RBER value for wordline WLn−1 is “390” and the RBER value for wordline WLn+1 is “410”; Tehrani p. 0049);
determining whether the number of errors satisfies a refresh condition (data integrity component 113 can determine whether at least one of the one or more first reliability statistics satisfies (e.g., meets or exceeds) a threshold criterion ("refresh condition")…RBER value to be “390,” which is below the threshold criterion of “400” and as such does not satisfy the threshold criterion. However, stat 274 indicates the RBER value to be “410,” which is above the threshold criterion of “400” and as such satisfies the threshold criterion. Thus, at least one of the first reliability statistics satisfies the threshold criterion; Tehrani p. 0051);
and selectively refreshing the data stored in the individual memory component based on whether the number of errors satisfies the refresh condition (the data stored at the data block can be relocated to a new data block of the memory sub-system (also referred to herein as “folding”)… The folding of the data stored at the data block to the other data block can include writing the data to the other data block to refresh the data stored by the memory sub-system; Tehrani p. 0017)(the processing logic migrates data stored on the first portion of the first data block to a second data block on the memory device if the error rate satisfies the threshold criterion; Tehrani p. 0068) (threshold satisfied>migrate/fold>refresh data).
Tehrani does not explicitly teach the induvial memory component when it mentions receiving a request to read data from an individual memory component of the set of memory components.
However, Palmer in an analogous art teaches receiving a request to read data from an individual memory component of the set of memory components (a read request is received for a first portion of a first die (e.g., a first plane or a first group of planes); Palmer p. 0068)( receiving a first read command requesting data stored on a first plane of a first die of the memory device; Palmer Claim 9).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani with the teachings of Palmer by configuring receiving a request to read data from an individual memory component of the set of memory components.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ receiving from an individual memory component in the system of Tehrani because Palmer teaches issuing a read command to increase the probability that commands can be executed in parallel using multi-plane read so the overall system latency can be reduced by executing more read commands in parallel (Palmer p. 0023).
As per claim 14, Tehrani in view of Palmer teaches the system of claim 1,
wherein the number of errors represent a bit error count associated with one or more portions of the data stored in the individual memory component (The RBER (also referred to as “error rate” herein) corresponds to a number of bit errors per sample size (e.g., per page or per code word) that the data stored at the data block experiences; Tehrani p. 0049).
As per claim 16, Tehrani in view of Palmer teaches the system of claim 1, the operations comprising:
preventing refreshing the data stored in the individual memory component in response to determining that the number of errors fails to satisfy the refresh condition (The folding of the data stored at the data block to the other data block can include writing the data to the other data block to refresh the data stored by the memory sub-system; Tehrani p. 0017)(responsive to each one of the one or more first reliability statistics not satisfying the threshold criterion, the processing logic can continue to perform the first subset of read operations without migrating data stored on the first data block; Tehrani p. 0061).
As per claim 17, Tehrani in view of Palmer teaches the system of claim 1,
wherein refreshing the data comprises
folding the data (the data stored at the data block can be relocated to a new data block of the memory sub-system (also referred to herein as “folding”). The folding of the data stored at the data block to the other data block can include writing the data to the other data block to refresh the data stored by the memory sub-system; Tehrani p. 0017).
As per claim 18, Tehrani in view of Palmer teaches A method comprising:
receiving a request to read data from an individual memory component of the set of memory components (receiving a request to perform a set of read operations; selecting a random read operation of the set of read operations, wherein the random read operation is performed on a first wordline located on a first portion of a first data block on a memory device; Tehrani Claim 1)(the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices; Tehrani p. 0034);
in response to receiving the request to read the data, reading the data from the individual memory component (The first read operation R249 can be performed on a first location on the memory device…The first data integrity scan operation 270 can include two read operations, one read operation R271 on victim wordline WLn−1 to determine a reliability statistic 272 and another read operation R273 on victim wordline WLn+1 to determine a reliability statistic; Tehrani p. 0048-0049);
computing a number of errors associated with reading the data from the individual memory component (The RBER (also referred to as “error rate” herein) corresponds to a number of bit errors per sample size (e.g., per page or per code word) that the data stored at the data block experiences…the RBER value for wordline WLn−1 is “390” and the RBER value for wordline WLn+1 is “410”; Tehrani p. 0049);
determining whether the number of errors satisfies a refresh condition (data integrity component 113 can determine whether at least one of the one or more first reliability statistics satisfies (e.g., meets or exceeds) a threshold criterion ("refresh condition")…RBER value to be “390,” which is below the threshold criterion of “400” and as such does not satisfy the threshold criterion. However, stat 274 indicates the RBER value to be “410,” which is above the threshold criterion of “400” and as such satisfies the threshold criterion. Thus, at least one of the first reliability statistics satisfies the threshold criterion; Tehrani p. 0051);
and selectively refreshing the data stored in the individual memory component based on whether the number of errors satisfies the refresh condition (the data stored at the data block can be relocated to a new data block of the memory sub-system (also referred to herein as “folding”)… The folding of the data stored at the data block to the other data block can include writing the data to the other data block to refresh the data stored by the memory sub-system; Tehrani p. 0017)(the processing logic migrates data stored on the first portion of the first data block to a second data block on the memory device if the error rate satisfies the threshold criterion; Tehrani p. 0068) (threshold satisfied>migrate/fold>refresh data).
Tehrani does not explicitly teach the induvial memory component when it mentions receiving a request to read data from an individual memory component of the set of memory components.
However, Palmer in an analogous art teaches receiving a request to read data from an individual memory component of the set of memory components (a read request is received for a first portion of a first die (e.g., a first plane or a first group of planes); Palmer p. 0068)( receiving a first read command requesting data stored on a first plane of a first die of the memory device; Palmer Claim 9).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani with the teachings of Palmer by configuring receiving a request to read data from an individual memory component of the set of memory components.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ receiving from an individual memory component in the system of Tehrani because Palmer teaches issuing a read command to increase the probability that commands can be executed in parallel using multi-plane read so the overall system latency can be reduced by executing more read commands in parallel (Palmer p. 0023).
As per claim 20, Tehrani in view of Palmer teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising (The data storage system 618 can include a machine-readable storage medium 624 (also known as a computer-readable medium) on which is stored one or more sets of instructions; Tehrani p. 0073)(A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive a request to perform a set of read operations; Tehrani Claim 15):
receiving a request to read data from an individual memory component of the set of memory components (receiving a request to perform a set of read operations; selecting a random read operation of the set of read operations, wherein the random read operation is performed on a first wordline located on a first portion of a first data block on a memory device; Tehrani Claim 1)(the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices; Tehrani p. 0034);
in response to receiving the request to read the data, reading the data from the individual memory component (The first read operation R249 can be performed on a first location on the memory device…The first data integrity scan operation 270 can include two read operations, one read operation R271 on victim wordline WLn−1 to determine a reliability statistic 272 and another read operation R273 on victim wordline WLn+1 to determine a reliability statistic; Tehrani p. 0048-0049);
computing a number of errors associated with reading the data from the individual memory component (The RBER (also referred to as “error rate” herein) corresponds to a number of bit errors per sample size (e.g., per page or per code word) that the data stored at the data block experiences…the RBER value for wordline WLn−1 is “390” and the RBER value for wordline WLn+1 is “410”; Tehrani p. 0049);
determining whether the number of errors satisfies a refresh condition (data integrity component 113 can determine whether at least one of the one or more first reliability statistics satisfies (e.g., meets or exceeds) a threshold criterion ("refresh condition")…RBER value to be “390,” which is below the threshold criterion of “400” and as such does not satisfy the threshold criterion. However, stat 274 indicates the RBER value to be “410,” which is above the threshold criterion of “400” and as such satisfies the threshold criterion. Thus, at least one of the first reliability statistics satisfies the threshold criterion; Tehrani p. 0051);
and selectively refreshing the data stored in the individual memory component based on whether the number of errors satisfies the refresh condition (the data stored at the data block can be relocated to a new data block of the memory sub-system (also referred to herein as “folding”)… The folding of the data stored at the data block to the other data block can include writing the data to the other data block to refresh the data stored by the memory sub-system; Tehrani p. 0017)(the processing logic migrates data stored on the first portion of the first data block to a second data block on the memory device if the error rate satisfies the threshold criterion; Tehrani p. 0068) (threshold satisfied>migrate/fold>refresh data).
Tehrani does not explicitly teach the induvial memory component when it mentions receiving a request to read data from an individual memory component of the set of memory components.
However, Palmer in an analogous art teaches receiving a request to read data from an individual memory component of the set of memory components (a read request is received for a first portion of a first die (e.g., a first plane or a first group of planes); Palmer p. 0068)( receiving a first read command requesting data stored on a first plane of a first die of the memory device; Palmer Claim 9).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani with the teachings of Palmer by configuring receiving a request to read data from an individual memory component of the set of memory components.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ receiving from an individual memory component in the system of Tehrani because Palmer teaches issuing a read command to increase the probability that commands can be executed in parallel using multi-plane read so the overall system latency can be reduced by executing more read commands in parallel (Palmer p. 0023).
Claims 2, 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable ove Tehrani in view of Palmer in further view of CAMP et al (US 20160110248 A1), herein CAMP.
As per claim 2, Tehrani in view of Palmer, as combined, teaches the system of claim 1.
Tehrani in view of Palmer does not explicitly teach the operations comprising:
reading the data from a first portion of an individual stripe stored across a plurality of memory components of the set of memory components.
However, CAMP in an analogous art teaches reading the data from a first portion of an individual stripe stored across a plurality of memory components of the set of memory components (page stripes are grouped into a block stripe as is shown in FIG. 6A, where each block in the block stripe is associated to a different lane… block selection can be further restricted to be from the same plane, die, and/or chip enable ("individual stripe"). Once a block from each lane has been picked, page stripes are preferably formed from pages with the same page number from all blocks in the block stripe; CAMP p. 0029)(selects a first valid block in the selected block stripe (block 1004) and a first page group in the selected block; CAMP p. 0042).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani in view of Palmer with the teachings of CAMP by configuring reading the data from a first portion of an individual stripe
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ reading the of an individual stripe in the system of Tehrani in view of Palmer because CAMP teaches flash controller can access all of the pages of data that comprise the page stripe simultaneously or nearly simultaneously to support efficient access to a page stripe (CAMP p. 0033).
As per claim 15, Tehrani in view of Palmer, as combined, teaches the system of claim 1. Tehrani in view of Palmer does not explicitly teach wherein the number of errors represent an uncorrectable bit error associated with one or more portions of the data stored in the individual memory component.
However, CAMP in an analogous art teaches wherein the number of errors represent an uncorrectable bit error associated with one or more portions of the data stored in the individual memory component (one or more pages can no longer be read (i.e., contain too many errors such that one or more codewords are uncorrectable); CAMP p. 0046).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani in view of Palmer with the teachings of CAMP by configuring reading the data from a first portion of an individual stripe
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ reading the of an individual stripe in the system of Tehrani in view of Palmer because CAMP teaches flash controller can access all of the pages of data that comprise the page stripe simultaneously or nearly simultaneously to support efficient access to a page stripe (CAMP p. 0033).
As per claim 19, Tehrani in view of Palmer, as combined, teaches the method of claim 18. Tehrani in view of Palmer does not explicitly teach the operations comprising:
reading the data from a first portion of an individual stripe stored across a plurality of memory components of the set of memory components.
However, CAMP in an analogous art teaches reading the data from a first portion of an individual stripe stored across a plurality of memory components of the set of memory components (page stripes are grouped into a block stripe as is shown in FIG. 6A, where each block in the block stripe is associated to a different lane… block selection can be further restricted to be from the same plane, die, and/or chip enable ("individual stripe"). Once a block from each lane has been picked, page stripes are preferably formed from pages with the same page number from all blocks in the block stripe; CAMP p. 0029)(selects a first valid block in the selected block stripe (block 1004) and a first page group in the selected block; CAMP p. 0042).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani in view of Palmer with the teachings of CAMP by configuring reading the data from a first portion of an individual stripe
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ reading the of an individual stripe in the system of Tehrani in view of Palmer because CAMP teaches flash controller can access all of the pages of data that comprise the page stripe simultaneously or nearly simultaneously to support efficient access to a page stripe (CAMP p. 0033).
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable ove Tehrani in view of Palmer in further view of CAMP in further view of UM et al (US 20150052415 A1), herein UM.
As per claim 3, Tehrani in view of Palmer in further view of CAMP, as combined, teaches the system of claim 2 but does not explicitly teach the operations comprising:
storing a first count representing a total number of errors in the data stored across the individual stripe.
However, UM in an analogous art teaches storing a first count representing a total number of errors in the data stored across the individual stripe (The victim block information storage block may store victim block information such as an address of a memory block set to a victim block and an error count of the memory block set to the victim block…Alternatively, the error count may become a sum of error counts of all pages included in the memory block; UM p. 0044).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani in view of Palmer in further view of UM with the teachings of UM by configuring storing a first count representing a total number of errors in the data stored across the individual stripe.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ storing a first count representing a total number of errors in the system of Tehrani in view of Palmer in further view of UM because UM teaches determining whether or not an error count of the initial victim block is equal to or greater than a reference value by comparing the error count of the initial victim block with the reference value that may be set in consideration of the reliability and/or performance of the data storage device (UM p. 0066).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu et al (US 20180188954 A1) herein Chu.
As per claim 4, Tehrani in view of Palmer in further view of CAMP in further view of UM, as combined, teaches the system of claim 3 but does not explicitly teach the operations comprising:
storing a second count representing a total number of errors associated with each memory component of the set of memory components.
However, Chu in an analogous art teaches storing a second count representing a total number of errors associated with each memory component of the set of memory components (Table 300 may be stored in memory 150 and may be accessed and updated by controller 140. Alternatively, table 300 may be maintained in internal memory within controller…one column indicating total error counts for respective data operation error types across a non-volatile memory die; Chu p. 0023-0024)(Controller 140 sums error counts of the blocks for respective operation error types, and determines the total error counts of respective operation error types for each of non-volatile memory dies…Controller repeats the same or similar steps to determine total error counts for all of operation error types in both non-volatile memory dies; Chu p. 0032).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani in view of Palmer in further view of CAMP in further view of UM with the teachings of Chu by configuring storing a second count representing a total number of errors associated with each memory component.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ storing a count representing a total number of errors associated with each memory component in the system of Tehrani in view of Palmer in further view of CAMP in further view of UM because Chu teaches monitoring data operation error counts of blocks across non-volatile memory die and excluding non-volatile memory die from future data operations when the data operation error counts for non-volatile memory die satisfy predetermined thresholds to improve performance and reliability of data storage systems (Chu p. 0012).
As per claim 5, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu, as combined above, teaches the system of claim 4, the operations comprising:
determining that one or more errors of the number of errors associated with reading the data occurred in the first portion of the individual stripe stored in a first memory component of the set of memory components (Controller 140 may send a read command using a second processor core responsible for read operations to non-volatile memory die ("first memory die") 160B to read data in page 34B of block 3B ("first portion") of non-volatile memory die…non-volatile memory die 160B may experience an error during the read operation to page 34B, and report the error to the second processor core in controller; Chu p. 0027);
and in response to determining that the one or more errors occurred in the first portion of the individual stripe stored in the first memory component of the set of memory components, incrementing the second count (Based on the received report, controller 140 increments the error count for a read operation error type under block 3B of non-volatile memory die 160B in table 300 as illustrated in table; Chu p. 0027)(the controller increments an error count for an error type of the data operation error for the non-volatile memory die… controller 140 increments an error count of the read operation for block 3B in non-volatile memory die 160B when controller 140 encounters an error during hard decoding of the data from page; Chu p. 0040)(sums error counts of the blocks for respective operation error types, and determines the total error counts of respective operation error types for each of non-volatile memory dies; Chu p. 0032).
Claims 6-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu in further view of Cadloni et al (US 20220083421 A1), herein Cadloni.
As per claim 6, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu, as combined, teaches the system of claim 5 but does not explicitly teach the operations comprising:
computing how many codewords in the first portion is associated with a bit error count that transgresses a bit error count threshold or have uncorrectable errors;
and incrementing the first count based on a quantity of the codewords in the first portion that is associated with the bit error count that transgresses the bit error count threshold or have uncorrectable errors.
However, Cadloni in an analogous art teaches computing how many codewords in the first portion is associated with a bit error count that transgresses a bit error count threshold or have uncorrectable errors (a certain number of times that one or more codewords saved in the memory region (i) have bit error counts exceeding a codeword BEC threshold in comparison to a codeword BEC event threshold and/or (ii) are classified as unreliable and/or as uncorrectable (e.g., UECC) in comparison to a UECC event threshold; Cadloni p. 0013)(whether a certain number of codewords saved in the memory region (i) have bit error counts exceeding a codeword BEC threshold in comparison to a codeword BEC event threshold and/or (ii) are classified an unreliable and/or uncorrectable (e.g., UECC) in comparison to a UECC event threshold; Cadloni p. 0038);
and incrementing the first count based on a quantity of the codewords in the first portion that is associated with the bit error count that transgresses the bit error count threshold or have uncorrectable errors (a number of times bit errors have been encountered in the corresponding memory region in the past can be stored in the one or more logs; Cadloni p. 0022).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu with the teachings of Cadloni by configuring computing the codewords in the first portion is associated with a bit error count that transgresses a bit error count threshold or have uncorrectable errors and incrementing the first count.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ computing how many codewords in the first portion in the system of Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu because Cadloni teaches proactively discovering, refreshing), and/or removing less capable, potentially defective, and/or poor performing memory regions before they become an error recovery problem (Cadloni p. 0039).
As per claim 7, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu in further view of Cadloni, as combined above, teaches the system of claim 6, the operations comprising:
determining whether all portions of the individual stripe have been read (background health checker 930 determines whether or not all page groups within the currently selected block have been processed; CAMP p. 0055)(background health checker 930 determines whether or not all page groups within the currently selected block have been processed.; CAMP p. 0044);
and in response to determining that less than all portions of the individual stripe have been read, reading data from a second portion of the individual stripe (If not, background health checker 930 selects a next page group for processing at block 1016, and the process returns to block…If not, background health checker 930 selects the next valid block in the block stripe; CAMP p. 0055-0056)(background health checker 930 performs a page group read sweep test over the selected page group; CAMP p. 0046).
As per claim 8, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu in further view of Cadloni, as combined above, teaches the system of claim 7, the operations comprising:
updating the first count and the second count based on a quantity of errors that transgresses an error threshold associated with reading data from a second portion of the individual stripe (a codeword stored in a memory region has a BEC (e.g., 42 bit errors) greater than and/or equal to a codeword BEC threshold (e.g., 40 bit errors), the routine 360 can register this as a codeword BEC event…can proceed to block 364 to schedule and/or perform a (e.g., immediate) retirement operation on a memory region storing one or more codewords that triggered the routine 360 to register a total of 16 or more codeword BEC events; Cadloni p. 0052)( the bit error count (BEC) of the codeword is greater than (or equal to) a codeword BEC threshold; Cadloni p. 0034)(Chu as stated in rejection for Claims 4-5 gives us the updating mechanism for the second count as Chu increments the error count for that block/die. Camp moves to the second portion and the second portion resides on another memory component that Chu updates).
As per claim 9, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu in further view of Cadloni, as combined above, teaches the system of claim 7, the operations comprising:
determining that all portions of the individual stripe have been read (Background health checker 930 determines whether or not all page groups within the currently selected block have been processed…If, however, background health checker 930 determines at block 1014 that all page groups in the currently selected block have been processed, the process passes to block 1020, which illustrates background health checker 930 updating the block health metric for the block in GPP memory…Background health checker 930 then determines at block 1030 whether all blocks in the currently selected block stripe have been processed; CAMP p. 0055-0056).
As per claim 10, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu in further view of Cadloni, as combined above, teaches the system of claim 9, the operations comprising:
determining that the second count transgresses a die count threshold in response to determining that all portions of the individual stripe have been read (Controller 140 sums error counts of the blocks for respective operation error types, and determines the total error counts of respective operation error types for each of non-volatile memory dies…Controller repeats the same or similar steps to determine total error counts for all of operation error types in both non-volatile memory dies… Controller 140 may determine whether a total error count for a specific data operation error type for non-volatile memory die satisfies a predetermined threshold value after an error count for the specific data operation error type is incremented; Chu p. 0032);
and in response to determining that the second count transgresses the die count threshold, determining that the refresh condition has been satisfied (a codeword BEC event count threshold can be one codeword BEC event such that the routine 360 can proceed to blocks 364 or 368 to schedule and/or perform (e.g., immediate) refresh and/or retirement operations on a memory region storing a codeword that triggered the routine 360 to register a codeword BEC event…a first codeword BEC event count threshold can be one codeword BEC event such that the routine 360 can proceed to block 368 to schedule and/or perform a (e.g., immediate) refresh operation on a memory region storing a codeword that triggered the routine 360 to register a codeword BEC event…a combination UECC and codeword BEC event threshold can be ten total UECC at RR0 and/or codeword BEC events.; Cadloni p. 0052-0053)( the routine 360 can wait to check all defined thresholds before proceeding to blocks 364 and/or 368 (e.g., to determine whether to refresh or to retire a memory region); Cadloni p. 0055).
As per claim 11, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu in further view of Cadloni, as combined above, teaches the system of claim 10, the operations comprising:
refreshing the data stored in the individual memory component in response to determining that the refresh condition has been satisfied (BEC event such that the routine 360 can proceed to block 368 to schedule and/or perform a (e.g., immediate) refresh operation on a memory region storing a codeword that triggered the routine 360 to register a codeword BEC event…a combination UECC and codeword BEC event threshold can be ten total UECC at RR0 and/or codeword BEC events.; Cadloni p. 0052-0053).
As per claim 12, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu in further view of Cadloni, as combined above, teaches the system of claim 10, the operations comprising:
determining that the first count transgresses a stripe count threshold (the routine 360 can compare the updated quality metric(s) to one or more codeword bit error count (BEC) event count thresholds to identify, refresh, and/or retire memory regions storing one or more codewords having BEC's greater than and/or equal to a codeword BEC threshold…a codeword BEC event count threshold can be a number (e.g., one, two, three, five, ten, sixteen, etc.) of codeword BEC events…storing one or more codewords that triggered the routine 360 to register a total of 16 or more codeword BEC events; Cadloni p. 0052);
and in response to determining that the first count transgresses the stripe count threshold, determining that the refresh condition has been satisfied (a first codeword BEC event count threshold can be one codeword BEC event such that the routine 360 can proceed to block 368 to schedule and/or perform a (e.g., immediate) refresh operation on a memory region storing a codeword that triggered the routine 360 to register a codeword BEC event…the routine 360 can proceed to block 368 to schedule and/or perform (e.g., immediate) refresh operations on the memory region for the first fifteen and/or sixteen codeword BEC events the routine 360 registers regarding the memory region; Cadloni p. 0052).
As per claim 13, Tehrani in view of Palmer in further view of CAMP in further view of UM in further view of Chu in further view of Cadloni, as combined above, teaches the system of claim 12, the operations comprising:
refreshing the data stored in the individual memory component in response to determining that the refresh condition has been satisfied (the routine 360 can proceed to block 368 to schedule and/or perform (e.g., immediate) refresh operations on the memory region for the first fifteen and/or sixteen codeword BEC events the routine 360 registers regarding the memory region…a combination UECC and codeword BEC event threshold can be ten total UECC at RR0 and/or codeword BEC events. In this example, the routine 360 can proceed to blocks 364 or 368 to schedule and/or perform (e.g., immediate) refresh and/or retirement operations on a memory region storing one or more codewords that triggered the routine; Cadloni p. 0052-0053)
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts of record teach:
Papandreou et al (US 20200234780 A1) teaches managing programming errors in a multilevel NAND flash memory is provided. The multilevel NAND flash memory uses a two-pass programming algorithm—e.g., a first programming pass and a second programming pass—for programming a memory block being organized in pages, sharing a word line. The method comprises performing the first programming pass for at least one memory page, reading the at least one memory page between the first programming pass and the second programming pass, determining an error count value for the at least one programmed memory page, and responsive to determining that the error count value is below a threshold value, performing the second programming pass with active data.
Cariello et al (US 20200110660 A1) teaches performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.
Bronner et al (US 20160071608 A1) teaches Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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