DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 05/08/2025 are acceptable for examination purposes.
Information Disclosure Statement
The reference(s) listed in the disclosure statement (IDS) submitted on 05/08/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-8, 13-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al (US 20210158885 A1) hereinafter referred as KIM1 in view of Kim (US 20060050576 A1), hereinafter referred as Kim2, in further view of Iyer et al (US 20160085619 A1), hereinafter referred as Iyer.
As per claim 1, KIM1 teaches an operating method of a storage device including a storage controller and a non- volatile memory, the operating method (The memory devices are categorized into volatile memory device and non-volatile memory device according to the storage mechanisms…the memory system according to the embodiment of the disclosure includes the memory controller 100 and the flash memory device 200; p. KIM1 p. 0033) comprising:
generating, by the storage controller, a plurality of pieces of transmission parity data (the memory controller 100 includes a parity signal generation unit 110 configured to receive the write enable signal WE transmitted in DDR mode and output a parity signal by generating a first parity bit for transmitted input data (the controller generates parity for transmitted input data); KIM p. 0032) respectively corresponding to a plurality of data lines (The data line DQ may be implemented with a plurality of flip-flops and IO pads which one-to-one correspond to the flip-flops. For the input data to be transmitted through the data line DQ, an exclusive OR (XOR) operation may be performed with a combination of logic gates to generate the first parity bit; KIM1 p. 0057), the plurality of pieces of transmission parity data including first transmission parity data and second transmission parity data (output a parity signal by generating a first parity bit for transmitted input data, and the flash memory device 200 includes a bit error detection unit 210 configured to receive the parity signal output from the memory controller 100, generate a second parity bit; KIM1 p. 0032) (generates a second parity bit for input data received by the flash memory device 200. Further, the bit error detection unit 210 extracts the first parity bit from the received parity signal, and performs a parity check by comparing the first parity bit with the second parity bit; KIM1 p. 0042);
transmitting, by the storage controller and to the non-volatile memory, (i) a plurality of pieces of data respectively corresponding to the plurality of data lines and (ii) the plurality of pieces of transmission parity data respectively corresponding to the plurality of pieces of data (Input data is transmitted to the flash memory device 200 through the data line DQ at the rising and falling edges of the data strobe signal DQS. In this case, the DDR transmission may be started and terminated by the command latch enable signal CLE and the address latch enable signal ALE. Compared to the conventional flash memory system in which data is input by DDR transmission and thus the write enable signal WE is fixed to the deasserted state “1” without being used, the write enable signal WE is used as a parity check bit by changing its usage during DDR transmission to detect a bit error during transmission in the memory system of the disclosure; KIM1 p. 0038)
performing, by the non-volatile memory, a determination operation to determine that a transmission error exists with respect to each data line in the second group of data lines based on the second transmission parity data (performs a parity check by comparing the first parity bit with the second parity bit. The bit error detection unit 210 may determine whether a bit error has occurred to the input data during DDR transmission from the result of the parity check; KIM1 p. 0042);
determining, by the non-volatile memory, that a condition for performing retraining is satisfied based on a counting result generated from the counting operation and a determination result generated from the determination operation (when the bit error detection unit determines that no bit error has occurred to the input data, the memory controller may be configured to transmit a program command to the flash memory device to write the input data to the flash memory device, and when the bit error detection unit determines that a bit error has occurred to the input data, the memory controller may be configured to retransmit ("retrain") the input data; KIM1 p. 0008);
and transmitting, by the non-volatile memory, transmission error status information to the storage controller based on a determination that the condition for performing retraining is satisfied (The parity check status register 220 stores a bit error detection result obtained by the bit error detection unit 210. The stored bit error detection result may be transmitted to the memory controller 100. In one embodiment, when the memory controller 100 transmits a status read command to the flash memory device 200, the flash memory device 200 may transmit the bit error detection result stored in the parity check status register 220 to the memory controller; KIM1 p. 0046) (The bit error detection result stored in the parity check status register 220 may also be transmitted to the memory controller 100 through the data IO logic 250; KIM1 p. 0050).
KIM1 does not explicitly teach respectively corresponding to a plurality of data lines having a first and second group of data lines.
However, Kim2 can be used to strengthen the teaching of parity architecture with a first and second parity generation and the comparison between the two as it states “the first parity generator 150 receives the data provided from the data input buffer 160 to generate an error detection code EDC. The error detection code generated from the first parity generator 150 is defined as a first parity…The second parity generator 140 generates an error detection code EDC in the same operation as the first parity generator 150 performed. The error detection code generated from the second parity generator 140 is defined as a second parity” (Kim2 p. 0019, 0024).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM1 with the teachings of Kim2 by configuring generating a first and a second transmission parity data.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a first and second parity generation in the system of KIM1 because Kim2 teaches comparing the first and second parities and generating a detection signal; and storing the detection signal in a state register to control the first and second clock signals to generate the detection signal before a program verify operation is performed (Kim2 p. 0071).
As stated above, KIM1 teaches generating, by the storage controller, a plurality of pieces of transmission parity data respectively corresponding to a plurality of data lines (KIM p.0032, 0057). KIM1 teaches data is transmitted through the data line DQ. DQ interface is implemented with multiple I/O pads.
KIM1 in view of Kim1, as combined, does not explicitly generating, by the storage controller, a plurality of pieces of transmission parity data respectively corresponding to a plurality of data lines.
However, Iyer in an analogous art teaches generating, by the storage controller, a plurality of pieces of transmission parity data respectively corresponding to a plurality of data lines (A link may support one lane—each lane representing a set of differential signal pairs ("plurality of data lines") (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider; Iyer p. 0040).
The combination of KIM1 and Kim2 also do not explicitly the first transmission parity data being transmitted through a first group of data lines of the plurality of data lines, and the second transmission parity data being transmitted through a second group of data lines of the plurality of data lines; performing, by the non-volatile memory, a counting operation to count a number of transmission error bits with respect to each data line in the first group of data lines based on the first transmission parity data;
However, Iyer teaches the first transmission parity data being transmitted through a first group of data lines of the plurality of data lines, and the second transmission parity data being transmitted through a second group of data lines of the plurality of data lines (the data link layer 210 is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components on a link. One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device (equates transmission across multiple data lines); Iyer p. 0035);
performing, by the non-volatile memory, a counting operation to count a number of transmission error bits (the lane monitor is further to determine a problem with the particular lane based on determining an amount of bit errors (“counting”) associated with the particular lane, wherein the amount includes the bit error associated with the particular lane; Iyer Claim 2; FIG 14B) with respect to each data line in the first group of data lines based on the first transmission parity data (determine that the one or more particular bits were sent over one or more particular lanes of the link; and associate the bit error with the one or more particular lanes; Iyer Claim 1).
Just like KIM1, Iyer also teaches performing, by the non-volatile memory, a determination operation to determine that a transmission error exists with respect to each data line in the second group of data lines based on the second transmission parity data (determine that a bit error in a flit transmitted over a link affected one or more particular bits of the flit using a syndrome value associated with a cyclic redundancy check (CRC) value of the flit; Iyer Claim 1).
As per determining, by the non-volatile memory, that a condition for performing retraining is satisfied based on a counting result generated from the counting operation and a determination result generated from the determination operation, KIM1, as stated above, teaches this but uses the word “retransmit” instead of “retraining”. Although the two words equate, Iyer also teaches performing retraining based on a counting result generated from the counting operation (wherein the lane monitor is further to determine a problem with the particular lane based on determining an amount ("counting") of bit errors associated with the particular lane, wherein the amount includes the bit error associated with the particular lane….the lane monitor is further to initiate an action on the particular lane based on determining the problem…the action comprises retraining the particular lane.; Iyer Claim 2-4).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM in view of Kim2 with the teachings of Iyer by configuring performing a counting operation to count a number of transmission error bit and retraining based off the results generated from that counting operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ retraining based from results from the counting operation that determines the amount of bit errors in the system of KIM1 in view of Kim2 because Iyer teaches counting bit errors associated with lane links assisting with the reduction of bit errors and retry rates for the link while limiting the impact on link performance, among other example advantages (Iyer p. 0064).
As per claim 6, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 1,
wherein the transmission error status information includes an index of a data line of the plurality of data lines that has a transmission error (It is determined that the one or more particular bits were sent over one or more particular lanes of the link. The bit error is associated with the one or more particular lanes based on determining that the affected bits were transmitted over the particular lanes (This is essentially an index identifying which data lane ("data line") experience the transmission error.); Iyer ABST);
and a number of transmission errors counted with respect to the data line (Track bit errors associated with each lane of the link; Iyer FIG. 14B)
As per claim 7, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 1,
wherein the transmission error status information includes a transmission error status or the number of transmission error bits with respect to each of the plurality of data lines (Lane Error Monitor and Lane Manager; Iyer FIG. 7) (Track bit errors associated with each lane of the link, Identify issue with a lane, Initiate action to resolve issues with lane; Iyer FIG. 14B)
As per claim 8, Claim 8 will receive the same rejection as Claim 1. KIM1 in view of Iyer teaches an operating method of a non-volatile memory, the operating method (The memory devices are categorized into volatile memory device and non-volatile memory device according to the storage mechanisms…the memory system according to the embodiment of the disclosure includes the memory controller 100 and the flash memory device 200; p. KIM p. 0002, 0033) comprising:
receiving, from a storage controller, (i) a plurality of pieces of data respectively corresponding to a plurality of data lines and (ii) a plurality of pieces of transmission parity data respectively corresponding to the plurality of pieces of data (Input data is transmitted to the flash memory device 200 through the data line DQ at the rising and falling edges of the data strobe signal DQS. In this case, the DDR transmission may be started and terminated by the command latch enable signal CLE and the address latch enable signal ALE. Compared to the conventional flash memory system in which data is input by DDR transmission and thus the write enable signal WE is fixed to the deasserted state “1” without being used, the write enable signal WE is used as a parity check bit by changing its usage during DDR transmission to detect a bit error during transmission in the memory system of the disclosure; KIM p. 0038);
performing a counting operation to count a number of transmission error bits (the lane monitor is further to determine a problem with the particular lane based on determining an amount of bit errors (“counting”) associated with the particular lane, wherein the amount includes the bit error associated with the particular lane; Iyer Claim 2; FIG 14B) with respect to each of the plurality of data lines based on the transmission parity data (determine that the one or more particular bits were sent over one or more particular lanes of the link; and associate the bit error with the one or more particular lanes; Iyer Claim 1);
determining that a condition for performing retraining is satisfied based on a counting result generated from the counting operation (when the bit error detection unit determines that no bit error has occurred to the input data, the memory controller may be configured to transmit a program command to the flash memory device to write the input data to the flash memory device, and when the bit error detection unit determines that a bit error has occurred to the input data, the memory controller may be configured to retransmit ("retrain") the input data; KIM p. 0008)(wherein the lane monitor is further to determine a problem with the particular lane based on determining an amount ("counting") of bit errors associated with the particular lane, wherein the amount includes the bit error associated with the particular lane….the lane monitor is further to initiate an action on the particular lane based on determining the problem…the action comprises retraining the particular lane.; Iyer Claim 2-4)
and transmitting transmission error status information to the storage controller based on a determination that the condition for performing retraining is satisfied (The parity check status register 220 stores a bit error detection result obtained by the bit error detection unit 210. The stored bit error detection result may be transmitted to the memory controller 100. In one embodiment, when the memory controller 100 transmits a status read command to the flash memory device 200, the flash memory device 200 may transmit the bit error detection result stored in the parity check status register 220 to the memory controller; KIM p. 0046) (The bit error detection result stored in the parity check status register 220 may also be transmitted to the memory controller 100 through the data IO logic 250; KIM p. 0050).
As per claim 13, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 8,
wherein the transmission error status information includes an index of a data line of the plurality of data lines that has a transmission error (It is determined that the one or more particular bits were sent over one or more particular lanes of the link. The bit error is associated with the one or more particular lanes based on determining that the affected bits were transmitted over the particular lanes (This is essentially an index identifying which data lane ("data line") experience the transmission error.); Iyer ABST);
and a number of transmission errors counted with respect to the data line (Track bit errors associated with each lane of the link; Iyer FIG. 14B).
As per claim 14, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 8,
wherein the transmission error status information includes a transmission error status or the number of transmission error bits with respect to each of the plurality of data lines (Lane Error Monitor and Lane Manager; Iyer FIG. 7) (Track bit errors associated with each lane of the link, Identify issue with a lane, Initiate action to resolve issues with lane; Iyer FIG. 14B)
As per claim 15, KIM1 in view of Kim2 in further view of Iyer teaches A storage device comprising: a non-volatile memory, and a storage controller (The memory devices are categorized into volatile memory device and non-volatile memory device according to the storage mechanisms…the memory system according to the embodiment of the disclosure includes the memory controller 100 and the flash memory device 200; p. KIM p. 0002, 0033) configured to
generate a plurality of pieces of transmission parity data (the memory controller 100 includes a parity signal generation unit 110 configured to receive the write enable signal WE transmitted in DDR mode and output a parity signal by generating a first parity bit for transmitted input data (the controller generates parity for transmitted input data); KIM p. 0032) (the first parity generator 150 receives the data provided from the data input buffer 160 to generate an error detection code EDC. The error detection code generated from the first parity generator 150 is defined as a first parity…The second parity generator 140 generates an error detection code EDC in the same operation as the first parity generator 150 performed. The error detection code generated from the second parity generator 140 is defined as a second parity; Kim2 p. 0019, 0024) respectively corresponding to a plurality of data lines (The data line DQ may be implemented with a plurality of flip-flops and IO pads which one-to-one correspond to the flip-flops. For the input data to be transmitted through the data line DQ, an exclusive OR (XOR) operation may be performed with a combination of logic gates to generate the first parity bit; KIM p. 0057) (A link may support one lane—each lane representing a set of differential signal pairs ("plurality of data lines") (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider; Iyer p. 0040),
and transmit, to the non-volatile memory, (i) a plurality of pieces of data respectively corresponding to the plurality of data lines and (ii) the plurality of pieces of transmission parity data respectively corresponding to the plurality of pieces of data (Input data is transmitted to the flash memory device 200 through the data line DQ at the rising and falling edges of the data strobe signal DQS. In this case, the DDR transmission may be started and terminated by the command latch enable signal CLE and the address latch enable signal ALE. Compared to the conventional flash memory system in which data is input by DDR transmission and thus the write enable signal WE is fixed to the deasserted state “1” without being used, the write enable signal WE is used as a parity check bit by changing its usage during DDR transmission to detect a bit error during transmission in the memory system of the disclosure; KIM p. 0038),
wherein the non-volatile memory is configured to perform a counting operation to count a number of transmission error bits (the lane monitor is further to determine a problem with the particular lane based on determining an amount ("counting") of bit errors associated with the particular lane, wherein the amount includes the bit error associated with the particular lane; Iyer Claim 2; FIG 14B) with respect to each of the plurality of data lines based on the transmission parity data (determine that the one or more particular bits were sent over one or more particular lanes of the link; and associate the bit error with the one or more particular lanes; Iyer Claim 1), determine that a condition for performing retraining is satisfied based on a counting result generated from the counting operation (when the bit error detection unit determines that no bit error has occurred to the input data, the memory controller may be configured to transmit a program command to the flash memory device to write the input data to the flash memory device, and when the bit error detection unit determines that a bit error has occurred to the input data, the memory controller may be configured to retransmit ("retrain") the input data; KIM p. 0008) (wherein the lane monitor is further to determine a problem with the particular lane based on determining an amount ("counting") of bit errors associated with the particular lane, wherein the amount includes the bit error associated with the particular lane….the lane monitor is further to initiate an action on the particular lane based on determining the problem…the action comprises retraining the particular lane.; Iyer Claim 2-4), and transmit transmission error status information to the storage controller based on a determination that the condition for performing retraining is satisfied (The parity check status register 220 stores a bit error detection result obtained by the bit error detection unit 210. The stored bit error detection result may be transmitted to the memory controller 100. In one embodiment, when the memory controller 100 transmits a status read command to the flash memory device 200, the flash memory device 200 may transmit the bit error detection result stored in the parity check status register 220 to the memory controller; KIM p. 0046) (The bit error detection result stored in the parity check status register 220 may also be transmitted to the memory controller 100 through the data IO logic 250; KIM p. 0050)
As per claim 20, KIM1 in view of Kim2 in further view of Iyer teaches the storage device of claim 15,
wherein the transmission error status information includes an index of a data line of the plurality of data lines that has a transmission error (It is determined that the one or more particular bits were sent over one or more particular lanes of the link. The bit error is associated with the one or more particular lanes based on determining that the affected bits were transmitted over the particular lanes (This is essentially an index identifying which data lane ("data line") experience the transmission error.); Iyer ABST)
and a number of transmission errors counted with respect to the data line (Track bit errors associated with each lane of the link; Iyer FIG. 14B).
Claims 2-3, 9-10, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of Kim2, in further view of Iyer in further view of Sforzin et al (US 20220179736 A1), herein after referred as Sforzin.
As per claim 2, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 1. The combination of KIM1, Kim2 and Iyer does not teach wherein the first transmission parity data is generated by the storage controller based on shortened Hamming code encoding.
However, Sforzin in an analogous art teaches wherein the first transmission parity data is generated by the storage controller based on shortened Hamming code encoding (can use an extended-shortened Hamming code. A primitive binary Hamming code can be used with parameters N=511, K=502, where N (or n) is the size (or length) of the codeword including the parity data and K (or k) is the size (or length) of the codeword data without the parity data (N and K refer to the values of the primitive binary Hamming code while n and k refer to values of the shortened binary Hamming code). The Hamming code can be generated by shortening or reducing the original 511 positions of the code by 245 positions in order to match a data payload…The encoding operation can include performing the computation p=d′R′, where p is a parity row vector of 9 bits, d′ is a data row vector of 257 bits, and R′ is an encoding matrix with 257 rows and 9 columns. The rows of R′ can be a subset of all non-zero patterns with 9 binary elements. Each pattern can correspond to a data position and the patterns linked to the shortened positions may not be in R′; Sforzin p. 0045-0046).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM1 in view of Kim2 in further view of Iyer with the teachings of Sforzin by configuring the transmission parity data is to be generated by the storage controller based on shortened Hamming code encoding.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ shortened Hamming code encoding in the system of KIM1 in view of Kim2 in further view of Iyer because Sforzin teaches Hamming code generated by shortening or reducing the original positions of the code by positions in order to match a data payload, thereby providing ECC protection tailored to the size of transmitted data (Sforzin p. 0045)
As per claim 3, KIM1 in view of Kim2 in further view of Iyer in further view of Sforzin teaches the operating method of claim 2,
wherein the first transmission parity data includes a bit making a number of 1s in the first transmission parity data an even number (The extension of the Hamming code can include adding a checksum bit, thus resulting in the code including parameters n=267, k=257, where there are 10 parity bits including the 1 checksum bit; Sforzin p. 0045)(the parity (even or odd) of a binary vector v can be defined as the binary value: w(v)mod 2), where w(v) is the weight function, i.e., the function returning the number of “1”s in the vector. Therefore, if the number of “1”s in the vector is even, the parity is “0,” while if the number of “1”s in the vector is odd, the parity is “1.”; Sforzin p. 0054).
As per claim 9, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 8,
wherein the transmission parity data is generated by the storage controller based on shortened Hamming code encoding (can use an extended-shortened Hamming code. A primitive binary Hamming code can be used with parameters N=511, K=502, where N (or n) is the size (or length) of the codeword including the parity data and K (or k) is the size (or length) of the codeword data without the parity data (N and K refer to the values of the primitive binary Hamming code while n and k refer to values of the shortened binary Hamming code). The Hamming code can be generated by shortening or reducing the original 511 positions of the code by 245 positions in order to match a data payload…The encoding operation can include performing the computation p=d′R′, where p is a parity row vector of 9 bits, d′ is a data row vector of 257 bits, and R′ is an encoding matrix with 257 rows and 9 columns. The rows of R′ can be a subset of all non-zero patterns with 9 binary elements. Each pattern can correspond to a data position and the patterns linked to the shortened positions may not be in R′.; Sforzin p. 0045-0046).
As per claim 10, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 9,
wherein the transmission parity data includes a bit making a number of 1s in the transmission parity data an even number (The extension of the Hamming code can include adding a checksum bit, thus resulting in the code including parameters n=267, k=257, where there are 10 parity bits including the 1 checksum bit; Sforzin p. 0045)(the parity (even or odd) of a binary vector v can be defined as the binary value: w(v)mod 2), where w(v) is the weight function, i.e., the function returning the number of “1”s in the vector. Therefore, if the number of “1”s in the vector is even, the parity is “0,” while if the number of “1”s in the vector is odd, the parity is “1.”; Sforzin p. 0054).
As per claim 16, KIM1 in view of Kim2 in further view of Iyer teaches the storage device of claim 15,
wherein the transmission parity data is generated by the storage controller based on shortened Hamming code encoding (can use an extended-shortened Hamming code. A primitive binary Hamming code can be used with parameters N=511, K=502, where N (or n) is the size (or length) of the codeword including the parity data and K (or k) is the size (or length) of the codeword data without the parity data (N and K refer to the values of the primitive binary Hamming code while n and k refer to values of the shortened binary Hamming code). The Hamming code can be generated by shortening or reducing the original 511 positions of the code by 245 positions in order to match a data payload…The encoding operation can include performing the computation p=d′R′, where p is a parity row vector of 9 bits, d′ is a data row vector of 257 bits, and R′ is an encoding matrix with 257 rows and 9 columns. The rows of R′ can be a subset of all non-zero patterns with 9 binary elements. Each pattern can correspond to a data position and the patterns linked to the shortened positions may not be in R′.; Sforzin p. 0045-0046).
As per claim 17, KIM1 in view of Kim2 in further view of Iyer teaches the storage device of claim 16,
wherein the transmission parity data includes a bit making a number of 1s in the transmission parity data an even number (The extension of the Hamming code can include adding a checksum bit, thus resulting in the code including parameters n=267, k=257, where there are 10 parity bits including the 1 checksum bit; Sforzin p. 0045)(the parity (even or odd) of a binary vector v can be defined as the binary value: w(v)mod 2), where w(v) is the weight function, i.e., the function returning the number of “1”s in the vector. Therefore, if the number of “1”s in the vector is even, the parity is “0,” while if the number of “1”s in the vector is odd, the parity is “1.”; Sforzin p. 0054).
Claims 4-5, 11-12, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of Kim2, in further view of Iyer in further view of Kern et al (US 20140173386 A1), hereinafter referred as Kern
As per claim 4, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 1,
wherein the first transmission parity data is generated by the storage controller based on shortened Bose-Chaudhuri-Hocquenghem (BCH) code encoding (If L columns of the H matrix of the unshortened BCH code are eliminated, an H matrix of a shortened BCH code of the length n=N-L is obtained. For a shortened code the following applies n=N-L<2.sup.m-1; Kern p. 0033) (A BCH code is a special linear code which may be described by a parity check matrix H and a generator matrix G which may be derived from the parity check matrix. If a code comprises the length N and if it comprises k information bits, then H is an M,N matrix comprising M lines and N columns, wherein M=N-k. The generator matrix G is then a k,N matrix comprising k lines and N columns, and the code comprises M checkbits; Kern p. 0031).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of KIM1 in view of Kim2 in further view of Iyer with the teachings of Kern by configuring the transmission parity data is to be generated by the storage controller based on shortened Bose-Chaudhuri-Hocquenghem (BCH) code encoding.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ Bose-Chaudhuri-Hocquenghem (BCH) code encoding in the system of KIM1 in view of Kim2 in further view of Iyer because Kern teaches forming a shortened BCH code by shortening the parity check matrix so the error correction circuits required here can be improved so that a least possible hardware effort is required and the signal runtime for determining the correction values is as low as possible (Kern p. 0082)
As per claim 5, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 4,
wherein the first transmission parity data includes a bit making a number of 1s in the first transmission parity data an even number (It is possible to supplement the H matrix H by a line of only ones. The additional integration of the overall parity corresponds to an additional line of only ones in the H matrix; Kern p. 0034)(In order to determine whether an even or an odd number of bits has been corrupted, the overall parity…of the data word v' may be used; Kern p. 0104).
As per claim 11, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 8,
wherein the transmission parity data is generated by the storage controller based on shortened Bose-Chaudhuri-Hocquenghem (BCH) code encoding (If L columns of the H matrix of the unshortened BCH code are eliminated, an H matrix of a shortened BCH code of the length n=N-L is obtained. For a shortened code the following applies n=N-L<2.sup.m-1; Kern p. 0033) (A BCH code is a special linear code which may be described by a parity check matrix H and a generator matrix G which may be derived from the parity check matrix. If a code comprises the length N and if it comprises k information bits, then H is an M,N matrix comprising M lines and N columns, wherein M=N-k. The generator matrix G is then a k,N matrix comprising k lines and N columns, and the code comprises M checkbits; Kern p. 0031).
As per claim 12, KIM1 in view of Kim2 in further view of Iyer teaches the operating method of claim 11,
wherein the transmission parity data includes a bit making a number of 1s in the transmission parity data an even number (It is possible to supplement the H matrix H by a line of only ones. The additional integration of the overall parity corresponds to an additional line of only ones in the H matrix; Kern p. 0034)(In order to determine whether an even or an odd number of bits has been corrupted, the overall parity…of the data word v' may be used; Kern p. 0104).
As per claim 18, KIM1 in view of Kim2 in further view of Iyer teaches the storage device of claim 15,
wherein the transmission parity data is generated by the storage controller based on shortened Bose-Chaudhuri-Hocquenghem (BCH) code encoding (If L columns of the H matrix of the unshortened BCH code are eliminated, an H matrix of a shortened BCH code of the length n=N-L is obtained. For a shortened code the following applies n=N-L<2.sup.m-1; Kern p. 0033) (A BCH code is a special linear code which may be described by a parity check matrix H and a generator matrix G which may be derived from the parity check matrix. If a code comprises the length N and if it comprises k information bits, then H is an M,N matrix comprising M lines and N columns, wherein M=N-k. The generator matrix G is then a k,N matrix comprising k lines and N columns, and the code comprises M checkbits; Kern p. 0031).
As per claim 19, KIM1 in view of Kim2 in further view of Iyer teaches the storage device of claim 15,
wherein the transmission parity data is generated by the storage controller based on single-parity-checker (SPC) encoding (It is possible to supplement the H matrix H by a line of only ones. The additional integration of the overall parity corresponds to an additional line of only ones in the H matrix; Kern p. 0034)(In order to determine whether an even or an odd number of bits has been corrupted, the overall parity…of the data word v' may be used; Kern p. 0104).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts of record teach:
LEE et al (US 20220199126 A1) teaches a data processing circuit, in a training mode, to compare a multi-level signal with first and second voltage signals, and to generate data density signals; a counter circuit to count the data density signals to generate counting values; a control circuit to store, in a register set, a voltage range, counting values corresponding to the voltage range and a control code associated with a first level of the first voltage signal and a second level of the second voltage signal
Boelter et al (US 20160092335 A1) teaches monitoring one or more runtime performance characteristics of a link and determining a state of the link based on at least one of the one or more runtime performance characteristics. Additionally, a retraining of the link may be automatically scheduled based on the state of the link. In one example, scheduling the retraining of the link further includes setting one or more retraining parameters.
JANG (US 20250014666 A1) teaches a data processing system including a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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