Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 15 July 2025.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: address decoder in claim 1 support for which was taken as FIG 1: 114 and [0043] of the Specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
ALLOWABLE SUBJECT MATTER
Claim 4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3,5-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated Cypher (US PG PUB No.
As per claim 1, a controller (see FIG 3: 310 and [0064]) configured to copy data from a processor (see FIG 2: 102A and [0042]) to a memory system (see FIG 2: 104A and [0042]), wherein the processor comprises a volatile memory (see FIG 2: 204A and [0042]) and wherein the memory system comprises a persistent memory (see FIG 2: 210A and [0042]), wherein the controller comprises a memory address decoder that is configured to:
receive a first address from the processor (see [0064]), wherein the first address is a physical address for the data to be copied to as utilized by the processor (see [0039]);
translate the first address into a second address taking into account interleaving settings and granularity of the persistent memory, wherein the second address is a shifted version of the first address, and is for the persistent memory (see [0070]); and
provide the second address to a memory controller of the memory system (see [0035]).
[Cypher discloses a memory mapping unit that translates a first address into a second address, where the second address is a shifted version of the first address (see [0061]: “Translating a real cache line address to a physical cache line address can involve cyclically shifting the real address 6 positions to the right, and then adding a fixed offset to the shifted address.”) taking into account interleaving settings and cache line size (see [0057]).]
As per claim 2, the controller according to claim 1,
wherein the first address is based on a first interleaving, wherein the translation of the first address into the second address includes a second interleaving (see [0062]).
As per claim 3, the controller according to claim 1,
wherein the interleaving settings includes granularity and number of devices (see [0061]).
As per claim 5, the controller according to claim 1,
wherein the data to be copied has a size smaller than the interleaving granularity (see [0026]).
As per claim 6, the controller according to claim 1,
wherein the granularity of the volatile memory is different from the granularity of the persistent memory (see [0024]).
As per claim 7, the controller according to claim 1,
wherein a memory addressing scheme of the volatile memory is different from a memory addressing scheme of the persistent memory (see [0064])
As per claim 8, the controller according to claim 1,
wherein the controller is comprised in a central processing unit Cache and Homing Agent (CPU CHA) (see .
As per claim 9, the controller according to claim 1,
wherein the controller is comprised in a Core Memory Controller.
As per claim 10, a method for copying data from a processor to a memory system, wherein the processor comprises a volatile memory and wherein the memory system comprises a persistent memory, wherein the method comprises
receiving a first address from the processor, wherein the first address being is a physical address for the data to be copied to as utilized by the processor (see [0039]);
translating the first address into a second address taking into account interleaving settings and granularity of the persistent memory, wherein the second address is a shifted version of the first address, and is for the persistent memory (see [0070]); and
providing the second address to a memory controller of the memory system (see [0035]).
[Cypher discloses a memory mapping unit that translates a first address into a second address, where the second address is a shifted version of the first address (see [0061]: “Translating a real cache line address to a physical cache line address can involve cyclically shifting the real address 6 positions to the right, and then adding a fixed offset to the shifted address.”) taking into account interleaving settings and cache line size (see [0057]).]
As per claim 11, a computer program product comprising program instructions for performing the method according to claim 10, when executed by one or more processors in a controller (see [0021]).
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
20120054455 : A non-uniform interleaving scheme in a multiple channel DRAM system comprises associating memory data with a memory address, associating address zones to predetermined ranges of memory addresses and associating predetermined interleaving granularities with the address zones. Memory data is interleaved across two or more memory channels such that a predetermined interleaving granularity is applied to each address zone.
20190361807 Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity (Abstract).
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
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