Prosecution Insights
Last updated: October 25, 2026
Application No. 19/203,337

PHOTOELECTRIC CONVERSION SUBSTRATE, RADIATION DETECTION PANEL, AND RADIATION DETECTION MODULE

Non-Final OA §102§103
Filed
May 09, 2025
Priority
Nov 18, 2022 — JP 2022-184689 +2 more
Examiner
SONG, HOON K
Art Unit
2884
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Canon Electron Tubes & Devices Co. Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1326 granted / 1539 resolved
+18.2% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
33 currently pending
Career history
1579
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
38.4%
-1.6% vs TC avg
§102
34.7%
-5.3% vs TC avg
§112
13.1%
-26.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1539 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3 and 7 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Sugawara et al. (US 20020153491). Regarding claim 1, Sugawara teaches a photoelectric conversion substrate comprising: a basement located in an effective area which is effective for detection of radiation, a frame-shaped non-effective area (DA, DB) surrounding the effective area (effective pixel area), and a correction area outside the non-effective area (figure 2); a plurality of gate lines 27 provided above the basement and extending in a first direction; a plurality of data lines 26 provided above the basement, intersecting the plurality of gate lines, and extending in the second direction; a plurality of first thin film transistors (TFT) provided above the basement and located in the effective area, each of the first thin film transistors being electrically connected to one corresponding gate line of the plurality of gate lines and one corresponding data line of the plurality of data lines (figures 10-11); a plurality of first thin film photodiodes (TFT) provided above the basement and located in the effective area, each of the plurality of first thin film photodiodes being electrically connected to one corresponding first thin film transistor of the plurality of first thin film transistors (figures 10-11); a plurality of second thin film (TFT) photodiodes provided above the basement and located in the non- effective area; and a plurality of second thin film transistors provided above the basement and located in the correction area, each of the second thin film transistors being electrically connected to one corresponding gate line of the plurality of gate lines and one corresponding data line of the plurality of data lines (figures 10-11, para 49-55). Regarding claim 2, Sugawara teaches the non-effective area includes: a first non-effective area and a second non- effective area each extending in the second direction, being adjacent to the effective area, and sandwiching the effective area in the first direction; and a third non-effective area and a fourth non- effective area each extending in the first direction, being adjacent to the effective area, and sandwiching the effective area in the second direction (figure 1 and 3A-3B, 10-11). Regarding claim 3, Sugawara teaches the gate line located in the third non-effective area, among the plurality of gate lines, intermittently extends in the third non-effective area, the gate line located in the fourth non-effective area, among the plurality of gate lines, intermittently extends in the fourth non-effective area, the data line located in the first non-effective area, among the plurality of data lines, intermittently extends in the first non-effective area, and the data line located in the second non-effective area, among the plurality of data lines, intermittently extends in the second non-effective area (figure 1 and 3A-3B, 10-11). Regarding claim 7, Sugawara teaches a radiation detection module comprising: a photoelectric conversion substrate (para 7); a drive circuit 18; and a detection circuit (para 41), wherein the photoelectric conversion substrate includes: a basement located in an effective area which is effective for detection of radiation, a frame-shaped non-effective area surrounding the effective area (DA, DB), and a correction area outside the non-effective area; a plurality of gate lines 27 provided above the basement and extending in a first direction; a plurality of data lines 26 provided above the basement, intersecting the plurality of gate lines, and extending in the second direction; a plurality of first thin film transistors (TFT) provided above the basement and located in the effective area, each of the first thin film transistors being electrically connected to one corresponding gate line of the plurality of gate lines and one corresponding data line of the plurality of data lines; a plurality of first thin film photodiodes (TFT) provided above the basement and located in the effective area, each of the plurality of first thin film photodiodes being electrically connected to one corresponding first thin film transistor of the plurality of first thin film transistors; a plurality of second thin film photodiodes (TFT) provided above the basement and located in the non- effective area; and a plurality of second thin film transistors (TFT) provided above the basement and located in the correction area, each of the second thin film transistors being electrically connected to one corresponding gate line of the plurality of gate lines and one corresponding data line of the plurality of data lines, the drive circuit is electrically connected to at least a plurality of gate lines located in the effective area, among the plurality of gate lines, and supplies control signals to the plurality of gate lines located in the effective area, the detection circuit is electrically connected to at least a plurality of data lines located in the effective area, among the plurality of data lines, and receives image data signals based on electric charges converted at the plurality of first thin film photodiodes, and the plurality of second thin film transistors comprise a function of correcting the image data signals (figures 10-11, para 49-55). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugawara in view of Iwata et al. (US 20150028338). Regarding claim 4, Sugawara teaches a radiation detection panel comprising: a photoelectric conversion substrate;, wherein the photoelectric conversion substrate includes: a basement located in an effective area which is effective for detection of radiation, a frame-shaped non-effective area surrounding the effective area, and a correction area outside the non-effective area; a plurality of gate lines provided above the basement and extending in a first direction; a plurality of data lines provided above the basement, intersecting the plurality of gate lines, and extending in the second direction; a plurality of first thin film transistors provided above the basement and located in the effective area, each of the first thin film transistors being electrically connected to one corresponding gate line of the plurality of gate lines and one corresponding data line of the plurality of data lines; a plurality of first thin film photodiodes provided above the basement and located in the effective area, each of the plurality of first thin film photodiodes being electrically connected to one corresponding first thin film transistor of the plurality of first thin film transistors; a plurality of second thin film photodiodes provided above the basement and located in the non- effective area; and a plurality of second thin film transistors provided above the basement and located in the correction area, each of the second thin film transistors being electrically connected to one corresponding gate line of the plurality of gate lines and one corresponding data line of the plurality of data lines, and the layer is provided on the photoelectric conversion substrate and is located in the effective area. However Sugawara fails to teach and a scintillator layer. Iwata teaches a scintillator layer (para 26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adapt the x-ray flat panel of Sugawara with the scintillator layer as taught by Iwata, since it would provide higher resolution. Regarding claim 5, Iwata teaches a light reflective layer provided on the scintillator layer and located in the effective area (para 26). Regarding claim 6, Iwata teaches a moisture-proof cover 67 provided on the photoelectric conversion substrate, the scintillator layer, and the light reflective layer, located in the effective area and the non-effective area, and sealing the scintillator layer and the light reflective layer together with the photoelectric conversion substrate (figure 3). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOON K SONG whose telephone number is (571)272-2494. The examiner can normally be reached M to Th 10am to 7pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Makiya can be reached at 571-272-2273. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HOON K SONG/Primary Examiner, Art Unit 2884
Read full office action

Prosecution Timeline

May 09, 2025
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
95%
With Interview (+8.4%)
2y 4m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1539 resolved cases by this examiner. Grant probability derived from career allowance rate.

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