DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Springett (US20240235269) in view of Yang (US 20210273569)
Re Claims 1, 4, 11, 14 and 19; Springett teaches a wireless power transmitter comprising (11):
a coil (27);
a first node electrically connected to a first side of the coil; Springett teaches half‑bridge node(s) connected to the resonant circuit (, Fig. 1, Node A, ¶[0011], ¶[0027]). The half‑bridge node is the claimed first node.
a second node electrically connected to a second side of the coil; Springett teaches two half‑bridge nodes when using an H‑bridge (Fig. 1, Node B ¶[0021]). In the H‑bridge embodiment, each node connects to a respective side of the coil.
a first transistor (35H) in electrical communication with a first voltage potential and the first node, the first transistor configured to electrically connect the first voltage potential to the first node based on a first command signal;
Springett teaches switching units linking the plus potential to the half‑bridge node (¶[0010]–[0012]. First switching unit corresponds to the claimed first transistor.)
the second transistor (36L) being configured to electrically connect the second voltage potential to the second node based on a second command signal, the first transistor and the second transistor being configured to transition the first node from the first voltage potential toward the second voltage potential and the second node from the second voltage potential toward the first voltage potential based on the first and second command signals during a first half of a switching cycle;
Springett teaches switching units linking the minus potential to the half‑bridge node and alternating node transitions during half‑cycles (¶[0012]–[0016] The first half‑cycle corresponds to Springett’s positive or negative half‑cycle.)
a third transistor (36H) in electrical communication with the first voltage potential and the second node, the third transistor being configured to electrically connect the first voltage potential to the second node based on a third command signal; (Springett teaches the second half‑bridge in the H‑bridge, where the upper switch connects V+ to the second node (¶[0021]).The upper switch of the second half‑bridge is the claimed third transistor.)
a fourth transistor 35Lin electrical communication with the second voltage potential and the first node, the fourth transistor being configured to electrically connect the second voltage potential to the first node based on a fourth command signal, the third transistor and the fourth transistor being configured to transition the first node from the second voltage potential toward the first voltage potential and the second node from the first voltage potential toward the second voltage potential based on the third and fourth command signals during a second half of the switching cycle. (Springett teaches the lower switch of the second half‑bridge connecting V− to the opposite node during the opposite half‑cycle (¶[0021]: This is the complementary switching of the H‑bridge.)
Springett discusses node voltage transitioning during deadtime (¶[0015]–[0017]).
Springett discloses deadtime control, but doesn’t expressly disclose how to do it.
Springett does not disclose a monitor circuit configured to: determine a first time at which a first voltage of the first node crosses a halfway point between the first voltage potential and the second voltage potential; and determine a second time at which a second voltage of the second node crosses the halfway point between the first voltage potential and the second voltage potential; and a feedback circuit that is configured to: adjust a delay of the second command signal based at least in part on one of the first and second times occurring before the other of the first and second times during the first half of the switching cycle; and adjust a delay of the fourth command signal based at least in part on one of the first and second times occurring before the other of the first and second times during the second half of the switching cycle.
Yang teaches determine a first time at which a first voltage of the first node crosses a halfway point between the first voltage potential and the second voltage potential; and determine a second time at which a second voltage of the second node crosses the halfway point between the first voltage potential and the second voltage potential
Yang “COMP” determining t1 and t2 when node voltages cross a threshold (¶[0026]–[0029], Fig. 3-4)Yang’s threshold (high or low) is a midpoint‑based crossing used to determine timing.)
Yang teaches a feedback circuit (Calc) that is configured adjusting delay based on whether t1 < t2 or t1 > t2 (¶[0029]–[0031] Yang’s deadtime/delay adjustment maps directly to the claimed delay adjustment.) to adjust a delay of the fourth command signal based at least in part on one of the first and second times occurring before the other… during the second half of the switching cycle. Yang teaches adjusting delays separately for each half of the switching cycle (claim 11; ¶[0081]–[0084] Fig. 3 and 4) Yang’s per‑half‑cycle delay adjustment corresponds to adjusting the fourth command signal.)
Thus, the skilled artisan would have been motivated to consult the prior art to “fill in the blanks” in the Springett disclosure and find a successful deadtime control method.
Springett teaches the wireless power transmitter, coil, nodes, H‑bridge, and switching behavior.
Yang teaches the monitor circuit, midpoint‑crossing timing detection, and delay adjustment logic. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing of the invention to have combined Springett with Yang in order to improve ZVS reliability and also combining them yields predictable improvements in switching efficiency, reduced EMI, and robust ZVS, which both references identify as goals.
Re Claims 5, 15; Yang discloses wherein: the monitor circuit is configured to determine the first and second times during each of the first and second halves of a current switching cycle of the power transmitter; and the feedback circuit is configured to: adjust the delay of the second command signal for the first half of a future switching cycle of the power transmitter based at least in part on the first and second times determined during the first half of the current switching cycle; and adjust the delay of the fourth command signal for the second half of the future switching cycle of the power transmitter based at least in part on the first and second times determined during the second half of the current switching cycle.
Yang teaches determining t1 and t2 for each half-cycle (¶[0026]–[0028]; FIG. 3–4). Yang explicitly applies this detection during each half of the switching cycle (claim 15 of Yang; ¶[0081]–[0084]). Yang’s per‑half‑cycle detection of threshold crossings directly corresponds to determining first and second times in each half-cycle.
the feedback circuit is configured to adjust the delay of the second command signal for the first half of a future switching cycle… based at least in part on the first and second times determined during the first half of the current switching cycle;
Secondary (Yang): Yang teaches adjusting delay for the next cycle based on whether t1 < t2 or t1 > t2 (¶[0029]–[0031]). Yang applies this adjustment specifically to the first half of the next switching cycle (claim 15 of Yang; ¶[0081]–[0084]). Yang’s adjustment of deadtime/delay for the next cycle’s first half maps directly to adjusting the second command signal delay.
and adjust the delay of the fourth command signal for the second half of the future switching cycle… based at least in part on the first and second times determined during the second half of the current switching cycle. Yang teaches adjusting the delay for the second half of the next switching cycle based on t1/t2 measured during the second half of the current cycle (claim 15 of Yang; ¶[0081]–[0084]). Yang’s per‑half‑cycle delay adjustment corresponds to adjusting the fourth command signal delay for the second half.
Re Claims 6, 16 and 20; Yang discloses wherein the feedback circuit is configured to: increase the delay of the second command signal for the first half of the future switching cycle based at least in part on the first time occurring before the second time during the first half of the current switching cycle; decrease the delay of the second command signal for the first half of the future switching cycle based at least in part on the first time occurring after the second time during the first half of the current switching cycle; increase the delay of the fourth command signal for the second half of the future switching cycle based at least in part on the first time occurring before the second time during the second half of the current switching cycle; and decrease the delay of the fourth command signal for the second half of the future switching cycle based at least in part on the first time occurring after the second time during the second half of the current switching cycle.
Yang teaches increasing delay when t1 < t2 (¶[0029]–[0031]). Yang applies this logic to the first half of the switching cycle (claim 16 of Yang; ¶[0081]–[0084]
Yang’s rule if t1 occurs before t2, increase delay maps directly to this limitation.)
decrease the delay of the second command signal… when the first time occurs after the second time during the first half… Yang teaches decreasing delay when t1 > t2 (¶[0029]–[0031]). Again applied to the first half of the switching cycle (claim 16 of Yang
Yang’s complementary rule if t1 occurs after t2, decrease delay matches this limitation.
increase the delay of the fourth command signal… when the first time occurs before the second time during the second half…)
Yang teaches applying the same t1/t2‑based logic separately for the second half of the switching cycle (claim 16 of Yang; ¶[0081]–[0084] per‑half‑cycle logic directly corresponds to adjusting the fourth command signal in the second half.)
decrease the delay of the fourth command signal… when the first time occurs after the second time during the second half… Yang teaches decreasing delay when t1 > t2 for the second half of the switching cycle (claim 16 of Yang; ¶[0081]–[0084] Interpretation: Yang’s second‑half logic maps directly to this limitation.)
Re Claims 8, 17; Yang teaches fixed‑magnitude delay adjustments:
a magnitude of the adjustment… is fixed at a pre‑determined value (claim 8¶[0084]–[0086] describe limiting and bounding delay adjustments, including fixed‑step increments. Yang’s fixed‑step deadtime/delay adjustment directly corresponds to the claimed fixed at a pre‑determined value. A POSITA would understand Yang’s fixed increment/decrement as the claimed fixed‑magnitude adjustment.)
Re Claims 9, 18; Yang discloses wherein a magnitude of the adjustment to the delays of the second and fourth command signals is determined based on a magnitude of a time difference between the first time and the second time for each of the corresponding first and second halves of the switching cycle.
Determining first time and second time when node voltages cross a threshold (¶[0026]–[0028]).
Computing the difference between these times (t2 − t1) (implicit in ¶[0029]–[0031]).
Adjusting delay magnitude based on the magnitude of the timing difference, not just its sign:
Claim 9 of Yang: “a magnitude of the adjustment… is determined based on a magnitude of a time difference between the first time and the second time.”
Applying this logic separately for each half of the switching cycle (¶[0081]–[0084]).
Thus Yang supplies the missing teaching: variable‑magnitude delay adjustments proportional to timing error.
Re Claim 2, 12; Yang discloses wherein: the delay of the second command signal comprises a delay of a falling edge of the second command signal during the first half of the switching cycle; and the delay of the fourth command signal comprises a delay of a falling edge of the fourth command signal during the second half of the switching cycle.
Yang teaches: Falling‑edge delay for the second command signal (claim 12 of Yang).
Applied during the first half of the switching cycle (¶[0081]–[0084]). Yang’s explicit disclosure of falling‑edge delay for the second command signal maps directly to this limitation. The delay of the fourth command signal comprises a delay of a falling edge… during the second half of the switching cycle.
Falling‑edge delay for the fourth command signal (claim 12 of Yang). Applied during the second half of the switching cycle (¶[0081]–[0084] Yang’s per‑half‑cycle falling‑edge delay adjustment corresponds exactly to the claimed behavior.).
Re Claims 3, 13; Yang discloses wherein the first, second, third and fourth command signals comprise pulse width modulation signals.
Yang explicitly teaches: pulse‑width modulation control units PWM_H and PWM_L (¶[0067]).
the command signals comprise pulse width modulation signals (claim 3).
PWM signals drive the transistors in each half‑bridge (FIG. 2; ¶[0067]–[0069]).
Yang’s explicit PWM disclosure directly satisfies the limitation. A POSITA would understand that Springett’s switching signals are implemented as PWM signals, and Yang confirms this explicitly.
Re Claim 10; Yang discloses wherein the feedback circuit is further configured to, when the delay of the second command signal is reduced to zero, adjust a delay of the first command signal based at least in part on one of the first and second times occurring before the other of the first and second times. ¶¶[0026]–[0027])
Response to Arguments
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive.
1. Applicant argues that Springett does not disclose the monitor circuit and feedback circuit as recited in claim 1.
The Examiner agrees that Springett alone does not disclose all limitations of claim 1. This was already acknowledged in the Office Action, where Yang was cited to address the missing subject matter. In an obviousness analysis, the question is whether Springett in view of Yang collectively teaches or suggests the claimed features. The applicant’s argument does not undermine the combination rationale because Springett provides the switching and timing environment, and Yang provides the timing‑comparison and delay‑adjustment teachings needed to complete the claim.
2. Applicant argues that Yang’s “midpoint” is not a halfway voltage level (VBRIDGE/2) and therefore cannot teach the claimed timing determinations.
Examiner’s response
The applicant distinguishes Yang’s midpoint as a neutral node rather than a numeric halfway voltage level. Even accepting the applicant’s characterization, Yang still teaches the essential technique of:
• identifying a reference level,
• determining when node voltages cross that reference, and
• using the timing of those crossings to control delay.
The claims require determining when node voltages cross a halfway point between two voltage potentials. Yang’s disclosure demonstrates that timing‑based voltage comparison is a known method for controlling delay. Once the prior art teaches comparing node‑voltage crossing times relative to a reference, applying the same comparison to a different reference level such as the halfway point between two potentials falls within the scope of what the combined teachings reasonably suggest.
The applicant has not shown that the claimed timing determination requires a fundamentally different mechanism than the one Yang already describes. The distinction raised concerns the specific reference level used, not the underlying technique.
3. Applicant argues that Yang does not teach determining mismatch between first and second node voltages.
The applicant asserts that Yang does not mention “mismatch.” However, Yang compares timing of voltage‑crossing events to determine whether delay adjustment is needed. Comparing two timing values and acting on their difference is substantively equivalent to determining which event occurs first and by how much. The Federal Circuit recognizes that a reference teaches a limitation when it performs the same function, even if it uses different terminology.
Yang’s timing comparison corresponds to determining relative timing between two node‑voltage events. The applicant’s argument does not demonstrate a substantive difference between the claimed mismatch determination and the comparison already taught by Yang.
4. Applicant argues that Yang’s delay‑time control differs from the claimed delay adjustment.
The applicant states that Yang adjusts timing based on threshold crossings and applies the adjustment in a following cycle, whereas the claimed invention adjusts delay based on relative timing mismatch at a halfway voltage level. Even if Yang applies the adjustment in a subsequent cycle, the underlying principle remains the same: detect voltage‑crossing events, compare their timing, and adjust control signals based on the comparison.
The applicant has not identified any technical distinction in how the timing comparison is used to adjust delay that would separate the claimed feedback behavior from the method Yang already describes. The difference in reference level and the cycle in which the adjustment is applied does not alter the fundamental nature of the timing‑based delay adjustment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL KESSIE whose telephone number is (571)272-4449. The examiner can normally be reached Monday-Friday 8am-5pmEst.
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/DANIEL KESSIE/Primary Examiner, Art Unit 2836
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