DETAILED ACTION
This Office action is in response to the application filed on May 09, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 09, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were filed on May 09, 2025. These drawings are accepted by the Examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over ITOU (U.S. Pub. No. 2021/0265914 A1) in view of Tran et al. (U.S. Pub. No. 2005/0140428 A1).
In re claim 1, ITOU discloses a semiconductor integrated circuit (Figs. 6a), comprising:
high-side transistor which is a PM OS transistor (MH1, MH2); and
an overcurrent detection circuit (150_1, 150_2) configured to compare a current flowing through the high-side transistor with a threshold current (Para. 0090-0096), wherein the overcurrent detection circuit includes:
a voltage-current conversion circuit configured to convert a reference voltage into a reference current;
replica transistor (152) which is a PMOS transistor provided on a path of the reference current output by the voltage-current conversion circuit and including a source (154a) connected to a source of the high-side transistor (Para. 0090-0096); and
a comparator (156) configured to compare a drain voltage of the high-side transistor with a drain voltage of the replica transistor (Para. 0090-0096), and wherein the voltage-current conversion circuit includes:
an input terminal configured to receive the reference voltage (Para. 0090-0096).
ITOU fails to disclose an N M OS transistor which is a native transistor; a first resistor connected between a source of the N M OS transistor and a ground; and a voltage divider circuit including a second resistor and a third resistor connected in series between the input terminal and the ground, and supplying a voltage, which is obtained by dividing the reference voltage, to a gate of the N M OS transistor.
Tran teaches (Fig. 9) a bandgap reference generator, comprising an N M OS transistor (912) which is a native transistor; a first resistor (931) connected between a source of the N M OS transistor and a ground; and a voltage divider circuit (942-943) including a second resistor and a third resistor connected in series between the input terminal and the ground, and supplying a voltage, which is obtained by dividing the reference voltage, to a gate of the N M OS transistor (Para. 0064-0068).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of ITOU to include is a native transistor; a first resistor connected between a source of the N M OS transistor and a ground; and a voltage divider circuit including a second resistor and a third resistor connected in series between the input terminal and the ground, and supplying a voltage, which is obtained by dividing the reference voltage, to a gate of the N M OS transistor, as disclosed in Tran to provide constant voltages and currents over temperature ranges (Para. 0002).
In re claim 6, ITOU discloses wherein the high-side transistor is a switching element of a DC/DC converter (Figs 6A-6B).
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 2, the prior art of record fails to disclose or suggest “wherein the replica transistor includes a plurality of PM OS transistors stacked vertically” in combination with other limitations of the claim.
Regarding to claim 3, the prior art of record fails to disclose or suggest “wherein the overcurrent detection circuit further includes a first switch connected between a drain of the high-side transistor and the source of the high-side transistor” in combination with other limitations of the claim.
Regarding to claim 4, the prior art of record fails to disclose or suggest “wherein the voltage divider circuit further includes a second switch connected in series with the second resistor and the third resistor.” in combination with other limitations of the claim.
Regarding to claim 5, the prior art of record fails to disclose or suggest “wherein the voltage-current conversion circuit further includes a third switch connected in series with the replica transistor” in combination with other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAFAEL O. DE LEÓN DOMENECH whose telephone number is (571)270-0517. The examiner can normally be reached 8:00 a.m. -5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hammond Crystal can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838
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