Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04 August 2025 and 02 October 2025 are being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 5, 7, 8, 18, 19 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
The claims 1, 18 and 20 recite(s) “accessing, by a first host device of the multiple host devices, a compute express link (CXL) memory to obtain data written to the CXL memory by at least a second host device of the multiple host devices; and performing, by the first host device and based on the obtained data, the distributed join.”
Step 1:
The claims as a whole fall within one or more statutory categories.
Step 2A prong 1:
The following limitations are identified as abstract idea(s):
“performing the distributed join”
Joining sets of data into a single set, such as table data, is a process that can be performed in the human mind.
Step 2A prong 2:
This judicial exception is not integrated into a practical application because the claim elements such as accessing a memory to obtain data written to memory appears to be retrieval/receiving of data (i.e. mere data gathering) , such obtaining of information is identified in MPEP 2106.05(g) as insignificant extra-solution activity and does not provide integration into a practical application.
Step 2B:
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements such as “first host device, “multiple host devices”, “compute express link (CXL) memory” and “second host device” appear to be generally linking of the use of the judicial exception to a particular technological environment or field of use, see MPEP 2106.05(h).
Claim(s) 2 and 19 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1:
The claims as a whole fall within one or more statutory categories.
Step 2A prong 1:
The following limitations are identified as abstract idea(s):
See abstract idea for claims 1 and 18 above.
Step 2A prong 2:
This judicial exception is not integrated into a practical application because the claim elements “wherein the CXL memory includes a portion of memory for each host device of the multiple host devices” is directed to generally linking the use of the judicial exception to a particular technological environment, see MPEP 2106.05(h), that includes portion of memory of each host device.
Step 2B:
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements of “portion of memory for each host device” is directed to generally linking the use of the judicial exception to a particular technological environment, see MPEP 2106.05(h), that includes portion of memory of each host device.
Claim(s) 5 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1:
The claims as a whole fall within one or more statutory categories.
Step 2A prong 1:
The following limitations are identified as abstract idea(s):
See abstract idea for claim 1 above.
Step 2A prong 2:
This judicial exception is not integrated into a practical application because the limitation “incrementing a reference counter during accessing of the CXL memory to obtain the data” is directed to adding insignificant extra solution activity to the judicial exception, see MPEP 2106.05(g).
Step 2B:
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception, see Step 2B of claim 1 above.
Claim(s) 7 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1:
The claims as a whole fall within one or more statutory categories.
Step 2A prong 1:
The following limitations are identified as abstract idea(s):
See abstract idea for claim 1 above.
Step 2A prong 2:
This judicial exception is not integrated into a practical application because the limitation “accessing the CXL memory to obtain the data is based on receiving a message from the second host device indicating that the second host device has written to the CXL memory” is directed to adding insignificant extra solution activity to the judicial exception, similar to mere data gathering, see MPEP 2106.05(g).
Step 2B:
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception, see Step 2B of claim 1 above.
Claim(s) 8 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1:
The claims as a whole fall within one or more statutory categories.
Step 2A prong 1:
The following limitations are identified as abstract idea(s):
See abstract idea for claim 1 above.
Step 2A prong 2:
This judicial exception is not integrated into a practical application because the limitation “obtaining the data from a buffer allocated … to the second host device” is directed to adding insignificant extra solution activity to the judicial exception, see MPEP 2106.05(g).
Step 2B:
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements “CXL memory”, “buffer” and “second host device” are directed to generally linking the use of the judicial exception to a particular technological environment, see MPEP 2106.05(h), that includes portion of memory of each host device.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 6 – 9, 13 and 18 – 20 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0036751 A1 issued to Guim Bernat et al (hereinafter Bernat).
As to claim 1, Bernat discloses a computer-implemented method for performing a distributed join in a database system that includes multiple host devices (multiple host devices in a distributed CXL infrastructure, see Bernat: Para. 0007 – 0009, Fig. 4 – Fig. 6), comprising:
accessing, by a first host device of the multiple host devices, a compute express link (CXL) memory to obtain data written to the CXL memory by at least a second host device of the multiple host devices (network device may access, using CXL protocols, the memory of another network device to process a request and to be shared in the memory pool, enabling additional flexibility and pooled memory transactions, the request using CXL.mem or CXL.cache protocol, see Bernat: Para. 0067 – 0068 and Fig. 8); and
performing, by the first host device and based on the obtained data, the distributed join (aggregating, using a CXL switch, memory into a memory pool from the memory of the of the host devices by way of CXL cache protocol, see Bernat: Para. 0057 – 0060, 0064 - 0065).
As to claim 2, Bernat discloses the computer-implemented method of claim 1, wherein the CXL memory includes a portion of memory for each host device of the multiple host devices (the memory of the platforms include portions made available for access by other devices on other platforms in the system and thus shared in the memory pool, see Bernat: Para. 0067 – 0068 and Fig. 8).
As to claim 3, Bernat discloses the computer-implemented method of claim 2, wherein each portion of memory includes, for a given host device associated with the portion of memory (the memory of the platforms include portions made available for access by other devices on other platforms in the system and thus shared in the memory pool, see Bernat: Para. 0067 – 0068 and Fig. 8), data access tables for each pair of host devices including the given host device and one of the other host devices (memory portions including sparse matrices for tracking access requests within the memory pool, see Bernat: Para. 0066 and 0069 – 0075), and wherein accessing the CXL memory to obtain the data is based on polling the portion of memory for the second host device to determine whether a write pointer in the data access table for the second host device for the pair of the first host device and the second host device matches a read pointer of the first host device (accessing the sparse matrix to determine, based on the data pattern, if the read request matches a non-zero pattern to data written in the memory pool in order to reduce additional traffic for reads on zeroed data, see Bernat: Para. 0066 and 0069 – 0075, matching read requests to non-zero values at memory pool address is matching read and write pointers).
As to claim 6, Bernat discloses the computer-implemented method of claim 1, wherein accessing the CXL memory to obtain the data is based on detecting that a test condition indicating that the second host device has written to the CXL memory is successful (use of Bloom filters or other probabilistic data structures to identify attempts to access data within the memory pool, including whether a portion (by address) of the sparse matrix of the memory pool has all 0’s or data written to it, see Bernat: Para. 0071 – 0075, data written to memory is a successful write).
As to claim 7, Bernat discloses the computer-implemented method of claim 1, wherein accessing the CXL memory to obtain the data is based on receiving a message from the second host device indicating that the second host device has written to the CXL memory (identifying written to portions of the pool memory by identifying non-zero values within the sparse matrix for the memory pool portion and updating the Bloom filter, see Bernat: Para. 0066, 0069 – 0075).
As to claim 8, Bernat discloses the computer-implemented method of claim 1, wherein accessing the CXL memory includes obtaining the data from a buffer allocated, in the CXL memory, to the second host device (servicing requests from host using a memory buffer as a memory expansion device to manage service requests sent from the host, see Bernat: Fig. 3C, Para. 0052 – 0057).
As to claim 9, Bernat discloses the computer-implemented method of claim 1, wherein accessing the CXL memory includes copying a portion of contents of the CXL memory into a local memory of the first host device, and obtaining the data from the local memory (caching needed portions of content from the memory pool to the memory of the host device using the CXL.cache subprotocol, see Bernat: Para. 0059 – 0064, Fig. 6, see also 0067 – 0068).
As to claim 13, Bernat discloses the computer-implemented method of claim 1, wherein the distributed join corresponds to a broadcast join, and wherein the obtained data corresponds to a broadcasted build relation generated based on the multiple hosts writing the data to the CXL memory (platforms notify other platforms for sharing of memory ranges and addressing and memory links are written to the pool, see Bernat: Para. 0076), and further comprising probing the broadcasted build relation using one or more probe partitions (updating the Bloom filter when platforms notify of writes, memory links, etc., see Bernat: Para. 0076, and use of Bloom filters or other probabilistic data structures to identify attempts to access data within the memory pool, including whether a portion (by address) of the sparse matrix of the memory pool has all 0’s or data written to it, see Bernat: Para. 0071 – 0075).
Claims 18 and 20 are rejected using similar rational to the rejection of claim 1 above.
Claim 19 is rejected using similar rationale to the rejection of claim 2 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0179799 A1 issued to Erickson et al (hereinafter Erickson).
As to claim 4, Bernat discloses the computer-implemented method of claim 2, however, Bernat does not explicitly disclose wherein each portion of memory includes a parameter for locking the portion of memory, and wherein accessing the CXL memory to obtain the data is based on determining that the parameter for locking the portion of memory for the second host device is set to an unlocked value.
Erickson teaches wherein each portion of memory includes a parameter for locking the portion of memory, and wherein accessing the CXL memory to obtain the data is based on determining that the parameter for locking the portion of memory for the second host device is set to an unlocked value (locking the memory within the memory virtualizer during write operations such as moves between memory of the source and remote locations to ensure coherency with respect to the pages, see Erickson: Para. 0029 – 0030).
Erickson and Bernat are analogous due to their disclosure of managing memory access between devices using CXL protocol.
Therefore, it would have been obvious to one of ordinary skill in the art to modify Bernat’s use of managing a memory pool for a plurality of host devices with Erickson’s use of a locking mechanism for the memory during write operations in order to increase performance of the system by using a memory virtualizer in the migration of pages between higher and lower latency memory installations to contribute to the memory pool (see Erickson: Para. 0022, 0039 – 0040)
As to claim 15, Bernat discloses the computer-implemented method of claim 13, however, Bernat does not explicitly disclose wherein probing the broadcasted build relation is realized by looping over the broadcasted build relation for each tuple of the one or more probe partitions.
Erickson teaches wherein probing the broadcasted build relation is realized by looping over the broadcasted build relation for each tuple of the one or more probe partitions (address/counter tuple for the entries within the LPA table, see Erickson: Para. 0028 and 0035, and loop iterations for tracking counters and migration within/between memory, see Erickson: Para. 0037 – 0040).
Erickson and Bernat are analogous due to their disclosure of managing memory access between devices using CXL protocol.
Therefore, it would have been obvious to one of ordinary skill in the art to modify Bernat’s use of managing a memory pool for a plurality of host devices with Erickson’s use of a loop iterations for managing counters (counter/address tuples) and migrations within the memory pool in order to increase performance of the system by using a memory virtualizer in the migration of pages between higher and lower latency memory installations to contribute to the memory pool (see Erickson: Para. 0022, 0039 – 0040)
Claim(s) 5, 14, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bernat in view of US 2023/0044342 A1 issued to Wilkinson (hereinafter Wilkinson).
As to claim 5, Bernat discloses the computer-implemented method of claim 1, however, Bernat does not explicitly disclose further comprising incrementing a reference counter during accessing of the CXL memory to obtain the data.
Wilkinson teaches further comprising incrementing a reference counter during accessing of the CXL memory to obtain the data (utilization counters for tracking accesses to memory addresses, see Wilkinson: Para. 0020 – 0021, 0027, 0033 – 0037).
Wilkinson and Bernat are analogous due to their disclosure of managing memory access between devices using CXL protocol.
Therefore, it would have been obvious to one of ordinary skill in the art to modify Bernat’s use of managing a memory pool for a plurality of host devices with Wilkinson’s use of counters for tracking memory address access in order to increase performance of the system by reducing data access times for commonly accessed data by mapping data in tier 1 memory (see Wilkinson: Para. 0016).
As to claim 14, Bernat discloses the computer-implemented method of claim 13, however, Bernat does not explicitly disclose further comprising generating, based on the broadcasted build relation, a local hash table, wherein probing the broadcasted build relation includes probing the one or more probe partitions against the local hash table.
Wilkinson teaches further comprising generating, based on the broadcasted build relation, a local hash table (using hash indexes for mapping data to counters to load balance the counters for memory access through the CXL link, see Wilkinson: Para. 0020 – 0021, 0033 – 0035, 0041 – 0044), wherein probing the broadcasted build relation includes probing the one or more probe partitions against the local hash table (accessing the histogram to determine the counters for the allocated memory for the data (pages), see Wilkinson: Para. 0020 – 0021, 0027, 0033 – 0037, 0041 – 0044).
Wilkinson and Bernat are analogous due to their disclosure of managing memory access between devices using CXL protocol.
Therefore, it would have been obvious to one of ordinary skill in the art to modify Bernat’s use of managing a memory pool for a plurality of host devices with Wilkinson’s use of hash indexes for managing counters for tracking memory address access in order to increase performance of the system by reducing data access times for commonly accessed data by mapping data in tier 1 memory (see Wilkinson: Para. 0016).
As to claim 16, Bernat discloses the computer-implemented method of claim 1, however, Bernat does not explicitly disclose wherein the distributed join corresponds to a shared hash table join, and wherein the obtained data corresponds to a shared hash table generated based on the multiple hosts writing a respective portion of the shared hash table to the CXL memory, and further comprising probing one or more probe partitions against the shared hash table.
Wilkinson teaches wherein the distributed join corresponds to a shared hash table join, and wherein the obtained data corresponds to a shared hash table generated based on the multiple hosts writing a respective portion of the shared hash table to the CXL memory (using hash indexes for mapping data to counters to load balance the counters for memory access through the CXL link, see Wilkinson: Para. 0020 – 0021, 0033 – 0035, 0041 – 0044), and further comprising probing one or more probe partitions against the shared hash table (accessing the histogram to determine the counters for the allocated memory for the data (pages), see Wilkinson: Para. 0020 – 0021, 0027, 0033 – 0037, 0041 – 0044).
Wilkinson and Bernat are analogous due to their disclosure of managing memory access between devices using CXL protocol.
Therefore, it would have been obvious to one of ordinary skill in the art to modify Bernat’s use of managing a memory pool for a plurality of host devices with Wilkinson’s use of hash indexes for managing counters for tracking memory address access in order to increase performance of the system by reducing data access times for commonly accessed data by mapping data in tier 1 memory (see Wilkinson: Para. 0016).
As to claim 17, Bernat modified by Wilkinson discloses the computer-implemented method of claim 16, wherein writing, by the first host device, the respective portion of the shared hash table is based on verifying a synchronization mechanism (authenticating and adjusting counters within the histogram data, see Wilkinson: Para. 0033 – 0035 and 0041 – 0044).
Claim(s) 10 – 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bernat in view of US 2012/0310916 A1 issued to Abadi et al (hereinafter Abadi).
As to claim 10, Bernat discloses the computer-implemented method of claim 1, however Bernat does not explicitly disclose wherein the distributed join corresponds to a repartition join, and wherein the obtained data corresponds to at least one build partition of multiple build partitions or at least one probe partition of multiple probe partitions using at least the obtained data based on a join key.
Abadi teaches wherein the distributed join corresponds to a repartition join (distributed (repartitioned) joined in the distributed database system, see Abadi: Para. 0078), and wherein the obtained data corresponds to at least one build partition of multiple build partitions or at least one probe partition of multiple probe partitions using at least the obtained data based on a join key (repartitioning multiple table partitions that are to be repartitioned by the same join key, see Abadi: Para. 0083).
Abadi and Bernat are analogous due to their disclosure of managing memory access between devices using a memory/buffer pool.
Therefore, it would have been obvious to one of ordinary skill in the art to modify Bernat’s use of managing a memory pool for a plurality of host devices with Abadi’s use of repartitioning of multiple partitions using the same join key in order to increase performance of the system by providing a more efficient data processing for obtaining large-size data from even bigger data sets stored in databases through execution of requests and queries (see Abadi: Para. 0010).
As to claim 11, Bernat modified by Abadi discloses the computer-implemented method of claim 10, further comprising generating a local hash table on one or more of the multiple build partitions, and probing a matching one or more of the multiple probe partitions based on the local hash table (generating global and local hash tables to ensure better load balancing when executing processing tasks over the stored data, see Abadi: Para. 0066 – 0067, 0079 – 0080, 0086, and probing the hash tables to find the data, see Abadi: Para. 0091).
As to claim 12, Bernat modified by Abadi discloses the computer-implemented method of claim 10, further comprising probing one or more of the multiple build partitions by looping over the one or more of the multiple build partitions for each tuple in a matching one or more of the multiple probe partitions (automatically repartitioning based on the join attribute of each tuples as the key and the rest of the tuple as the value, see Abadi: Para. 0083).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK E HERSHLEY whose telephone number is (571)270-7774. The examiner can normally be reached M-F: 9am-6pm.
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/MARK E HERSHLEY/Primary Examiner, Art Unit 2164