DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 3, 7 – 8, 11, 14 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over OH US Patent Application Publication No. 2020/0042460 (originally cited in IDS filed 5/9/2025, herein after referred to as OH) in view of Pal et al. US Patent Application Publication No. 2022/0269433 (herein after referred to as Pal).
Regarding claims 1 and 18, OH describes a storage system comprising [and an operating method of a storage system]: a host (Host 102 of Fig. 1 and Fig. 6); a memory connected to the host (Memory 106 of Fig. 6); a connection configured to communicate with the host (Fig. 1 shows the connection between the Host 102 and the devices 110A, 110B, and 110C); a storage device (memory system 110A of Fig. 1 (page 6, paragraph [0088])) including a nonvolatile memory (NAND 152, 154, 156, 158 of Fig. 1), an internal buffer memory (…a map manager (MM) 44… The map manager (MM) 44 can handle or control map data… The host request manager (HRM) 46 can send an inquiry request to the map data manager (MM) 44, to determine a physical address corresponding to the logical address… (page 9, paragraphs [0121] – [0122])), and a storage controller configured to control the nonvolatile memory and the internal buffer memory and to communicate with the host through the connection (Controller 130 of Fig. 1. The controller 130 may control storage of data in the memory device 150 (page 6, paragraph [0094]). …the controller 130 includes a host interface 132, a flash translation layer (FTL) 40… (page 9, paragraph [0116]). …the flash translation layer (FTL) 40 can include… a map manager (MM) 44… The map manager (MM) 44 can handle or control map data (page 9, paragraph [0121])); and a memory device including a buffer memory and a memory controller configured to control the buffer memory and to communicate with the host through the connection (…devices 110A, 110B, and 110C of Fig. 1 are similar components, also including NAND memory 152, controller 130, and map manager 44 as described above), wherein the storage controller is configured to receive a first read request including a first address from the host through the connection, wherein the storage controller is configured to read first map data corresponding to the first address from the internal buffer memory in response to the first map data being stored in the internal buffer memory (The system can include a host transmitting a read, write, or erase command into the at least one memory system. In another example, the system can further include a metadata translator configured to perform address translation based on the map table. The map table can include mapping information used for translating a logical address into a physical address (page 2, paragraphs [0035] – [0036]). Therefore, the controller 130 may map a logical address, which is entered from the host 102, with a physical address of the memory device 150 through the map data (page 8, paragraph [0110]). …the host request manager (HRM) 46 can use the map manager (MM) 44 and the block manager 48 to handle or process requests according to the read and program commands, and the events which are delivered from the host interface 132. The host request manager (HRM) 46 can send an inquiry request to the map data manager (MM) 44, to determine a physical address corresponding to the logical address which is entered with the events (page 9, paragraph [0122])), wherein the storage controller is configured to send a second read request to another memory through the connection in response to the first map data not being stored in the internal buffer memory (However, if the controller in the first memory system 110A does not find the metadata associated with the logical address, the controller may request the metadata corresponding to the logical address at the host controller interface 108 (page 19, paragraph [0216])), and receive the first map data from the memory device through the connection, and store the first map data in the internal buffer memory (Instead of reading metadata from the nonvolatile memory device for the address translation that can be performed by the first memory system 110A having the highest priority among the plurality of memory systems 110A, 110B, 110C, the metadata stored in the host memory 106 can be delivered into the first memory system 110A from the host. There is an advantage that the first memory system 110A can is more quickly obtain the metadata used for the address translation (page 19, paragraph [0220])), and wherein the storage controller is configured to read first data from the nonvolatile memory based on the first map data in response to the first read request, and output the first data to the host through the connection (The first memory system 110A may translate the logical address to a physical address based on the transferred metadata… One of the plurality of memory systems 110A, 110B, 110C receiving the physical address and the read command can access a specific location corresponding to the physical address and transfer data outputted from the specific location to the host memory 106 (page 19, paragraphs [0217] – [0219])). OH does not specifically disclose that the connection between devices is a switch, nor that the second read is directed to the memory device.
OH describes that a “second read” is directed to the host (…However, if the controller in the first memory system 110A does not find the metadata associated with the logical address, the controller may request the metadata corresponding to the logical address at the host controller interface 108. The host controller interface 108 may transfer a portion of the metadata stored in the host memory 106, which corresponds to the logical address, into the first memory system 110A (page 19, paragraphs [0216] – [0217])), as opposed to a “memory device”. However, the host memory 106 is identified as a volatile memory (Since the memory 106 in the host 102 is a type of volatile memory… (page 15, paragraph [0163])) just as the memory 144 in memory devices 110B and 110C (The memory 144 may be implemented with a volatile memory (page 8, paragraph [0107])). Furthermore the host and memory devices 110A, 110B, and 110C are all connected by the same connection (see Fig. 1). Therefore, storing and requesting the mapping information from the memory 144 located in devices 110B and 110C (RAM 144), being similar in function and network location to the host memory 106, would be an obvious substitution and one of ordinary skill in the art would expect predictable results.
Pal describes a computer system in which multiple peer devices may be coupled downstream of a switch. The switch device may enable certain peer communications between these devices with reduced latency. Such communications may proceed from initiator peer device directly through the switch device to the target peer device, without passing through a host or other upstream device (page 1, paragraph [0011]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Pal teachings in the OH system. Skilled artisan would have been motivated to incorporate the method of connecting peer devices via switch as taught by Pal in the OH system for effectively providing reduced latency peer-to-peer communication. Additionally, a switch is a well-known and conventional type of multi participant interface that would be obvious to connect a host to several storage/memory devices. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as host/memory/storage component communication. This close relation between both of the references highly suggests an expectation of success.
Regarding claims 2 and 19, OH in view of Pal describe the storage system of claim 1 [and the method of claim 18] (see above), wherein the storage controller is configured to receive a first write request including a second data and a second address (The system can include a host transmitting a read, write, or erase command into the at least one memory system… (OH, page 2, paragraph [0035]). The controller 130 may store the data, provided by the host 102, into the memory device 150 (OH, page 7, paragraph [0099]). Also, through the address mapping operation based on the map data, when the controller 130 tries to update data stored in a particular page, the controller 130 may program the updated data on another empty page and may invalidate old data of the particular page (e.g., update a physical address, corresponding to a logical address of the updated data, from the previous particular page to the another newly programmed page) due to a characteristic of a flash memory device. Further, the controller 130 may store map data of the new data into the FTL (OH, page 8, paragraph [0110])) through the switch from the host (As described by Pal), wherein the storage controller is configured to write the second data into the nonvolatile memory based on the second address in response to the first write request (The controller 130 may store the data, provided by the host 102, into the memory device 150 (OH, page 7, paragraph [0099])), and wherein the storage controller is configured to generate a second map data based on the second address and write the second map data into the internal buffer memory (Also, through the address mapping operation based on the map data, when the controller 130 tries to update data stored in a particular page, the controller 130 may program the updated data on another empty page and may invalidate old data of the particular page (e.g., update a physical address, corresponding to a logical address of the updated data, from the previous particular page to the another newly programmed page) due to a characteristic of a flash memory device. Further, the controller 130 may store map data of the new data into the FTL (OH, page 8, paragraph [0110])).
Regarding claims 3 and 20, OH in view of Pal describe the storage system of claim 2 [and the method of claim 19] (see above), wherein the storage controller is configured to send a second write request including the second map data through the switch to the memory device (The controller 130 may send the metadata that needs to be updated [to the host] (OH, page 15, paragraph [0171]). It is obvious that the updated mapping data would be sent to the secondary device storing mapping data (as described in claim 1 above)).
Regarding claim 7, OH in view of Pal describe the storage system of claim 1 (see above), further comprising: a second storage device (memory system 110B or 110C of Fig. 1 (OH, page 6, paragraph [0088])) including a second nonvolatile memory (NAND 152, 154, 156, 158 of OH, Fig. 1), a second internal buffer memory (…a map manager (MM) 44… The map manager (MM) 44 can handle or control map data… The host request manager (HRM) 46 can send an inquiry request to the map data manager (MM) 44, to determine a physical address corresponding to the logical address… (OH, page 9, paragraphs [0121] – [0122])), and a second storage controller configured to control the second nonvolatile memory and the second internal buffer memory (Controller 130 of Fig. 1. The controller 130 may control storage of data in the memory device 150 (OH, page 6, paragraph [0094]). …the controller 130 includes a host interface 132, a flash translation layer (FTL) 40… (OH, page 9, paragraph [0116]). …the flash translation layer (FTL) 40 can include… a map manager (MM) 44… The map manager (MM) 44 can handle or control map data (OH, page 9, paragraph [0121]). Memory devices 110A, 110B, 110C are similar components) and to communicate through the switch with the host (Fig. 1 of OH shows the connection between Host 102 and devices 110A, 110B, and 110C. Pal describes that a switch may be used to connect multiple components similarly (see claim 1 above)), wherein the second storage controller is configured to receive a third read request including a second address through the switch from the host, wherein the second storage controller is configured to read a second map data corresponding to the second address from the second internal buffer memory in response to the second map data being stored in the second internal buffer memory (The system can include a host transmitting a read, write, or erase command into the at least one memory system. In another example, the system can further include a metadata translator configured to perform address translation based on the map table. The map table can include mapping information used for translating a logical address into a physical address (OH, page 2, paragraphs [0035] – [0036]). Therefore, the controller 130 may map a logical address, which is entered from the host 102, with a physical address of the memory device 150 through the map data (OH, page 8, paragraph [0110]). …the host request manager (HRM) 46 can use the map manager (MM) 44 and the block manager 48 to handle or process requests according to the read and program commands, and the events which are delivered from the host interface 132. The host request manager (HRM) 46 can send an inquiry request to the map data manager (MM) 44, to determine a physical address corresponding to the logical address which is entered with the events (OH, page 9, paragraph [0122]). Memory devices 110A, 110B, 110C are similar devices and expected to operate similarly with read requests directed to them), wherein the second storage controller is configured to send a fourth read request (However, if the controller in the first memory system 110A does not find the metadata associated with the logical address, the controller may request the metadata corresponding to the logical address at the host controller interface 108 (OH, page 19, paragraph [0216]). Memory devices 110A, 110B, 110C are similar devices and expected to operate similarly with read requests directed to them) through the switch to the memory device in response to the second map data not being stored in the second internal buffer memory (As previously explained with respect to claim 1 above, any other memory located in devices 110B and 110C (RAM 144) is just as capable of storing L2P mapping data and as disclosed by OH, reading from RAM would be faster than reading from NAND. It would be obvious to try storing the map data in one of the other RAMs present in the invention of OH.), and receive the second map data through the switch from the memory device, and store the second map data in the second internal buffer memory (Instead of reading metadata from the nonvolatile memory device for the address translation that can be performed by the first memory system 110A having the highest priority among the plurality of memory systems 110A, 110B, 110C, the metadata stored in the host memory 106 can be delivered into the first memory system 110A from the host. There is an advantage that the first memory system 110A can is more quickly obtain the metadata used for the address translation (OH, page 19, paragraph [0220])), and wherein the storage controller is configured to read second data from the second nonvolatile memory based on the second map data in response to the third read request, and output the second data through the switch to the host (The first memory system 110A may translate the logical address to a physical address based on the transferred metadata… One of the plurality of memory systems 110A, 110B, 110C receiving the physical address and the read command can access a specific location corresponding to the physical address and transfer data outputted from the specific location to the host memory 106 (OH, page 19, paragraphs [0217] – [0219])).
Regarding claim 8, OH in view of Pal describe the storage system of claim 1 (see above), further comprising: a second memory device including a second buffer memory and a second memory controller configured to control the second buffer memory and to communicate through the switch with the host (…devices 110A, 110B, and 110C of OH, Fig. 1 are similar components, also including NAND memory 152, controller 130, and map manager 44 as described above. Communication through a switch is similarly obvious in view of Pal as explained in claim 1 above).
Regarding claim 11, OH in view of Pal describe the storage system of claim 8 (see above), further comprising: a second storage device including a second nonvolatile memory, a second internal buffer memory, and a second storage controller configured to control the second nonvolatile memory and the second internal buffer memory and to communicate through the switch with the host (…devices 110A, 110B, and 110C of OH, Fig. 1 are similar components, also including NAND memory 152, controller 130, and map manager 44 as described above. Communication through a switch is similarly obvious in view of Pal as explained in claim 1 above. As an amount of data to be stored or handled by the user increases, the number of memory systems 110A, 110B, 110C associated or engaged with the host 102 in the data processing system may increase (OH, page 4, paragraph [0059])).
Regarding claim 14, OH in view of Pal describe the storage system of claim 1 (see above), wherein the memory controller divides the buffer memory into a first area and a second area, stores the first map data in the first area, and permits the host to access the second area through the switch (In Fig. 6, the memory system 110 can use the host memory 106 included in the host 102 as a cache memory for temporarily storing metadata 166, but the memory system 110 described in Fig. 9 may use the host memory 106 included in the host 102 as a buffer for storing user data 168. In Fig. 9, a case when the host memory 106 included in the host 102 stores the user data 168 is described… (OH, page 16, paragraph [0174])).
Regarding claim 15, OH describes a storage device comprising (memory system 110A of Fig. 1 (page 6, paragraph [0088])): a nonvolatile memory (NAND 152, 154, 156, 158 of Fig. 1); an internal buffer memory (…a map manager (MM) 44… The map manager (MM) 44 can handle or control map data… The host request manager (HRM) 46 can send an inquiry request to the map data manager (MM) 44, to determine a physical address corresponding to the logical address… (page 9, paragraphs [0121] – [0122])); and a storage controller configured to control the nonvolatile memory and the internal buffer memory (Controller 130 of Fig. 1. The controller 130 may control storage of data in the memory device 150 (page 6, paragraph [0094]). …the controller 130 includes a host interface 132, a flash translation layer (FTL) 40… (page 9, paragraph [0116]). …the flash translation layer (FTL) 40 can include… a map manager (MM) 44… The map manager (MM) 44 can handle or control map data (page 9, paragraph [0121])), to communicate with an external connection (Fig. 1 shows the connection between the Host 102 and the devices 110A, 110B, and 110C), wherein the nonvolatile memory includes user data (…the first memory system 100A may include… as well as a user data block 40_3… (page 18, paragraph[ 0198])) and map data (…the first memory system 100A may include a metadata block 40_2… (page 18, paragraph [0198]). …metadata (L2P MAP)… (page 18, paragraph [0207])), wherein the map data includes a plurality of address pairs in which logical block addresses are mapped to physical block addresses (…first map data, including an L2P map table or an L2P map list in which logical information as the mapping information between logical addresses and physical addresses for the user data stored in the memory blocks are recorded… (page 11, paragraph [0134])), wherein the storage controller is configured to receive a first read request including a first logical address from the external connection, wherein the storage controller is configured to read first map data corresponding to the first logical address from the internal buffer memory in response to the first map data being stored in the internal buffer memory (The system can include a host transmitting a read, write, or erase command into the at least one memory system. In another example, the system can further include a metadata translator configured to perform address translation based on the map table. The map table can include mapping information used for translating a logical address into a physical address (page 2, paragraphs [0035] – [0036]). Therefore, the controller 130 may map a logical address, which is entered from the host 102, with a physical address of the memory device 150 through the map data (page 8, paragraph [0110]). …the host request manager (HRM) 46 can use the map manager (MM) 44 and the block manager 48 to handle or process requests according to the read and program commands, and the events which are delivered from the host interface 132. The host request manager (HRM) 46 can send an inquiry request to the map data manager (MM) 44, to determine a physical address corresponding to the logical address which is entered with the events (page 9, paragraph [0122])), wherein the storage controller is configured to send a second read request to the external connection to access an external memory in response to the first map data not being stored in the internal buffer memory (However, if the controller in the first memory system 110A does not find the metadata associated with the logical address, the controller may request the metadata corresponding to the logical address at the host controller interface 108 (page 19, paragraph [0216])), and receive the first map data through the external connection from the external memory, and store the first map data in the internal buffer memory (Instead of reading metadata from the nonvolatile memory device for the address translation that can be performed by the first memory system 110A having the highest priority among the plurality of memory systems 110A, 110B, 110C, the metadata stored in the host memory 106 can be delivered into the first memory system 110A from the host. There is an advantage that the first memory system 110A can is more quickly obtain the metadata used for the address translation (page 19, paragraph [0220])), and wherein the storage controller is configured to read first data from the nonvolatile memory based on the first map data in response to the first read request, and output the first data to the external connection (The first memory system 110A may translate the logical address to a physical address based on the transferred metadata… One of the plurality of memory systems 110A, 110B, 110C receiving the physical address and the read command can access a specific location corresponding to the physical address and transfer data outputted from the specific location to the host memory 106 (page 19, paragraphs [0217] – [0219])). OH does not specifically disclose that the connection between devices is a switch, nor that the second read is directed to an external memory device.
OH describes that a “second read” is directed to the host (…However, if the controller in the first memory system 110A does not find the metadata associated with the logical address, the controller may request the metadata corresponding to the logical address at the host controller interface 108. The host controller interface 108 may transfer a portion of the metadata stored in the host memory 106, which corresponds to the logical address, into the first memory system 110A (page 19, paragraphs [0216] – [0217])), as opposed to a “memory device”. However, the host memory 106 is identified as a volatile memory (Since the memory 106 in the host 102 is a type of volatile memory… (page 15, paragraph [0163])) just as the memory 144 in memory devices 110B and 110C (The memory 144 may be implemented with a volatile memory (page 8, paragraph [0107])). Furthermore the host and memory devices 110A, 110B, and 110C are all connected by the same connection (see Fig. 1). Therefore, storing and requesting the mapping information from the memory 144 located in devices 110B and 110C (RAM 144), being similar in function and network location to the host memory 106, would be an obvious substitution and one of ordinary skill in the art would expect predictable results.
Pal describes a computer system in which multiple peer devices may be coupled downstream of a switch. The switch device may enable certain peer communications between these devices with reduced latency. Such communications may proceed from initiator peer device directly through the switch device to the target peer device, without passing through a host or other upstream device (page 1, paragraph [0011]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Pal teachings in the OH system. Skilled artisan would have been motivated to incorporate the method of connecting peer devices via switch as taught by Pal in the OH system for effectively providing reduced latency peer-to-peer communication. Additionally, a switch is a well-known and conventional type of multi participant interface that would be obvious to connect a host to several storage/memory devices. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as host/memory/storage component communication. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 16, OH in view of Pal describe the storage device of claim 15 (see above), wherein the storage controller is configured to receive a first write request including a second data and a second logical address (The system can include a host transmitting a read, write, or erase command into the at least one memory system… (OH, page 2, paragraph [0035]). The controller 130 may store the data, provided by the host 102, into the memory device 150 (OH, page 7, paragraph [0099]). Also, through the address mapping operation based on the map data, when the controller 130 tries to update data stored in a particular page, the controller 130 may program the updated data on another empty page and may invalidate old data of the particular page (e.g., update a physical address, corresponding to a logical address of the updated data, from the previous particular page to the another newly programmed page) due to a characteristic of a flash memory device. Further, the controller 130 may store map data of the new data into the FTL (OH, page 8, paragraph [0110])) from the external switch (As described by Pal), wherein the storage controller is configured to write the second data into the nonvolatile memory based on the second logical address in response to the first write request (The controller 130 may store the data, provided by the host 102, into the memory device 150 (OH, page 7, paragraph [0099])), and wherein the storage controller is configured to generate a second map data based on the second logical address and write the second map data into the internal buffer memory (Also, through the address mapping operation based on the map data, when the controller 130 tries to update data stored in a particular page, the controller 130 may program the updated data on another empty page and may invalidate old data of the particular page (e.g., update a physical address, corresponding to a logical address of the updated data, from the previous particular page to the another newly programmed page) due to a characteristic of a flash memory device. Further, the controller 130 may store map data of the new data into the FTL (OH, page 8, paragraph [0110])).
Regarding claim 17, OH in view of Pal describe the storage device of claim 16 (see above), wherein the storage controller is configured to send a second write request including the second map data to the external switch to access the external memory device (The controller 130 may send the metadata that needs to be updated [to the host] (OH, page 15, paragraph [0171]). It is obvious that the updated mapping data would be sent to the secondary device storing mapping data (as described in claim 1 above)).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over OH in view of Pal, further in view of Kim US Patent Application Publication No. 2021/0232343 (herein after referred to as Kim).
Regarding claim 4, OH in view of Pal describe the storage system of claim 1 (see above). While OH makes it clear that the metadata [such as L2P MAP] stored in volatile memory may disappear when an event such as interruption of power supply to the host occurs (OH, page 15, paragraph [0163]), it does not specifically disclose wherein, before performing a power-off operation, the storage controller is configured to send a third read request through the switch to the memory device, receive map data stored in the memory device through the switch from the memory device, and update the map data into the nonvolatile memory.
Kim describes a nonvolatile memory storage device. When power is on, the memory controller 1200 may read logical-physical address mapping information stored in the nonvolatile memory device 1100 and load the read logical-physical address mapping information to the buffer memory device 1300. In addition, the memory controller 1200 may flush logical-physical address mapping information stored in the buffer memory device 1300 to the nonvolatile memory device 1100. In an embodiment, the logical-physical address mapping information is flushed to the nonvolatile memory device 1100 before power is off to prevent the logical-physical address mapping information stored in the buffer memory device 1300 from being lost (page 6, paragraph [0092]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Kim teachings in the OH in view of Pal system. Skilled artisan would have been motivated to incorporate the method of flushing mapping information from volatile memory locations to nonvolatile memory before power-off as taught by Kim in the OH in view of Pal system for effectively preventing mapping data loss. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as storage memory devices. This close relation between both of the references highly suggests an expectation of success.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over OH in view of Pal and Kim, further in view of Lin US Patent Application Publication No. 2019/0188125 (herein after referred to as Lin).
Regarding claim 5, OH in view of Pal and Kim describe the storage system of claim 4 (see above). While Kim discloses that the logical-physical address mapping information is flushed to the nonvolatile memory device before power is off (Kim, page 6, paragraph [0092]), it does not specifically disclose wherein the storage controller is configured to send the third read request in response to receiving a power off information through the switch from the host.
Lin describes a data storage device. Specifically, when the host device 200 issues a Power Off Notification (PON) command to the controller 110A/110B, the content of the first mapping table may be updated to the H2F (that is, the second mapping table) and/or the F2H table (that is, the third mapping table) stored in the memory device 120 (page 4, paragraph [0041]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Lin teachings in the OH in view of Pal and Kim system. Skilled artisan would have been motivated to incorporate the method of flushing mapping information from volatile memory locations to nonvolatile memory based on power-off notification from a host as taught by Lin in the OH in view of Pal and Kim system for effectively providing an indication of when the host actually requires a power-off procedure. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as storage memory devices. This close relation between both of the references highly suggests an expectation of success.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over OH in view of Pal and Kim, further in view of Delaney et al. US Patent Application Publication No. 2017/0315889 (herein after referred to as Delaney).
Regarding claim 6, OH in view of Pal and Kim describe the storage system of claim 4 (see above). They do not explicitly disclose wherein the storage controller is configured to send an acknowledgement through the switch to the host after updating the map data into the nonvolatile memory.
Delaney describes a system with a solid state drive. Specifically, after the SSD controller 101 completes each of steps 505, 507, 509 and 511, the SSD controller 101 may be programmed to send an acknowledgement signal to the secondary controller 107 indicating that a particular step of the power loss procedure completed. If the secondary controller 107 receives an acknowledgement from the SSD controller 101, the secondary controller 107 may store the acknowledgement in second non-volatile memory 143 after the completion of the respective step.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Delaney teachings in the OH in view of Pal and Kim system. Skilled artisan would have been motivated to incorporate the method of sending acknowledgment of completion as taught by Delaney in the OH in view of Pal and Kim system for effectively providing an indication of step completion during a power-off procedure. Additionally, acknowledgment/completion signals are well-known and conventional in the art as a way to communicate that essential steps have been completed before moving on to another step. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as storage memory devices. This close relation between both of the references highly suggests an expectation of success.
Allowable Subject Matter
Claims 9 – 10 and 12 – 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 9 describes, “the storage system of claim 8, wherein in response to the first map data not being stored in the internal buffer memory, the storage controller is configured to determine whether the first map data is stored in the memory device or the second memory device, and based on the determination, send the second read request including the first address through the switch to the memory device or the second memory device”. Claim 10 describes, “the storage system of claim 8, wherein the storage controller is configured to store at least a portion of a map data of the storage device through the switch into the memory device, and store at least another portion of the map data of the storage device through the switch into the second memory device”. Claim 12 describes, “the storage system of claim 11, wherein the storage controller is configured to store map data of the storage device through the switch into the memory device, and the second storage controller is configured to store map data of the second storage device through the switch into the second memory device”. Claim 13 describes, “the storage system of claim 11 (see above), wherein the storage controller is configured to store at least a portion of the map data of the storage device through the switch into the memory device, and store at least another portion of the map data of the storage device through the switch into the second memory device, and wherein the second storage controller is configured to store at least a portion of map data of the second storage device through the switch into the memory device, and store at least another portion of the map data of the second storage device through the switch into the second memory device”. The prior art of record cited above does not teach or suggest the additional limitations presented in the claims. Byun et al. US Patent Application Publication No. 2020/0334166 (originally cited in IDS filed 5/9/2025) describes a memory system for utilizing a memory included in an external device. When a map cache miss occurs while processing inquiry or update requests, the map manager may send a read request to the memory interface to load a relevant mapping table stored in the memory device (page 11, paragraph [0130]). However, Byun does not teach or suggest the additional limitations presented in the claims. Lee et al. US Patent Application Publication No. 2023/0028071 describes a memory module in a system. The system memory map may include a device memory area (a), which may also be referred to as a CXL memory area, a host memory area (b), and a hole area (c) which may not be a memory area. The system memory map may include an upper memory address and a lower memory address for each area (page 6, paragraph [0078]). However, Lee does not teach or suggest the additional limitations presented in the claims. Kakaiya et al. US Patent Application Publication No. 2022/0405212 describes a system for secure direct peer-to-peer memory access requests between devices. Circuitry may also be configured to determine if the translated access request misses the memory protection cache (MPC) based on information received in the translated access request and, if so determined, request the memory protection unit (MPU) of the host to fill in memory protection information for the translated access request. For example, the circuitry may be configured to notify a requestor to retry the translated access request that misses the MPC, along with hold-off information (page 4, paragraph [0040]). However, Kakaiya does not teach or suggest the additional limitations presented in the claims. Tsirkin US Patent Application Publication No. 2022/0358049 describes memory access handling for peripheral component interconnect devices. If a memory access request is unable to be translated on-device IOMMU (e.g., due to missing translation records in IOMMU page table), the memory access request may be translated by system IOMMU and then access host memory. Accordingly, memory mapping module may then cache the translation data associated with the memory access request and update IOMMU page table (page 5, paragraph [0043]). However, Tsirkin does not teach or suggest the additional limitations presented in the claims. Kaburaki et al. US Patent Application Publication No. 2019/0235762 describes a memory system controlling nonvolatile memory. When a cache miss has occurred, it becomes possible to fill, instead of filling the entirety of one cache line of the address translation table cache 31, only a part (e.g., one sub-line) of this one cache line (page 5, paragraph [0095]). However, Kaburaki does not teach or suggest the additional limitations presented in the claims.
Conclusion
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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July 25, 2026
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