DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is in response to communications filed 05/09/2025 and 07/16/2025.
The Examiner acknowledges the Preliminary Amendments filed 07/16/2025.
Claim 1 is cancelled.
Claims 2-21 are added.
Claims 2-21 are pending.
Claims 2-21 are rejected.
The Examiner notes the current action does not include prior art rejections over the current presentation of the claims. The cited relevant prior art references made of record below are considered as pertinent to the claims and disclosed details provided in the Specification.
The claims are subject to the objections and rejections provided herein which must be addressed accordingly.
Priority
Applicant’s priority claim as a continuation of US Application 17/892,661 filed 01/11/2024, now US Patent No. 12,307,096, is herein acknowledged.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement dated 05/09/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Drawings
The applicant’s drawings submitted on 05/09/2025 are acceptable for examination purposes.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 12,307,096, hereinafter referred to as “Patent”, in view of Yang et al. (US 2022/0382454). In view of Yang, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the writing of data to a first zone as related to a multiple-level memory cell cursor instead of the single-level memory cell cursor as claimed in the Patent as Yang discloses handling writing to a plurality of zones as represented by a plurality of cell configurations including SLC, MLC, TLC, and QLC as discussed in Paragraph [0065]. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are a broader recitation of those in the US Patent as demonstrated by the comparison below.
Instant Application
US Patent 12,307,096
A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive a first command to write first information to a first zone of the memory system; write, based at least in part on receiving the first command, the first information to the first zone of the memory system; determine a first rate at which the first information is written to the first zone of the memory system; determine that the first rate satisfies a threshold rate associated with a first multiple-level memory cell cursor of a plurality of cursors; and assign the first zone of the memory system to the first multiple-level memory cell cursor of the plurality of cursors associated with the memory system based at least in part on determining that the first rate satisfies the threshold rate.
A memory system, comprising: one or more memory devices comprising non-volatile memory cells; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive a first command to write first information associated with a first type of information of a plurality of types of information to a first zone of the memory system, the first zone for storing the first type of information and corresponding to a first range of logical addresses of the memory system; write, based at least in part on receiving the first command, the first information to a first set of memory cells corresponding to a single-level memory cell cursor of a plurality of cursors associated with the memory system, the first set of memory cells within the first zone of the memory system; close the first zone from being written with additional information based at least in part on writing the first information; determine, in response to closing the first zone, that a first rate at which the first type of information is written to the memory system satisfies a threshold rate associated with a multiple-level memory cell cursor of the plurality of cursors; receive, based at least in part on closing the first zone, a second command to write second information associated with the first type of information to a second zone of the memory system, the second zone for storing the first type of information and corresponding to a second range of logical addresses of the memory system; and write, based at least in part on the first rate satisfying the threshold rate, the second information to a second set of memory cells corresponding to the multiple-level memory cell cursor, the second set of memory cells within the second zone of the memory system.
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: open a second zone of the memory system for being written with the first information based at least in part on determining that the first rate satisfies the threshold rate.
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine, based at least in part on closing the first zone, the first rate relative to other rates at which other types of information of the plurality of types of information are written to the memory system, wherein the multiple-level memory cell cursor comprises the second set of memory cells based at least in part on the first rate being greater than the other rates at which the other types of information are written to the memory system.
The memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to: assign the second zone to a second multiple-level memory cell cursor of the plurality of cursors based at least in part on opening the second zone.
The memory system of claim 1, wherein the multiple-level memory cell cursor comprises the second set of memory cells based at least in part on the first rate satisfying the threshold rate.
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: close the first zone from being written with additional information based at least in part on writing the first information.
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: close a third zone from being written with additional information, wherein the third zone is for storing a second type of information of the plurality of types of information; determine, based at least in part on closing the third zone, a second rate at which the second type of information is written to the memory system; receive, based at least in part on closing the third zone, a third command to write third information associated with the second type of information to a fourth zone of the memory system, the fourth zone for storing the second type of information and corresponding to a third range of logical addresses of the memory system; and write, while the multiple-level memory cell cursor is open and based at least in part on the second rate, the third information to a second multiple-level memory cell cursor of the plurality of cursors for storing information written to the fourth zone that comprises a third set of memory cells.
The memory system of claim 5, wherein the processing circuitry is further configured to cause the memory system to: determine the first information to write to a second zone of the memory system in response closing the first zone.
The memory system of claim 4, wherein the processing circuitry is further configured to cause the memory system to: determine, based at least in part on closing the third zone, the second rate relative to the first rate and other rates at which other types of information of the plurality of types of information are written to the memory system, wherein the second rate is less than the first rate, and wherein the second multiple-level memory cell cursor comprises the third set of memory cells based at least in part on the second rate being greater than the other rates at which the other types of information are written to the memory system and a capability of the memory system to have two or more multiple-level memory cell cursors that comprise memory cells concurrently open and written to in response to commands from a host system.
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: receive a second command to write second information to a second zone of the memory system based at least in part on assigning the first zone to the first multiple-level memory cell cursor; and write, based at least in part on receiving the second command, the second information to the second zone corresponding to a second multiple-level memory cell cursor of the plurality of cursors.
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: close a third zone from being written with additional information, wherein the third zone is for storing a second type of information; determine, based at least in part on closing the third zone, a second rate at which the second type of information is written to the memory system; receive, based at least in part on closing the third zone, a third command to write third information associated with the second type of information to a fourth zone of the memory system, the fourth zone for storing the second type of information and corresponding to a third range of logical addresses of the memory system; and write, based at least in part on the second rate, the third information to a second single-level memory cell cursor of the plurality of cursors for storing information written to the fourth zone that comprises a third set of memory cells.
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: receive a third command to write third information to a third zone of the memory system.
The memory system of claim 6, wherein the processing circuitry is further configured to cause the memory system to: determine, based at least in part on closing the third zone, the second rate relative to the first rate and other rates at which other types of information of the plurality of types of information are written to the memory system, wherein the second single-level memory cell cursor comprises the third set of memory cells based at least in part on the second rate being less than the first rate, one or more of the other rates at which the other types of information are written to the memory system, or any combination thereof.
The memory system of claim 8, wherein the processing circuitry is further configured to cause the memory system to: write, based at least in part on receiving the third command, third information associated to a third multiple-level memory cell cursor of the plurality of cursors, wherein the third multiple-level memory cell cursor is configured to store the third information.
The memory system of claim 6, wherein the processing circuitry is further configured to cause the memory system to: determine, based at least in part on closing the third zone, whether the second rate satisfies a second threshold rate, wherein the second single-level memory cell cursor comprises the third set of memory cells based at least in part on the second rate failing to satisfy the second threshold rate.
The memory system of claim 9, wherein the third multiple-level memory cell cursor is the same as the first multiple-level memory cell cursor.
The memory system of claim 1, wherein the first zone is one zone of a plurality of zones and each zone of the plurality of zones is for storing a type of information of the plurality of types of information.
The memory system of claim 9, wherein the third multiple-level memory cell cursor is different than the first multiple-level memory cell cursor.
The memory system of claim 9, wherein information written to each zone of the plurality of zones is stored in a respective single-level memory cell cursor of the plurality of cursors that comprises a respective set of memory cells that each store a single bit of information.
A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processing circuitry to: receive a first command to write first information to a first zone of a memory system; write, based at least in part on receiving the first command, the first information to the first zone of the memory system; determine a first rate at which the first information is written to the first zone of the memory system; determine that the first rate satisfies a threshold rate associated with a first multiple-level memory cell cursor of a plurality of cursors; and assign the first zone of the memory system to the first multiple-level memory cell cursor of the plurality of cursors associated with the memory system based at least in part on determining that the first rate satisfies the threshold rate.
The memory system of claim 1, wherein: the second set of memory cells comprises tri-level memory cells that are each configured to store three bits of information.
The non-transitory computer-readable medium of claim 12, wherein the instructions are further executable by the processing circuitry to: open a second zone of the memory system for being written with the first information based at least in part on determining that the first rate satisfies the threshold rate.
The memory system of claim 1, wherein the plurality of types of information comprises hot data, warm data, cold data, hot metadata, warm metadata, cold metadata, or any combination thereof.
The non-transitory computer-readable medium of claim 13, wherein the instructions are further executable by the processing circuitry to: assign the second zone to a second multiple-level memory cell cursor of the plurality of cursors based at least in part on opening the second zone.
A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processing circuitry to: receive a first command to write first information associated with a first type of information of a plurality of types of information to a first zone of a memory system, the first zone for storing the first type of information and corresponding to a first range of logical addresses of the memory system; write, based at least in part on receiving the first command, the first information to a first set of memory cells corresponding to a single-level memory cell cursor of a plurality of cursors associated with the memory system, the first set of memory cells within the first zone of the memory system; close the first zone from being written with additional information based at least in part on writing the first information; determine, in response to closing the first zone, that a first rate at which the first type of information is written to the memory system satisfies a threshold rate associated with a multiple-level memory cell cursor of the plurality of cursors; receive, based at least in part on closing the first zone, a second command to write second information associated with the first type of information to a second zone of the memory system, the second zone for storing the first type of information and corresponding to a second range of logical addresses of the memory system; and write, based at least in part on the first rate satisfying the threshold rate, the second information to a second set of memory cells corresponding to the multiple-level memory cell cursor, the second set of memory cells within the second zone of the memory system.
A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive a first command to write first information to a first zone of the memory system; write, based at least in part on receiving the first command, the first information to a first set of memory cells corresponding to a single-level memory cell cursor of a plurality of cursors associated with the memory system, the first set of memory cells within the first zone of the memory system; receive a second command to write second information to a second zone of the memory system; and write, based at least in part on receiving the second command, the second information to a second set of memory cells corresponding to a multiple-level memory cell cursor, the second set of memory cells within the second zone of the memory system.
The non-transitory computer-readable medium of claim 13, wherein the instructions are further executable by the processing circuitry to: determine, based at least in part on closing the first zone, the first rate relative to other rates at which other types of information of the plurality of types of information are written to the memory system, wherein the multiple-level memory cell cursor comprises the second set of memory cells based at least in part on the first rate being greater than the other rates at which the other types of information are written to the memory system.
The memory system of claim 15, wherein the processing circuitry is further configured to cause the memory system to: determine a threshold rate at which the first information is written to the memory system based at least in part on writing the first information, wherein the threshold rate is associated with the multiple-level memory cell cursor of the plurality of cursors.
The non-transitory computer-readable medium of claim 13, wherein the instructions are further executable by the processing circuitry to: close a third zone from being written with additional information, wherein the third zone is for storing a second type of information of the plurality of types of information; determine, based at least in part on closing the third zone, a second rate at which the second type of information is written to the memory system; receive, based at least in part on closing the third zone, a third command to write third information associated with the second type of information to a fourth zone of the memory system, the fourth zone for storing the second type of information and corresponding to a third range of logical addresses of the memory system; and write, while the multiple-level memory cell cursor is open and based at least in part on the second rate, the third information to a second multiple-level memory cell cursor of the plurality of cursors for storing information written to the fourth zone that comprises a third set of memory cells.
The memory system of claim 15, wherein the processing circuitry is further configured to cause the memory system to: determine that a first rate at which the first information is written to the memory system satisfies a threshold rate associated with the multiple-level memory cell cursor of the plurality of cursors, wherein writing the second information is based at least in part on determining that the first rate satisfies the threshold rate.
The non-transitory computer-readable medium of claim 15, wherein the instructions are further executable by the processing circuitry to: determine, based at least in part on closing the third zone, the second rate relative to the first rate and other rates at which other types of information of the plurality of types of information are written to the memory system, wherein the second rate is less than the first rate, and wherein the second multiple-level memory cell cursor comprises the third set of memory cells based at least in part on the second rate being greater than the other rates at which the other types of information are written to the memory system and a capability of the memory system to have two or more multiple-level memory cell cursors that comprise memory cells concurrently open and written to in response to commands from a host system.
The memory system of claim 15, wherein the processing circuitry is further configured to cause the memory system to: close the first zone from being written with additional information based at least in part on writing the first information.
The non-transitory computer-readable medium of claim 13, wherein the instructions are further executable by the processing circuitry to: close a third zone from being written with additional information, wherein the third zone is for storing a second type of information; determine, based at least in part on closing the third zone, a second rate at which the second type of information is written to the memory system; receive, based at least in part on closing the third zone, a third command to write third information associated with the second type of information to a fourth zone of the memory system, the fourth zone for storing the second type of information and corresponding to a third range of logical addresses of the memory system; and write, based at least in part on the second rate, the third information to a second single-level memory cell cursor of the plurality of cursors for storing information written to the fourth zone that comprises a third set of memory cells.
The memory system of claim 18, wherein the processing circuitry is further configured to cause the memory system to: determine a first rate at which the first information is written to the memory system based at least in part on closing the first zone.
The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processing circuitry to: determine, based at least in part on closing the third zone, the second rate relative to the first rate and other rates at which other types of information of the plurality of types of information are written to the memory system, wherein the second single-level memory cell cursor comprises the third set of memory cells based at least in part on the second rate being less than the first rate, one or more of the other rates at which the other types of information are written to the memory system, or any combination thereof.
The memory system of claim 15, wherein the multiple-level memory cell cursor comprises the second set of memory cells based at least in part on a first rate at which the first information is written to the memory system satisfying a threshold rate.
The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processing circuitry to: determine, based at least in part on closing the third zone, whether the second rate satisfies a second threshold rate, wherein the second single-level memory cell cursor the third set of memory cells based at least in part on the second rate failing to satisfy the second threshold rate.
The memory system of claim 15, wherein: the first zone is for storing the first information and corresponding to a first range of logical addresses of the memory system; and the second zone is for storing the first information and corresponding to a second range of logical addresses of the memory system.
The non-transitory computer-readable medium of claim 13, wherein the first zone is one zone of a plurality of zones and each zone of the plurality of zones is for storing a type of information of the plurality of types of information, and wherein information written to each zone of the plurality of zones is stored in a respective single-level memory cell cursor of the plurality of cursors that comprises a respective set of single level memory cells that each store a single bit of information.
A method, comprising: receiving a first command to write first information associated with a first type of information of a plurality of types of information to a first zone of a memory system, the first zone for storing the first type of information and corresponding to a first range of logical addresses of the memory system; write, based at least in part on receiving the first command, the first information to a first set of memory cells corresponding to a single-level memory cell cursor of a plurality of cursors associated with the memory system, the first set of memory cells within the first zone of the memory system; closing the first zone from being written with additional information based at least in part on writing the first information; determining, in response to closing the first zone, that a first rate at which the first type of information is written to the memory system satisfies a threshold rate associated with a multiple-level memory cell cursor of the plurality of cursors; receiving, based at least in part on closing the first zone, a second command to write second information associated with the first type of information to a second zone of the memory system, the second zone for storing the first type of information and corresponding to a second range of logical addresses of the memory system; and writing, based at least in part on the first rate satisfying the threshold rate, the second information to a second set of memory cells corresponding to the multiple-level memory cell cursor, the second set of memory cells within the second zone of the memory system.
The method of claim 21, further comprising: determining, based at least in part on closing the first zone, the first rate relative to other rates at which other types of information of the plurality of types of information are written to the memory system, wherein the multiple-level memory cell cursor comprises the second set of memory cells based at least in part on the first rate being greater than the other rates at which the other types of information are written to the memory system.
The method of claim 21, further comprising: close a third zone from being written with additional information, wherein the third zone is for storing a second type of information of the plurality of types of information; determine, based at least in part on closing the third zone, a second rate at which the second type of information is written to the memory system; receive, based at least in part on closing the third zone, a third command to write third information associated with the second type of information to a fourth zone of the memory system, the fourth zone for storing the second type of information and corresponding to a third range of logical addresses of the memory system; and write, while the multiple-level memory cell cursor is open and based at least in part on the second rate, the third information to a second multiple-level memory cell cursor of the plurality of cursors for storing information written to the fourth zone that comprises a third set of memory cells.
The method of claim 23, further comprising: determine, based at least in part on closing the third zone, the second rate relative to the first rate and other rates at which other types of information of the plurality of types of information are written to the memory system, wherein the second rate is less than the first rate, and wherein the second multiple-level memory cell cursor comprises the third set of memory cells based at least in part on the second rate being greater than the other rates at which the other types of information are written to the memory system and a capability of the memory system to have two or more multiple-level memory cell cursors that comprise memory cells concurrently open and written to in response to commands from a host system.
The method of claim 21, further comprising: close a third zone from being written with additional information, wherein the third zone is for storing a second type of information; determine, based at least in part on closing the third zone, a second rate at which the second type of information is written to the memory system; receive, based at least in part on closing the third zone, a third command to write third information associated with the second type of information to a fourth zone of the memory system, the fourth zone for storing the second type of information and corresponding to a third range of logical addresses of the memory system; and write, based at least in part on the second rate, the third information to a second single-level memory cell cursor of the plurality of cursors for storing information written to the fourth zone that comprises a third set of memory cells.
Regarding claim 2, the claim of the instant application is substantially similar to that of Claim 1 of the Patent as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 1 of the instant application and US Patent notes the differences and the US Patent thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application in view of Yang Paragraph [0065] wherein it is disclosed that writes may be handled to a plurality of zone types including single level cell (SLC), multiple level cell (MLC), triple level cell (TLC), and more. Furthermore, as part of closing the first zone and proceeding to write to a different second zone in the Patent, it would be obvious to one of ordinary skill in the art that the first zone is assigned to the first MLC cursor as supported by the originally filed Specification wherein the “assign” language as supported by Paragraph [0003] refers to writing information to the corresponding cells and therefore under broadest reasonable interpretation of the claim language.
Regarding claim 3 of the instant application, the limitations are substantially identical to claim 1 of the Patent. Herein it would be obvious to one of ordinary skill in the art that in order to write to the second zone, it must be opened for writing.
Regarding claim 4 of the instant application, the limitations are substantially identical to claim 1 of the Patent. Under similar reasoning as presented for claim 1, as part of opening the second zone for writing to the MLC cursor of the second set of cells, this therefore requires assigning the second zone to the second MLC cursor.
Regarding claim 5 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 6 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 7 of the instant application, the limitations are substantially identical to claim 1 and claim 9 of the Patent in view of Yang. While the Patent indicates the first zone corresponding to the SLC cursor and the second zone corresponding to the MLC cursor, in view of Yang, it would be obvious to one of ordinary skill in the art as identified within Yang to handle multiple different cursors of the same type (SLC, MLC, TLC, etc.).
Regarding claim 8 of the instant application, the limitations are substantially identical to claim 1 and claim 9 of the Patent in view of Yang for similar reasons as identified for claim 7. Herein the recitation of receiving a third command to write third information to a third zone would be obvious to one of ordinary skill in the art as performing similar steps as presented in claim 7 regarding the second command and second zone and in view of the Patent claim 1 wherein a first command writing to a first zone is processed.
Regarding claim 9 of the instant application, the limitations are substantially identical to claim 1 and claims 9-10 of the Patent in view of Yang for similar reasons as identified for claim 7. As recited in the Patent claims 1 and 9-10, each zone corresponds to storing a type of information and is subject to writing to a respective cursor which one of ordinary skill in the art may recognize as being a plurality of MLC cursors.
Regarding claim 10 of the instant application, the limitations are substantially identical to claim 1 and claims 9-10 of the Patent. As the Patent recites each zone corresponding to a type of information; in the case that the third information type is the same as the first information type, the cursor may be the same.
Regarding claim 11 of the instant application, the limitations are substantially identical to claim 1 and claims 9-10 of the Patent. As the Patent recites each zone corresponding to a type of information, in the case that the third information type is different than the first information type, the cursor may will be different.
Regarding claim 12 of the instant application, the limitations are substantially identical to claim 13 of the Patent. The claim of the instant application is substantially similar to that of Claim 13 of the Patent as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 1 of the instant application and US Patent notes the differences and the US Patent thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application in view of Yang Paragraph [0065].
Regarding claim 13 of the instant application, the limitations are substantially identical to claim 13 of the Patent. Herein it would be obvious to one of ordinary skill in the art that in order to write to the second zone, it must be opened for writing.
Regarding claim 14 of the instant application, the limitations are substantially identical to claim 13 of the Patent. Under similar reasoning as presented for claim 1, as part of opening the second zone for writing to the MLC cursor of the second set of cells, this therefore requires assigning the second zone to the second MLC cursor.
Regarding claim 15 of the instant application, the limitations are substantially identical to claim 1 of the Patent. The claim of the instant application is substantially similar to that of Claim 13 of the Patent as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 1 of the instant application and US Patent notes the differences and the US Patent thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application in view of Yang Paragraph [0065].
Regarding claim 16 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 17 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 18 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 19 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 20 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 21 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
This is a nonstatutory double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yang et al. (US 2022/0382454) – Paragraph [0082-90] wherein directing data in particular address zones is discussed.
Agarwal et al. (US 2022/0113905) – Paragraph [0032] wherein configuring storage zone for speed or latency.
Zhang et al. (US 2020/0272356) – Paragraph [0040-41] wherein determining write speeds of data types is discussed.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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