DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 20 recites the limitation "the first or second signals" in line 2. There is insufficient antecedent basis for this limitation in the claim. Specifically, claim 20 which depends on claim 16, which depends on claim 10; and none of the claims recite “a first signal” or “a second signal”. Thus, it is not clear which signals claim is referring to, thus rendering the claim indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (2020/0066226).
Regarding claim 1, Han teaches an electronic device comprising: a display panel (300; Fig 1; Fig 2); a processor (100; Fig 1; Fig 2), comprising processing circuitry (para [0040] The host 100 is configured to control the operation of the display driver IC 200. In an embodiment, the host 100 may be implemented as an Integrated Circuit (IC), a System-on-Chip (SoC), an Application Processor (AP), or a mobile AP. The host 100 may include a processor 101, a MIPI transmission unit (MIPI Tx) 102, and a mode switching signal transmission unit 103.), configured to selectively generate a first signal (para [0062] sets the mode switching signal HS to a logic ‘0’) and a second signal (para [0060] a mode switching signal HS to a logic ‘1’) based at least in part on an image (para [0042] the processor 101 may determine whether the image data DATA to be transmitted to the display driver IC 200 is still image data or moving image data, and may set a display mode to a command mode or a video mode based on the result of determination.) to be displayed via the display panel satisfying a first condition (para[0060] moving image) and a second condition (para[0060] still image), respectively; and display driver integrated circuitry (DDI) (200; Fig 2) including internal memory (204; Fig 2) and operatively coupled with the display panel and the processor (Fig 2), the DDI configured to: based at least in part on the first signal being received from the processor, provide the display panel with the image as received from the processor instead of retrieving the image from the internal memory (para [0054] , the controller 203 may transmit the output image data DDATA to the display 300 through the video mode processing path PATH2 which does not pass through the frame memory 204; Fig 4), and based at least in part on the second signal being received from the processor, provide the display panel with the image as retrieved from the internal memory instead of receiving the image from the processor (para [0054] For example, when the display mode indicates the command mode in response to the mode switching signal HS, the controller 203 may transmit the output image data DDATA to the display 300 through the command mode processing path PATH1 which passes through the frame memory 204; Fig 4).
Regarding claim 3, Han teaches the electronic device of claim 1, wherein the DDI is configured to: based at least in part on the first signal being received from the processor, refrain from storing the image received from the processor into the internal memory (para [0054] The controller 203 may generate output image data DDATA by processing the image data DATA. In various embodiments of the present disclosure, the controller 203 may identify, based on the mode switching signal HS, whether the display mode is a command mode or a video mode, and may determine whether to transmit the output image data DDATA to the display 300 through the frame memory 204 (command mode) or whether to transmit the output image data DDATA to the display 300 by bypassing the frame memory 204 (video mode).).
Regarding claim 7, Han teaches the electronic device of claim 1, wherein the DDI is configured to: based at least in part on the image being received from the processor and provided to the display panel, refrain from retrieving from the internal memory the image previously stored thereinto (Fig 5;para [0054] whereas when the display mode indicates the video mode in response to the mode switching signal HS, the controller 203 may transmit the output image data DDATA to the display 300 through the video mode processing path PATH2 which does not pass through the frame memory 204.; para [0055] In an example, the timing controller 205 may read data from the frame memory 204 during a high-level period of a frame scan signal Frame_Scan. ).
Regarding claim 8, Han teaches the electronic device of claim 1, wherein the DDI is configured to: based at least in part on the first signal being received from the processor, maintain the providing the display panel with the image received from the processor without storing the image into the memory until the second signal is received from the processor (Fig 4; Fig 5; para [0065] From a time point at which the high-level period 502 of the TE control signal TE ends, that is, from the falling edge of the TE control signal TE, the display driver IC 200 may immediately transmit the image data DATA of a video image, received from the host 100 during the high-level period 502 of the TE control signal TE, to the display 300 through the video mode processing path PATH2 at step 411. Therefore, the display 300 may seamlessly display the moving image data even if the mode changes at step 412.).
Regarding claim 9, Han teaches the electronic device of claim 1, wherein the DDI is configured to: based at least in part on the second signal being received from the processor, maintain the providing the display panel with the image retrieved from the internal memory without receiving the image from the processor until the first signal is from the processor (para [0069] In order to correctly perform switching to the command mode, output image data DDATA corresponding to still images must be written to the frame memory 204 before the frame memory 204 is loaded. para [0071] the display driver IC 200 may immediately transmit the image data DATA of a still image, received from the host 100 during the high-level period 504 of the TE control signal TE, to the display 300 through the command mode processing path PATH1 at step 417.).
Allowable Subject Matter
Claims 2, and 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, prior art of record fails to teach the following claim limitations of “…and refrain from providing the DDI with the image at least temporarily based at least in part on the second signal being provided from the processor to the DDI.”; in combination with all other claim limitations. Regarding claim 4, prior art of record fails to teach the following claim limitations of “wherein the processor is configured to: identify that the first condition is satisfied, based at least in part on a determination that the image or another image is to be sent to the DDI in next one or more vertical synchronization time periods; and identify that the second condition is satisfied, based at least in part on a determination that no image is to be sent to the DDI in at least one of the next one or more vertical synchronization time periods”; in combination with all other claim limitations. Regarding claim 5, prior art of record fails to teach the following claim limitations of “wherein the DDI is configured to: based at least in part on the first signal being received from the processor, store the image received from the processor into the internal memory substantially concurrently with the image being displayed via the displayed panel at least temporarily before performing the providing the display panel with the image as received from the processor instead of being retrieved from the internal memory.”; in combination with all other claim limitations. Regarding claim 6, prior art of record fails to teach the following claim limitations of “wherein the DDI is configured to: based at least in part on the second signal being received from the processor, store the image received from the processor into the internal memory substantially concurrently with the image being displayed via the displayed panel at least temporarily before performing the providing the display panel with the image as retrieved from the internal memory instead of being received from the processor.”; in combination with all other claim limitations.
Claims 10-19 are allowed.
The following is an examiner’s statement of reasons for allowance: Regarding claim 10, prior art of record fails to teach the following claim limitations of “…while…receive, from the at least one processor, a second command for deactivating storing of an image received from the at least one processor in the memory of the display driver circuitry; in response to a first image received initially from the at least one processor after the second command is received from the at least one processor: display, via the display panel, the first image by scanning the first image received from the at least one processor, and perform storing of the first image in the memory of the display driver circuitry despite the second command; and in response to a second image received from the at least one processor while displaying the first image via the display panel: display, via the display panel, the second image by scanning the second image received from the at least one processor, and in accordance with the second command, refrain from storing of the second image in the memory of the display driver circuitry”; in combination with all other claim limitations; specifically the order in which . Regarding claim 17, prior art of record fails to teach the following claim limitations of “…while…receive, from the at least one processor, a second command, wherein the first command is, until a third command is received from the at least one processor, for activating storing of an image received from the at least one processor in the memory of the display driver circuitry, wherein the second command is for activating only storing of an image initially received from the at least one processor in the memory of the display driver circuitry after the second command is transmitted from the at least one processor to the display driver circuitry, and wherein the third command is for deactivating storing of an image received from the at least one processor in the memory of the display driver circuitry; in response to a first image received initially from the at least one processor after the second command is received from the at least one processor: display, via the display panel, the first image by scanning the first image received from the at least one processor, and based on the second command, perform storing of the first image in the memory of the display driver circuitry; in response to a second image received from the at least one processor while displaying the first image via the display panel: display, via the display panel, the second image by scanning the second image received from the at least one processor, and based on the second command, refrain from storing of the second image in the memory of the display driver circuitry.”; in combination with all other claim limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (2016/0027146) teaches A display driver includes a first memory configured to store a plurality of pieces of image data, and an image generator configured to access the first memory based on display information and generate first display data based on the plurality of pieces of image data stored in the first memory. Kim also further teaches For example, when a typical image such as a time image, an incoming phone call image, a weather image, a temperature image, a number, a character, an expectable image, etc. is displayed on the display panel, the host processor (e.g., the host processor 10 of FIG. 1) may transmit a first command signal CMD1 to the display driver 100, and the display driver 100 may operate in the first operation mode Mode1 in response to receiving the first command signal CMD1.(para [0121]). Kim further teaches second operation mode (para [0122]; Fig 6).
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/PREMAL R PATEL/Primary Examiner, Art Unit 2624