Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Objections
Claims 5, 17, and 23 are objected to because of the following informalities:
Claim 5, line 3, “bulk regions of a PMOS transistor” appears to be “bulk regions of PMOS transistors”.
Claim 17, line 4, “the first power supply voltage terminal” appears to be “the first supply voltage terminal” in order to be consistent with “first supply voltage terminal” used in Claims 1 and 3.
Claim 23 should depend on claim 21 instead of claim 20 since “an input and output control logic” is introduced in claim 21, not claim 20.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,316,316 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are a broader recitation, a mere change of preamble (“memory controller” versus “interface system” and “memory system”), or an obvious subset of the patented I/O driving circuit limitations.
19/204,640 (Instant Application)
Patent No.: US 12,316,316 B2
1. A memory controller comprising: an interface configured to transfer data between a host and a memory device, and an input/output driving circuit including a pull-down driver connected between a pad and a ground node, and a gate control logic connected between a pad voltage terminal and a first supply voltage terminal, wherein the pull-down driver includes a plurality of NMOS transistors and the gate control logic includes a plurality of PMOS transistors.
2. The memory controller of claim 1, wherein the pull-down driver includes a first NMOS transistor connected to the pad, a second NMOS transistor connected to the first NMOS transistor, and a third NMOS transistor connected between the second NMOS transistor and the ground node.
3. The memory controller of claim 1, wherein the gate control logic includes: a first PMOS transistor connected to the pad voltage terminal and controlled by a first supply voltage provided from the first supply voltage terminal, a second PMOS transistor connected to the first PMOS transistor, and a third PMOS transistor connected between the second PMOS transistor and the first supply voltage terminal.
4. The memory controller of claim 3, wherein the second PMOS transistor is enabled based on a pad voltage provided from the pad voltage terminal.
5. The memory controller of claim 2, wherein the first NMOS transistor is enabled based on a feedback voltage provided to bulk regions of a PMOS transistor.
1. An interface system including a plurality of interface devices communicating each other, each of the interface devices comprising: at least one input/output driving circuit including a pull-down driver connected between a pad and a ground node, and a gate control logic connected between a pad voltage terminal and a first supply voltage terminal, wherein the pull-down driver includes a first NMOS transistor connected to the pad, a second NMOS transistor connected to the first NMOS transistor, and a third NMOS transistor connected between the second NMOS transistor and the ground node, wherein the gate control logic includes a first PMOS transistor connected to the pad voltage terminal and controlled by a first supply voltage provided from the first supply voltage terminal, a second PMOS transistor connected to the first PMOS transistor, and a third PMOS transistor connected between the second PMOS transistor and the first supply voltage terminal, and wherein the second PMOS transistor is enabled based on a pad voltage provided from the pad voltage terminal, and the first NMOS transistor is enabled based on a feedback voltage provided to bulk regions of the first to third PMOS transistors.
14. A memory system comprising: a memory device configured to store data; and a memory controller configured to communicate with the memory device by an input/output driving circuit, wherein the input/output driving circuit comprises: a pull-down driver including a first transistor and a second transistor which are electrically coupled between a pad and a ground node; and a gate control logic including a third transistor and a fourth transistor which are electrically coupled between the pad and a first terminal receiving a first driving voltage, the gate control logic being configured to receive a pad voltage provided from the pad and generate a feedback voltage, wherein a source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.
6. The memory controller of claim 1, wherein the input/output driving circuit further comprises an internal resistor connected to the pad receiving an external voltage higher than a first supply voltage provided from the first supply voltage terminal.
7. The memory controller of claim 6, wherein the pad voltage terminal is an output node of the internal resistor.
2. The interface system of claim 1, wherein the input/output driving circuit further comprises an internal resistor connected to the pad receiving an external voltage higher than the first supply voltage, and wherein the pad voltage terminal is an output node of the internal resistor.
8. The memory controller of claim 1, wherein the input/output driving circuit further comprises an input and output control logic configured to receive a clock signal and an enable signal and generate a first control signal provided to a gate of one of the plurality of NMOS transistors.
3. The interface system of claim 1, wherein the input/output driving circuit further comprises an IO (input and output) control logic configured to receive a clock signal and an enable signal, as input signals, and generate a first control signal provided to a gate of the third NMOS transistor.
9. The memory controller of claim 8, wherein the input and output control logic receives a first supply voltage from the first supply voltage terminal and a second supply voltage lower than the first supply voltage, as a power source.
4. The interface system of claim 3, wherein the IO control logic receives the first supply voltage and a second supply voltage lower than the first supply voltage, as a power source.
10. The memory controller of claim 8, wherein one of the plurality of PMOS transistors receives an inverted enable signal, as a gate voltage.
5. The interface system of claim 3, wherein the third PMOS transistor receives an inverted enable signal, as a gate voltage.
11. The memory controller of claim 2, wherein the first to third NMOS transistors are designed to be driven under a second supply voltage lower than a first supply voltage provided from the first supply voltage terminal.
12. The memory controller of claim 3, wherein the first to third PMOS transistors are designed to be driven under a second supply voltage lower than a first supply voltage provided from the first supply voltage terminal.
6. The interface system of claim 3, wherein the first to third NMOS transistors and the first to third PMOS transistors are designed to be driven under a second supply voltage lower than the first supply voltage.
13. The memory controller of claim 8, wherein at least one of the gate control logic and the input and output control logic provides a control signal to gates of at least one of the plurality of NMOS transistors to maintain internal voltages of at least one of the plurality of NMOS transistors in a voltage range of a second supply voltage, when the first supply voltage or a voltage higher than the first supply voltage is input to at least one of electrodes of the plurality of NMOS transistors.
14. The memory controller of claim 13, wherein the internal voltage includes at least one of gate-source voltage, gate-drain voltage and drain-source voltage of one of the plurality of NMOS transistors.
7. The interface system of claim 6, wherein at least one of the gate control logic and the IO control logic provides at least one control signal to gates of the first and third NMOS transistors to maintain internal voltages of the first to third NMOS transistors in a voltage range of the second supply voltage, when the first supply voltage or a voltage higher than the first supply voltage is input to at least one of electrodes of the first to third NMOS transistors, wherein the internal voltages include gate-source voltages, gate-drain voltages and drain-source voltages of the first to third NMOS transistors.
15. The memory controller of claim 2, wherein the second NMOS transistor receives the first supply voltage, as a gate voltage.
8. The interface system of claim 7, wherein the second NMOS transistor receives the first supply voltage, as a gate voltage.
16. The memory controller of claim 1, wherein the gate control logic further comprises a voltage stabilizing unit, wherein the voltage stabilizing unit is electrically connected between the pad voltage terminal and bulk regions of the PMOS transistors where a feedback voltage is outputted, based on a first supply voltage provided from the first supply voltage terminal.
17. The memory controller of claim 1, wherein the gate control logic further comprises an external voltage selection unit, wherein the external voltage selection unit is electrically connected between bulk regions of the PMOS transistors and the first power supply voltage terminal, based on a first supply voltage provided from the first supply voltage terminal and a second control signal.
9. The interface system of claim 1, wherein the gate control logic further comprises at least one of a voltage stabilizing unit and an external voltage selection unit, wherein the voltage stabilizing unit is electrically connected between the pad voltage terminal and the bulk regions of the first to third PMOS transistors where the feedback voltage is outputted, based on the first supply voltage, and wherein the external voltage selection unit is electrically connected between the bulk regions of the first to third PMOS transistors and the first power supply voltage terminal, based on the first supply voltage and a second control signal.
18. A memory controller between a memory device and a host, comprising: a pull-down driver including a first transistor and a second transistor which are electrically coupled between a pad and a ground node; and wherein a source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.
19. The memory controller of claim 18, further comprising: a gate control logic configured to receive a pad voltage provided from the pad and generate a feedback voltage.
20. The memory controller of claim 19, wherein the gate control logic includes a third transistor and a fourth transistor which are electrically coupled between the pad and a first supply voltage terminal.
10. An interface system between a memory device and a memory controller, comprising: at least one input/output driving circuit including: a pull-down driver including a first transistor and a second transistor which are electrically coupled between a pad and a ground node; and a gate control logic including a third transistor and a fourth transistor which are electrically coupled between the pad and a first supply voltage terminal, the gate control logic configured to receive a pad voltage provided from the pad and generate a feedback voltage, wherein a source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.
14. A memory system comprising: a memory device configured to store data; and a memory controller configured to communicate with the memory device by an input/output driving circuit, wherein the input/output driving circuit comprises: a pull-down driver including a first transistor and a second transistor which are electrically coupled between a pad and a ground node; and a gate control logic including a third transistor and a fourth transistor which are electrically coupled between the pad and a first terminal receiving a first driving voltage, the gate control logic being configured to receive a pad voltage provided from the pad and generate a feedback voltage, wherein a source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.
21. The memory controller of claim 18, further comprising: an input and output control logic configured to receive the clock signal and the enable signal, as input signals, and generate the control signal.
11. The interface system of claim 10, wherein the input/output driving circuit further comprises an IO control logic configured to receive the clock signal and the enable signal, as input signals, and generate the control signal.
15. The memory system of claim 14, wherein the input/output driving circuit further comprises an IO control logic configured to receive the clock signal and the enable signal as input signals, and generate the control signal.
22. The memory controller of claim 20, wherein the first to fourth transistors are designed to be driven under a second supply voltage lower than a first supply voltage provided from the first supply voltage terminal.
12. The interface system of claim 11, wherein the first to fourth transistors are designed to be driven under a second supply voltage lower than a first supply voltage provided from the first supply voltage terminal.
16. The memory system of claim 15, wherein the first to fourth transistors are designed to be driven under a second driving voltage lower than the first driving voltage.
23. The memory controller of claim 20, wherein at least one of the gate control logic and the input and output control logic provides a control signal to gates of the first and second transistors to maintain internal voltages of the first to fourth transistors in a voltage range of the second supply voltage, when the first supply voltage or a voltage higher than the first supply voltage is input to at least one of electrodes of the first and second transistors.
24. The memory controller of claim 23, wherein the internal voltages include at least one of gate-source voltages, gate-drain voltages and drain-source voltages of the first to fourth transistors.
13. The interface system of claim 12, wherein at least one of the gate control logic and the IO control logic provides at least one control signal to gates of the first and second transistors to maintain internal voltages of the first to fourth transistors in a voltage range of the second supply voltage, when the first supply voltage or a voltage higher than the first supply voltage is input to at least one of electrodes of the first and second transistors, and wherein the internal voltages include gate-source voltages, gate-drain voltages and drain-source voltages of the first to fourth transistors.
17. The memory system of claim 16, wherein at least one of the gate control logic and the IO control logic provides at least one control signal to gates of the first and second transistors to maintain internal voltages of the first to fourth transistors in a voltage range of the second driving voltage, when the first driving voltage or a voltage higher than the first driving voltage is input to at least one of electrodes of the first and second transistors, and wherein the internal voltages include gate-source voltages, gate-drain voltages and drain-source voltages of the first to fourth transistors.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-15, and 18-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2014/0002146 A1, hereinafter referred to as Kim).
Regarding claim 1, Kim discloses a memory controller (1000, "The semiconductor integrated circuit 1000 may include first, second and third circuit blocks 1100, 1200 and 1300. The first circuit block 1100 may be a semiconductor memory, a controller, a CPU or a microprocessor.") comprising:
an interface (I/F Circuit 1200, Fig. 10) configured to transfer data between a host (computer circuitry 802, Fig. 14) and a memory device (memory 1400, Fig. 14; "the electronic system 2000 may include a computer circuitry 802 including a memory 1400," FIG. 14; interface 1200 of controller IC 1000 transfers signals between host-side computer circuitry 802 and memory 1400 / circuits 2100, 2200, paras [0129], [0157]), and
an input/output driving circuit (Output Circuit 1300, "The third circuit block 1300 is an output circuit to which the circuit illustrated in FIG. 5 may be applied.", para [0129]; FIG. 10) including a pull-down driver (20: NMl, NM2 and NM3, Fig. 5) connected between a pad (PAD) and a ground node ("a pull-down driver 20 having first, second and third transistors NMl, NM2 and NM3 of second conductivity type connected by a cascode structure between a ground node and the output node NO1.", para [0067]; FIG. 5) and a gate control logic (a level shifter 100, a reference voltage generator 200, a dynamic gate control unit 300, 10: PM1-PM3, Fig. 5) connected between a pad voltage terminal (NO1) and a first supply voltage terminal (OVDD, having ),
wherein the pull-down driver includes a plurality of NMOS transistors (NM1, NM2 and NM3, para [0071] - [0073]) and the gate control logic (a level shifter 100, a reference voltage generator 200, a dynamic gate control unit 300, 10: PM1-PM3, Fig. 5) includes a plurality of PMOS transistors (10: PM1-PM3, Fig. 5; P2 – P17, Fig. 6).
Regarding claim 2, Kim discloses wherein the pull-down driver (20: NM1, NM2 and NM3, Fig. 5) includes a first NMOS transistor (NM3 or NM2) connected (directly or indirectly) to the pad (PAD), a second NMOS transistor (NM2 or NM3) connected to the first NMOS transistor, and a third NMOS transistor (NM1) connected between the second NMOS transistor and the ground node (Ground).
Regarding claim 3, Kim discloses wherein the gate control logic (a level shifter 100, a reference voltage generator 200, a dynamic gate control unit 300, 10: PM1-PM3, Fig. 5) includes:
a first PMOS transistor (PM3, Fig. 5) connected to the pad voltage terminal (NO1) and controlled by a first supply voltage (0VDD) provided from the first supply voltage terminal,
a second PMOS transistor (PM2, Fig. 5) connected to the first PMOS transistor, and
a third PMOS transistor (PM1, Fig. 5) connected between the second PMOS transistor and the first supply voltage terminal (0VDD).
Regarding claim 4, Kim discloses wherein the second PMOS transistor (PM2, Fig. 5) is enabled based on a pad voltage (PAD) provided from the pad voltage terminal.
("a second PMOS transistor having a source-drain channel between the pull-down gate control voltage and the power supply voltage and a gate to receive the output node voltage.", claim 23)
Regarding claim 8, Kim discloses wherein the input/output driving circuit further comprises an input and output control logic (50, Fig. 5) configured to receive a clock signal ("The data output driving circuit includes an input gating unit 50 ... The input gating unit 50 gates input data DATA_IN according to a state of an output enable (OE) signal to output the gated data ... to first and second gating nodes ND10 and ND11.", paras [0061]-[0062]; FIG. 5; "a gate of the N-type first transistor receives a voltage level of the input data being applied through the second gating node.", claim 19; FIG. 13 places that same FIG. 5 circuit in output data buffers 724 of a semiconductor memory device 1400 having command/address/write-data buffers - i.e., a clocked memory data path. Under BRI, DATA_IN of unit 50 is generated based on the memory clock and is gated by OE) and an enable signal (OE) and generate a first control signal (NG1) provided to a gate of one of the plurality of NMOS transistors (NM1).
Regarding claim 9, Kim discloses wherein the input and output control logic (50, Fig. 5) receives a first supply voltage (OVDD = 3.3V, para [0050]) from the first supply voltage terminal and a second supply voltage (VDD = 1.8V) lower than the first supply voltage, as a power source ("The input gating unit 50 gates input data DATA_IN ... to output the gated data as a swing level of a power supply voltage VDD.", para [0062], FIG. 5; “level shifter 100” then "shifts the NAND response ... as a swing level of the high voltage OVDD.", para [0064]. Unit 50 and the downstream gate-control path therefore operate from both VDD and OVDD, OVDD being higher than VDD).
Regarding claim 10, Kim discloses wherein one of the plurality of PMOS transistors (PM3) receives (via NG1 and PG3 in 300, Figs. 5 and 8) an inverted enable signal (inverter GA2, FIG. 5; input gating unit 50 includes "inverter GA2" that inverts the OE signal), as a gate voltage (PG3).
Regarding claim 11, Kim discloses wherein the first to third NMOS transistors (NM1 – NM3) are designed to be driven (NM1: “The NOR gate GA3 receives a logic that an output of the NAND gate GA1 is inverted and an output logic of the inverter GA2 to generate a NOR response, that is, a voltage (or a pull-down driving voltage) NG1 to the second gating node ND11”, para [0062]; NM2: “the power supply voltage (VDD, NG2)”, para [0119]; NM3: “the power supply voltage VDD and the pull-down gate control voltage NG3 may be 0V-1.8V, 1.8V,”, para [0075]) under a second supply voltage (VDD = 1.8V) lower than a first supply voltage (OVDD = 3.3V) provided from the first supply voltage terminal.
Regarding claim 12, Kim discloses wherein the first to third PMOS transistors (PM1 – PM3) are designed to be driven under a second supply voltage (1.8V) lower than a first supply voltage (3.3V) provided from the first supply voltage terminal (same 1.8 V process devices on a 3.3 V OVDD rail: "manufactured using a CMOS manufacturing process for an operation voltage of 1.8V", Claim 8; "voltage swing range of the output node ... from 0V to 3.3V.", para [0053], claim 9).
Regarding claim 13, Kim discloses wherein at least one of the gate control logic and the input and output control logic provides a control signal (NG1, Fig. 5) to gates of at least one of the plurality of NMOS transistors (NM1, Fig. 5) to maintain internal voltages of at least one of the plurality of NMOS transistors in a voltage range of a second supply voltage, when the first supply voltage or a voltage higher than the first supply voltage is input to at least one of electrodes of the plurality of NMOS transistors (“controlling a voltage difference between a drain and a source of each of the first, second and third transistors of second conductivity type below a level of the power supply voltage when pulling down the pull-down driver", para [0014]; FIG. 4; “voltage levels of the nodes PAD, ND2 and ND1 are 3.3V, 2.75V and 1.5V, respectively”, para [0057]).
Regarding claim 14, Kim discloses wherein the internal voltage includes at least one of gate-source voltage, gate-drain voltage and drain-source voltage of one of the plurality of NMOS transistors (“voltage Vds between a drain and a source of the third N-type MOS transistor NM3… voltage Vds between a drain and a source of the second N-type MOS transistor NM2”, para [0057]; FIG. 4).
Regarding claim 15, Kim discloses wherein the second NMOS transistor (NM3) receives the first supply voltage, as a gate voltage (“the NG3 becomes 3.3V (OVDD)”, para [0066]).
Regarding claim 18, Kim discloses a memory controller (1000, "The semiconductor integrated circuit 1000 may include first, second and third circuit blocks 1100, 1200 and 1300. The first circuit block 1100 may be a semiconductor memory, a controller, a CPU or a microprocessor.") between a memory device (memory 1400, Fig. 14; "the electronic system 2000 may include a computer circuitry 802 including a memory 1400," FIG. 14; interface 1200 of controller IC 1000 transfers signals between host-side computer circuitry 802 and memory 1400 / circuits 2100, 2200, paras [0129], [0157]) and a host (computer circuitry 802, Fig. 14), comprising:
a pull-down driver (20: NMl, NM2 and NM3, Fig. 5) including a first transistor and a second transistor which are electrically coupled between a pad and a ground node ("a pull-down driver 20 having first, second and third transistors NMl, NM2 and NM3 of second conductivity type connected by a cascode structure between a ground node and the output node NO1.", para [0067]; FIG. 5); and
wherein a source voltage level of the second transistor (ND1) is controlled by a control signal (NG1) generated based on a clock signal and an enable signal (ND1 node is set by turn on of NM1, whose gate receives the OE-gated data level from input gating unit 50: “input gating unit 50 gates input data DATA_IN according to a state of an output enable (OE) signal”, para [0062], gate (NG1) of NM1 receives that data level. FIG. 13 embeds FIG. 5 in output data buffers 724 of memory device 1400, so DATA_IN is the clocked output of the array/buffers. Under BRI the control signal is generated based on the memory clock and the OE enable, and it sets the source node of the series NM2 transistor.)
Regarding claim 19, Kim discloses a gate control logic (100, 200, 300, 10) configured to receive a pad voltage (at NO1) provided from the pad (PAD) and generate a feedback voltage (NG3/PG3 are the generated feedback / gate-control voltages, "The dynamic gate control unit 300 receives a feedback of the output node NO1 voltage to control levels of the control voltages PG3 and NG3.", para [0066]; FIG. 5).
Regarding claim 20, Kim discloses wherein the gate control logic includes a third transistor and a fourth transistor (“a pull-up driver 10 having first, second and third transistors PM1, PM2 and PM3 of a first conductivity-type connected by a cascode structure between the high voltage OVDD and the output node NO1”, para [0067]) which are electrically coupled between the pad (PAD) and a first supply voltage terminal (OVDD).
Regarding claim 21, Kim discloses an input and output control logic (50) configured to receive the clock signal and the enable signal, as input signals, and generate the control signal ("input gating unit 50 gates input data DATA_IN according to ... output enable (OE)", para [0062]; FIG. 5. DATA_IN of the FIG. 13 memory output data buffer embodiment is the clocked read/output data. Unit 50 therefore receives the enable OE and the clock derived data and generates the NMOS gate control signal NG1)
Regarding claim 22, Kim discloses wherein the first to fourth transistors are designed to be driven under a second supply voltage lower than a first supply voltage provided from the first supply voltage terminal (all of PM1-PM3 and NM1-NM3 "manufactured using a CMOS manufacturing process for an operation voltage of 1.8V" while OVDD/PAD = 3.3V, FIG. 2; claims 8- 9; Vds held below the power-supply / 1.8 V level).
Regarding claim 23, Kim discloses wherein at least one of the gate control logic and the input and output control logic provides a control signal (output of GA3, Fig. 5) to gates of the first and second transistors (NM1-NM3) to maintain internal voltages of the first to fourth transistors (NM1-NM3, PM1-PM3) in a voltage range of the second supply voltage, when the first supply voltage or a voltage higher than the first supply voltage is input to at least one of electrodes of the first and second transistors ("controlling a voltage difference between a drain and a source of each of the first, second and third transistors of first conductivity type below a level of the power supply voltage when pulling up ... and ... of second conductivity type below a level of the power supply voltage when pulling down", para [0013]; Fig. 4, PAD = 3.3 V while intermediate NMOS nodes are 2.75 V, 1.5 V; FIG. 3 analogous PMOS node waveforms. Gates of the pad side and series devices receive PGl/PBIAS/PG3 and data/VDD/NG3 from 50/100/300.)
Regarding claim 24, Kim discloses wherein the internal voltages include at least one of gate-source voltages, gate-drain voltages and drain-source voltages of the first to fourth transistors ("voltage Vds between a drain and a source" of the stacked NMOS, FIG. 4; same Vds control for the PMOS stack, and FIG. 3; node voltages PD1/PD2/PAD).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen (US 7,362,136) discloses dual voltage single gate oxide I/O circuit with high voltage stress tolerance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL D CHANG/Primary Examiner, Art Unit 2845
Prosecution Insights