DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 8, 10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fletcher (US 2018/0226042).
Regarding claim 1, Fletcher teaches An electronic device having an active region and a non-active region, and the electronic device comprising: an electronic component disposed in the active region (Fig. 3 active area 205) ;a first gate driving circuit disposed in the non-active region and coupled to the electronic component(Fig. 3 gate driver 308);at least one first output control component disposed in the non-active region, and the at least one first output control component comprising a control terminal, a first terminal and a second terminal(Fig. 3 FETs 322); and a first control circuit disposed in the non-active region (Fig. 3 control circuit 228),wherein the control terminal of the at least one first output control component is coupled to the first control circuit, the first terminal of the at least one first output control component is coupled to the first gate driving circuit, and the second terminal of the at least one first output control component is coupled to the electronic component (Fig. 3 shows FETs 322 coupled to control circuit 228, gate driver 308 and electronic component 205).
Regarding claim 5, Fletcher teaches wherein the at least one first output control component comprises a plurality of first output control components, each of the plurality of first output control components comprises the control terminal, the first terminal and the second terminal, and the control terminal of each of the plurality of first output control components is coupled to the first control circuit component (Fig. 3 shows plurality of FETs 322 coupled to control circuit 228).
Regarding claim 8, Fletcher teaches wherein the electronic component comprises a pixel, and the pixel comprises a switching transistor, wherein a control terminal of the switching transistor is coupled to the second terminal of the at least first output control component (Fig. 3 shows active region 205 with pixels having a switch transistor 206 coupled to control circuit FETs 322).
Regarding claim 10, Fletcher teaches a second gate driving circuit, at least one second output control component, and a second control circuit disposed in the non-active region, wherein the at least one second output control component comprises a control terminal, a first terminal and a second terminal, the control terminal of the at least one second output control component is coupled to the second control circuit, the first terminal of the at least one second output control component is coupled to the second gate driving circuit, and the second terminal of the at least one second output control component is coupled to the electronic component (Fig. 3 shows second gate driver 304, connected to second set of FETs 314, and second set of FETs 314 connected to second control circuit 224).
Regarding claim 12, Fletcher teaches wherein the first gate driving circuit and the second gate driving circuit are disposed on two opposite sides of the active region respectively (Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Fletcher (US 2018/0226042) in view of Wang (US 2015/0325181).
Regarding claim 2, Fletcher teaches the limitations as discussed above but does not teach wherein the first control circuit comprises a capacitor and a plurality of transistors.
However in the field of controlling the output of the gate driver, Wang teaches wherein the first control circuit comprises a capacitor and a plurality of transistors ([0086-0089] teaches the output control unit includes a first output control unit 21 with a output transistor T21 and a capacitor C and a second output control unit 22 includes a second output transistor T22.).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the control circuit as taught by Wang. This combination would improve the normal output of the gate driver as taught by Wang [0127].
Regarding claim 3, Wang teaches wherein the first control circuit comprises a capacitor and a plurality of transistors ([0069]).
Regarding claim 4, Wang teaches wherein each of the plurality of transistors comprises a first terminal (source/drain), a second terminal (source/drain) and a control terminal (gate), and the plurality of transistors comprise a first transistor(T21), a second transistor(T22) and a third transistor(T252), wherein the first terminal of the first transistor and the first terminal of the second transistor are coupled to each other and used to receive an enable signal, the second terminal of the first transistor and the second terminal of the second transistor are coupled to two terminals of the capacitor respectively, the firs terminal and the second terminal of the third transistor are coupled to the second terminal of the first transistor and ground respectively, the control terminal of the second transistor and the control terminal of the third transistor are used to receive a first clock signal, and the control terminal of the first transistor is used to receive a second clock signal (Fig. 3 show all three transistor coupled to each other, to capacitor C, and receiving a first clock signal CLK and second clock signal CLKB).
Claims 6, 9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Fletcher (US 2018/0226042) in view of Lee (US 2024/0046882).
Regarding claim 6, Fletcher teaches the limitations as discussed above and teaches a plurality of output control components (FETS 322) having first terminals respectively connected to gate driver circuit 308 and gate lines 204 (Fig. 3) , but fails to teach wherein the first gate driving circuit comprises a first stage output unit to an n-th stage output unit used to output a first stage output signal to an n-th stage output signal respectively, the first stage output unit to the n-th stage output unit are coupled to the first terminals of the plurality of first output control components respectively, and n is a positive integer.
However in the field of driving a display device, Lee teaches wherein the first gate driving circuit comprises a first stage output unit to an n-th stage output unit used to output a first stage output signal to an n-th stage output signal respectively, the first stage output unit to the n-th stage output unit are coupled to the first terminals of the plurality of first output control components respectively, and n is a positive integer (Fig. 5-6 show N stages of output units connected to respective gate/scan lines).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the N stages of a gate driver circuit as taught by Lee. This combination would improve the viewing experience for a user by improving the speed of the signal output.
Regarding claim 9, Fletcher teaches the limitations of claim 1 as discussed above and further teaches wherein the electronic component comprises a pixel, and the pixel comprises a transistor, wherein a control terminal of the transistor is coupled to the second terminal of the at least first output control component (Fig. 3 shows active region 205 with pixels having a switch transistor 206 coupled to control circuit FETs 322), however Fletcher fails to teach the pixel comprises a light emitting component and the transistor is a light emission transistor.
However in the field of manufacturing a display device, Lee teaches a display device could be a variety of display devices including a LCD and a light emitting display device where the pixel comprises a light emitting component and the transistor is a light emission transistor ([0003][0045]).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the method of manufacturing different display devices circuit as taught by Lee. This combination would improve the viewing experience for a user by improving speed of the signal output.
Regarding claim 13, Fletcher teaches the limitations as discussed above and discloses the use of multiple gate driving circuit and although it obvious the multiple gate driving circuits could rearranged to any location, Fletcher fails to teach wherein the first gate driving circuit and the second gate driving circuit are disposed on a same side of the active region.
However in the field of manufacturing a display device Lee teaches wherein the first gate driving circuit and the second gate driving circuit are disposed on a same side of the active region (Fig. 4 shows gate drivers 161-164 disposed on the same side).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the method of manufacturing different display devices circuit as taught by Lee. This combination would improve the viewing experience for a user by improving speed of the signal output.
Claims 7, 11, 14-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Fletcher (US 2018/0226042) in view of Sawahata (US 2025/0078719).
Regarding claim 7, Fletcher teaches the limitations of claim 1 as discussed above but fails to teach a first detecting circuit disposed in the non-active region, wherein the first detecting circuit has an input terminal and an output terminal, the input terminal of the first detecting circuit is coupled to the first gate driving circuit, and the output terminal of the first detecting circuit is coupled to the first control circuit.
However in the field of detecting a fault in the display device, Sawahata teaches protection circuits (Fig. 1 element 6/7) with a first detecting circuit disposed in the non-active region, wherein the first detecting circuit has an input terminal and an output terminal (Fig. 2 current detecting circuits K1-Kn), the input terminal of the first detecting circuit is coupled to the first gate driving circuit ([0007]), and the output terminal of the first detecting circuit is coupled to the first control circuit (Fig. 2 shows current detecting circuits K1-Kn coupled to control circuit 16 which control gates of output transistor T1-Tn).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the detecting device as taught by Sawahata. This combination would provide allow a display device to maintain display even after a fault has been detected as taught by Sawahata [0006].
Regarding claim 11, Fletcher teaches the limitations of claim 1 as discussed above but fails to teach a second detecting circuit disposed in the non-active region, wherein the second detecting circuit has an input terminal and an output terminal, the input terminal of the second detecting circuit is coupled to the second gate driving circuit, and the output terminal of the second detecting circuit is coupled to the second control circuit.
However in the field of detecting a fault in the display device, Sawahata teaches protection circuits (Fig. 1 element 6/7) with a second detecting circuit disposed in the non-active region, wherein the second detecting circuit has an input terminal and an output terminal (Fig. 2 current detecting circuits K1-Kn), the input terminal of the first detecting circuit is coupled to the second gate driving circuit ([0007]), and the output terminal of the second detecting circuit is coupled to the second control circuit (Fig. 2 shows current detecting circuits K1-Kn coupled to control circuit 16 which control gates of output transistor T1-Tn).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the detecting device as taught by Sawahata. This combination would provide allow a display device to maintain display even after a fault has been detected as taught by Sawahata [0006].
Regarding claim 14, Fletcher teaches Fletcher teaches An electronic device having an active region and a non-active region, and the electronic device comprising: an electronic component disposed in the active region (Fig. 3 active area 205) ;a first gate driving circuit disposed in the non-active region and coupled to the electronic component(Fig. 3 gate driver 308);a plurality first output control component disposed in the non-active region, and each of the first output control component comprising a control terminal, a first terminal and a second terminal(Fig. 3 FETs 322); and a first control circuit disposed in the non-active region (Fig. 3 control circuit 228),wherein the first terminals of the plurality of first output control components are coupled to the first gate driving circuit, and the second terminals of the plurality of first output control components are coupled to the electronic component. (Fig. 3 shows FETs 322 coupled to control circuit 228, gate driver 308 and electronic component 205). Although Fletcher teaches the limitations as discussed above, he fails to teach a first detecting circuit disposed in the non-active region, wherein the first detecting circuit has an input terminal and an output terminal, the input terminal of the first detecting circuit is coupled to the first gate driving circuit, and the output terminal of the first detecting circuit is coupled to the control terminal of each of the plurality of first output control components.
However in the field of detecting a fault in the display device, Sawahata teaches protection circuits (Fig. 1 element 6/7) with a first detecting circuit disposed in the non-active region, wherein the first detecting circuit has an input terminal and an output terminal (Fig. 2 current detecting circuits K1-Kn), the input terminal of the first detecting circuit is coupled to the first gate driving circuit ([0007]), and the output terminal of the first detecting circuit is coupled to the control terminal of each of the plurality of first output control components (Fig. 2 shows current detecting circuits K1-Kn coupled to control circuit 16 which control gates of output transistor T1-Tn).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the detecting device as taught by Sawahata. This combination would provide allow a display device to maintain display even after a fault has been detected as taught by Sawahata [0006].
Regarding claim 15, Fletcher teaches wherein each of the plurality of first output control components is a P-type or a N-type transistor ([0022-0023]).
Regarding claim 16, Fletcher teaches wherein the electronic component comprises a pixel, and the pixel comprises a switching transistor, wherein a control terminal of the switching transistor is coupled to the second terminal of the at least first output control component (Fig. 3 shows active region 205 with pixels having a switch transistor 206 coupled to control circuit FETs 322).
Regarding claim 18, Fletcher teaches a second gate driving circuit, at least one second output control component, and a second control circuit disposed in the non-active region, wherein the at least one second output control component comprises a control terminal, a first terminal and a second terminal, the control terminal of the at least one second output control component is coupled to the second control circuit, the first terminal of the at least one second output control component is coupled to the second gate driving circuit, and the second terminal of the at least one second output control component is coupled to the electronic component (Fig. 3 shows second gate driver 304, connected to second set of FETs 314, and second set of FETs 314 connected to second control circuit 224).
Regarding claim 19, Fletcher teaches wherein the first gate driving circuit and the second gate driving circuit are disposed on two opposite sides of the active region respectively (Fig. 3).
Claims 17 and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fletcher (US 2018/0226042) in view of Sawahata (US 2025/0078719) and Lee (US 2024/0046882).
Regarding claim 17, Fletcher in view of Sawahata teach the limitations as discussed above but fail to teach and Fletcher further teaches wherein the electronic component comprises a pixel, and the pixel comprises a transistor, wherein a control terminal of the transistor is coupled to the second terminal of the at least first output control component (Fig. 3 shows active region 205 with pixels having a switch transistor 206 coupled to control circuit FETs 322), however Fletcher fails to teach the pixel comprises a light emitting component and the transistor is a light emission transistor.
However in the field of manufacturing a display device, Lee teaches a display device could be a variety of display devices including a LCD and a light emitting display device where the pixel comprises a light emitting component and the transistor is a light emission transistor ([0003], [0045]).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the method of manufacturing different display devices circuit as taught by Lee. This combination would improve the viewing experience for a user by improving speed of the signal output.
Regarding claim 20, Regarding claim 13, Fletcher in view of Sawahata teach the limitations as discussed above and discloses the use of multiple gate driving circuit and although it obvious the multiple gate driving circuits could rearranged to any location, Fletcher fails to teach wherein the first gate driving circuit and the second gate driving circuit are disposed on a same side of the active region.
However in the field of manufacturing a display device Lee teaches wherein the first gate driving circuit and the second gate driving circuit are disposed on a same side of the active region (Fig. 4 shows gate drivers 161-164 disposed on the same side).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Fletcher with the detecting device as taught by Sawahata and the method of manufacturing different display devices circuit as taught by Lee. This combination would improve the viewing experience for a user by improving speed of the signal output.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRE L MATTHEWS whose telephone number is (571)270-5806. The examiner can normally be reached Mon-Fri 9:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDRE L MATTHEWS/ Primary Examiner, Art Unit 2621