DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10, 12, 14-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10, 13-16 of U.S. Patent No. 12,298,918. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent contain each and every limitation of the claims of the instant application.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) retrieving and verifying master data responsive to a digital signature, retrieving computer-readable instructions, calculating a hash of the instructions, and determining whether the hash correlates to respective hash information of a hash table, which falls under mathematical concepts related to cryptography. This judicial exception is not integrated into a practical application because the additional recited elements, e.g. processing circuitry and memory devices, amount to simply implementing the abstract idea on a computer; as no practical effect results from mere comparison of hash values, the claim merely recites performing mathematical functions. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional limitations merely retrieve information from memory, which are well-understood, routine, conventional computer functions. Claims 1, 14, and 17 contain similar subject matter, and are thus each subject to this rejection. None of the respective dependent claims correct this and are therefore rejected for the same reasons.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nelson et al (WO 2023/055351).
Regarding Claim 14:
Nelson teaches a method, comprising:
retrieving, via a processing circuitry ([0017] as illustrated in Figure 1, the computing device 102 includes the secure microcontroller 108), master data from an off-chip data storage device ([0027] in order to create a root of trust in the secure memory 110, during the boot procedure of the computing device 102 the secure microcontroller 108 signature validates the decrypted plurality of pages stored in the secure memory 110; the signatures of each page are validated with a public key corresponding to the private key mentioned above), the master data to include a digital signature and a hash table ([0022] In some examples, the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; [0025] when pages included in the secure memory 110 are written (e.g., when the computing device instructions (e.g., code) are written), they are signed with a private key that does not exist in the computing device 102; such pages are then encrypted with signatures included in the encryption; [0027] in order to create a root of trust in the secure memory 110, during the boot procedure of the computing device 102 the secure microcontroller 108 signature validates the decrypted plurality of pages stored in the secure memory 110; the signatures of each page are validated with a public key corresponding to the private key mentioned above; if a signature fails, the validation table 114 is not trusted; if the signatures pass, the validation table 114 is trusted), the digital signature to verify the master data ([0027] the signatures of each page are validated with a public key corresponding to the private key mentioned above), the hash table including respective hash information for respective portions of computer-readable instructions stored by the off-chip data storage device ([0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; the term “hash” refers to a function to map data of arbitrary size to a bit array of a fixed size; the term “validation table” refers to a data structure that maps keys to values; the secure microcontroller 108 compares a hash associated with the page 112 with the validation table 114);
verifying the master data responsive to the digital signature ([0027] the signatures of each page are validated with a public key corresponding to the private key mentioned above);
retrieving a portion of computer-readable instructions from the off-chip data storage device ([0019] the secure microcontroller 108 can receive the request from the processor 104 that includes the page 112 to be retrieved and an address in the memory 106 to place the page 112; in response to receiving the request from the processor 104, the secure microcontroller 108 retrieves the page 112 from the memory 105);
calculating a hash value of the retrieved portion of the computer-readable instructions ([0021] the secure microcontroller 108 validates the page 112; the secure microcontroller 108 performs a validation operation on the page 112 to ensure the page 112 is unaltered (e.g., by an unauthorized user); [0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110); and
determining whether the calculated hash value correlates to respective hash information of the hash table of the master data for the respective retrieved portion of the computer-readable instructions ([0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; the secure microcontroller 108 compares a hash associated with the page 112 with the validation table 114; [0023] the hash of the page 112 matching the hash in the validation table 114).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 12-13, 15-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nelson, and further in view of Shanahan et al (PGPUB 2017/0289151).
Regarding Claim 1:
Nelson teaches an apparatus, comprising:
a semiconductor device package including a processing circuitry ([0017] as illustrated in Figure 1, the computing device 102 includes the secure microcontroller 108); and
an off-chip data storage device including master data and computer-readable instructions stored thereon ([0012] the page 112 is illustrated in Figure 1 as including dashed lines; the dashed lines of the page 112 indicate the page 112 may be accessed in a different memory 105 of the computing device 102 by the secure microcontroller 108 and placed in the memory 106, as is further described herein; the memory 105 can be, for instance, non-executable memory, executable memory, among other examples; [0013] during the demand paging process, the processor 104 executes an instruction associated with a process by attempting to load the page 112 from the memory 105 into the memory 106 for execution by the process; [0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110), the master data including a digital signature and a hash table ([0022] In some examples, the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; [0025] when pages included in the secure memory 110 are written (e.g., when the computing device instructions (e.g., code) are written), they are signed with a private key that does not exist in the computing device 102; such pages are then encrypted with signatures included in the encryption; [0027] in order to create a root of trust in the secure memory 110, during the boot procedure of the computing device 102 the secure microcontroller 108 signature validates the decrypted plurality of pages stored in the secure memory 110; the signatures of each page are validated with a public key corresponding to the private key mentioned above; if a signature fails, the validation table 114 is not trusted; if the signatures pass, the validation table 114 is trusted), the hash table including respective hash information for respective portions of the computer-readable instructions ([0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; the term “hash” refers to a function to map data of arbitrary size to a bit array of a fixed size; the term “validation table” refers to a data structure that maps keys to values; the secure microcontroller 108 compares a hash associated with the page 112 with the validation table 114),
wherein the processing circuitry to:
retrieve the master data from the off-chip data storage device ([0027] in order to create a root of trust in the secure memory 110, during the boot procedure of the computing device 102 the secure microcontroller 108 signature validates the decrypted plurality of pages stored in the secure memory 110; the signatures of each page are validated with a public key corresponding to the private key mentioned above);
verify the master data responsive to the digital signature ([0027] the signatures of each page are validated with a public key corresponding to the private key mentioned above);
retrieve a portion of the computer-readable instructions from the off-chip data storage device ([0019] the secure microcontroller 108 can receive the request from the processor 104 that includes the page 112 to be retrieved and an address in the memory 106 to place the page 112; in response to receiving the request from the processor 104, the secure microcontroller 108 retrieves the page 112 from the memory 105);
calculate a hash value of the retrieved portion of the computer-readable instructions ([0021] the secure microcontroller 108 validates the page 112; the secure microcontroller 108 performs a validation operation on the page 112 to ensure the page 112 is unaltered (e.g., by an unauthorized user); [0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110); and
determine whether the calculated hash value correlates to the respective hash information of the hash table of the master data for the respective retrieved portion of the computer-readable instructions ([0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; the secure microcontroller 108 compares a hash associated with the page 112 with the validation table 114; [0023] the hash of the page 112 matching the hash in the validation table 114).
Nelson does not explicitly teach the semiconductor device package including an on-chip memory device.
However, Shanahan teaches the concept of a semiconductor device package including an on-chip memory device ([abstract] dynamic loading of integrity protected modules into a secure enclave include a computing device having a processor with secure enclave support; the computing device divides an executable image into multiple chunks, hashes each of the chunks with corresponding attributes that affect security to generate a corresponding hash value, and generates a hash tree as a function of the hash values; [0019] the memory 126 is communicatively coupled to the processor 120 via the I/O subsystem 124, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 120, the memory 126, and other components of the computing device 100; the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip; [0020] the data storage device 128 may be embodied as any type of device or devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices, i.e. “off-chip data storage device”; the data storage device 128 may be used to store one or more executable binary images).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to combine the on-chip memory device teachings of Shanahan with the verified code page teachings of Nelson. Constructing a computing device as a system on a chip provides many benefits, such as improved miniaturization, ease of installation, and built-in compatibility. In addition, locating security components as part of the same circuit increases the challenge for an attacker to crack or defeat security features, as reduced size, shorter path lengths, and non-removable components make data interception expensive and difficult.
Regarding Claim 2:
Nelson in view of Shanahan teaches the apparatus of claim 1. In addition, Nelson teaches wherein the processing circuitry evicts a portion of the computer-readable instructions from the memory device responsive to a determination that the memory device is full ([0015] if the page 112 is not mapped to the memory 106, the processor 104 finds a page to free (e.g., eject) from the memory 106 and loads the page 112 to the memory 106); and
Shanahan teaches wherein the memory device is the on-chip memory device ([0019] the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip).
The rationale to combine Nelson and Shanahan is the same as provided for claim 1 due to the overlapping subject matter between claims 1 and 2.
Regarding Claim 3:
Nelson in view of Shanahan teaches the apparatus of claim 1. In addition, Nelson teaches the processing circuitry comprising a memory management unit (MMU) including a table representation of the respective portions of the computer-readable instructions, wherein one or more portion representations of the table representation are mapped to physical memory locations in the memory device ([0023] the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106; the secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed, i.e. “table representation mapped to physical memory locations”; the validation table 114 can accordingly track valid pages located in the memory 106 and can be utilized to periodically interrogate the pages in the memory 106 to ensure the pages loaded in the memory 106 are not altered, as is further described herein; validation table can therefore be seen as claimed MMU); and
Shanahan teaches wherein the memory device is the on-chip memory device ([0019] the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip).
The rationale to combine Nelson and Shanahan is the same as provided for claim 1 due to the overlapping subject matter between claims 1 and 3.
Regarding Claim 4:
Nelson in view of Shanahan teaches the apparatus of claim 3. In addition, Nelson teaches the processing circuitry to update the table representation responsive to the determination that the calculated hash value correlates to the respective hash information of the hash table for the respective retrieved portion of the computer-readable instructions ([0023] the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106; the secure microcontroller 108 validates the page 112 using the hash of the page 112 in order to ensure the page 112 has not been altered while residing in the secure memory 110; the secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed; the validation table 114 can accordingly track valid pages located in the memory 106 and can be utilized to periodically interrogate the pages in the memory 106 to ensure the pages loaded in the memory 106 are not altered, as is further described herein).
Regarding Claim 5:
Nelson in view of Shanahan teaches the apparatus of claim 4. In addition, Nelson teaches wherein updating the table representation comprises adding, or removing, a mapping of a representation of one of the respective portions of the computer-readable instructions to, or from, a memory location of the memory device ([0023] the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106; the secure microcontroller 108 validates the page 112 using the hash of the page 112 in order to ensure the page 112 has not been altered while residing in the secure memory 110; the secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed; the validation table 114 can accordingly track valid pages located in the memory 106 and can be utilized to periodically interrogate the pages in the memory 106 to ensure the pages loaded in the memory 106 are not altered, as is further described herein); and
Shanahan teaches wherein the memory device is the on-chip memory device ([0019] the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip).
The rationale to combine Nelson and Shanahan is the same as provided for claim 1 due to the overlapping subject matter between claims 1 and 5.
Regarding Claim 6:
Nelson in view of Shanahan teaches the apparatus of claim 1. In addition, Nelson teaches wherein the memory device includes pages having pre-determined addresses in memory, the pages to store respective portions of the computer-readable instructions ([0013] if the page 112 is mapped to the memory 106 (e.g., but not loaded in the memory 106), the processor 104 transmits a request to the secure microcontroller 108 to retrieve and place the page 112 in the memory 106, as is further described herein; [0016] to load the page 112 to the memory 106, the processor 104 transmits a request to the secure microcontroller 108; the request transmitted to the secure microcontroller 108 can include the page 112 to be received and the address in the memory 106 to place the page 112); and
Shanahan teaches wherein the memory device is the on-chip memory device ([0019] the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip).
The rationale to combine Nelson and Shanahan is the same as provided for claim 1 due to the overlapping subject matter between claims 1 and 6.
Regarding Claim 7:
Nelson in view of Shanahan teaches the apparatus of claim 6. In addition, Nelson teaches the processing circuitry to:
choose a page of the pages to evict responsive to a determination that each page of the pages is occupied ([0015] if the page 112 is not mapped to the memory 106, the processor 104 finds a page to free (e.g., eject) from the memory 106 and loads the page 112 to the memory 106);
evict data in the chosen page ([0015] if the page 112 is not mapped to the memory 106, the processor 104 finds a page to free (e.g., eject) from the memory 106 and loads the page 112 to the memory 106); and
store the retrieved portion of the computer-readable instructions in the chosen page ([0019] the secure microcontroller 108 can receive the request from the processor 104 that includes the page 112 to be retrieved and an address in the memory 106 to place the page 112; [0023] the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106).
Regarding Claim 8:
Nelson in view of Shanahan teaches the apparatus of claim 7. In addition, Nelson teaches wherein one portion is a least-recently used portion of a subset of the portions stored in the pages ([0023] pages located in the memory 106, i.e. plural pages; therefore, one page will be the “least-recently used portion”).
Regarding Claim 9:
Nelson in view of Shanahan teaches the apparatus of claim 7. In addition, Nelson teaches wherein one portion is a least used portion of a subset of the portions stored in the pages ([0023] pages located in the memory 106, i.e. plural pages; therefore, one page will be the “least used portion”).
Regarding Claim 12:
Nelson in view of Shanahan teaches the apparatus of claim 1. In addition, Nelson teaches the processing circuitry to enter an error state responsive to the determination that the calculated hash value does not correlate to the respective hash information of the hash table ([0024] in an example in which the hash of the page 112 does not match the hash in the validation table 114, the secure microcontroller 108 performs a recovery action).
Regarding Claim 13:
Nelson in view of Shanahan teaches the apparatus of claim 1. In addition, Nelson teaches the processing circuitry to:
execute the retrieved portion of the computer-readable instructions on the memory device responsive to a determination that the calculated hash value correlates to the respective hash information of the hash table ([0023] the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106; in response to the hash of the page 112 matching the hash in the validation table 114, the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106 included in the request received from the processor 104); and
do not execute the retrieved portion of the computer-readable instructions on the memory device responsive to a determination that the calculated hash value does not correlate to the respective hash information of the hash table ([0037] in response to the hash check not being passed (e.g., the hash of the page 112 in the memory 106 does not match a hash included in the validation table 114), the secure microcontroller 108 performs a recovery measure to reestablish the root of trust in the secure memory 110; for example, the secure microcontroller 108 causes the computing device 102 to reboot); and
Shanahan teaches wherein the memory device is the on-chip memory device ([0019] the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip).
The rationale to combine Nelson and Shanahan is the same as provided for claim 1 due to the overlapping subject matter between claims 1 and 13.
Regarding Claim 15:
Nelson teaches the method of claim 14. In addition, Nelson teaches the processing circuitry comprising a memory management unit (MMU), the MMU including a table representation of one or more portions of the computer-readable instructions mapped to locations in memory of an on-chip memory device.
Nelson does not explicitly teach wherein the memory device is an on-chip memory device.
However, Shanahan teaches the concept wherein a memory device is an on-chip memory device ([abstract] dynamic loading of integrity protected modules into a secure enclave include a computing device having a processor with secure enclave support; the computing device divides an executable image into multiple chunks, hashes each of the chunks with corresponding attributes that affect security to generate a corresponding hash value, and generates a hash tree as a function of the hash values; [0019] the memory 126 is communicatively coupled to the processor 120 via the I/O subsystem 124, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 120, the memory 126, and other components of the computing device 100; the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip; [0020] the data storage device 128 may be embodied as any type of device or devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices, i.e. “off-chip data storage device”; the data storage device 128 may be used to store one or more executable binary images).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to combine the on-chip memory device teachings of Shanahan with the verified code page teachings of Nelson. Constructing a computing device as a system on a chip provides many benefits, such as improved miniaturization, ease of installation, and built-in compatibility. In addition, locating security components as part of the same circuit increases the challenge for an attacker to crack or defeat security features, as reduced size, shorter path lengths, and non-removable components make data interception expensive and difficult.
Regarding Claim 16:
Nelson in view of Shanahan teaches the method of claim 15. In addition, Nelson teaches the method comprising retrieving the one or more portions of the computer-readable instructions responsive to an attempted execution of another portion of the computer-readable instructions represented in the MMU table but not mapped to a memory location of the memory device ([0013] during the demand paging process, the processor 104 executes an instruction associated with a process by attempting to load the page 112 from the memory 105 into the memory 106 for execution by the process; since the page 112 is not yet located (e.g., loaded) in the memory 106, a page fault error is generated; if the page 112 is not loaded in the memory 106, the processor stalls the process until the page 112 is retrieved; [0033] the secure microcontroller 108 then places the page 112 in the memory 106 at the address in the memory 106; that is, in response to the mathematical operation determining the page 112 has not been altered while residing in the secure memory 110, the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106 included in the request received from the processor 104; the secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed); and
Shanahan teaches wherein the memory device is the on-chip memory device ([0019] the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip).
The rationale to combine Nelson and Shanahan is the same as provided for claim 15 due to the overlapping subject matter between claims 15 and 16.
Regarding Claim 17:
Nelson teaches a computing system comprising:
an off-chip data storage device including master data and computer-readable instructions stored thereon ([0012] the page 112 is illustrated in Figure 1 as including dashed lines; the dashed lines of the page 112 indicate the page 112 may be accessed in a different memory 105 of the computing device 102 by the secure microcontroller 108 and placed in the memory 106, as is further described herein; the memory 105 can be, for instance, non-executable memory, executable memory, among other examples; [0013] during the demand paging process, the processor 104 executes an instruction associated with a process by attempting to load the page 112 from the memory 105 into the memory 106 for execution by the process; [0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110), the master data including a digital signature and a hash table ([0022] In some examples, the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; [0025] when pages included in the secure memory 110 are written (e.g., when the computing device instructions (e.g., code) are written), they are signed with a private key that does not exist in the computing device 102; such pages are then encrypted with signatures included in the encryption; [0027] in order to create a root of trust in the secure memory 110, during the boot procedure of the computing device 102 the secure microcontroller 108 signature validates the decrypted plurality of pages stored in the secure memory 110; the signatures of each page are validated with a public key corresponding to the private key mentioned above; if a signature fails, the validation table 114 is not trusted; if the signatures pass, the validation table 114 is trusted), the hash table including respective hash information for respective portions of the computer-readable instructions ([0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; the term “hash” refers to a function to map data of arbitrary size to a bit array of a fixed size; the term “validation table” refers to a data structure that maps keys to values; the secure microcontroller 108 compares a hash associated with the page 112 with the validation table 114); and
a semiconductor device package including ([0017] as illustrated in Figure 1, the computing device 102 includes the secure microcontroller 108):
a processing circuitry comprising a memory management unit (MMU) including a table representation of one or more portions of computer-readable instructions mapped to locations in memory of a memory device ([0023] the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106; the secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed, i.e. “table representation mapped to physical memory locations”; the validation table 114 can accordingly track valid pages located in the memory 106 and can be utilized to periodically interrogate the pages in the memory 106 to ensure the pages loaded in the memory 106 are not altered, as is further described herein; validation table can therefore be seen as claimed MMU),
wherein the processing circuitry to:
obtain a portion of the computer-readable instructions from the off-chip data storage device ([0019] the secure microcontroller 108 can receive the request from the processor 104 that includes the page 112 to be retrieved and an address in the memory 106 to place the page 112; in response to receiving the request from the processor 104, the secure microcontroller 108 retrieves the page 112 from the memory 105); and
determine whether a hash representation of the portion of the computer-readable instructions correlates to respective hash information of the hash table ([0022] the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110; the secure microcontroller 108 compares a hash associated with the page 112 with the validation table 114; [0023] the hash of the page 112 matching the hash in the validation table 114).
Nelson does not explicitly teach an on-chip memory device comprising a number of pages, at least one of the number of pages configured to store the hash table; and
wherein the memory device is an on-chip memory device.
However, Shanahan teaches the concept of an on-chip memory device comprising a number of pages, at least one of the number of pages configured to store the hash table ([abstract] dynamic loading of integrity protected modules into a secure enclave include a computing device having a processor with secure enclave support; the computing device divides an executable image into multiple chunks, hashes each of the chunks with corresponding attributes that affect security to generate a corresponding hash value, and generates a hash tree as a function of the hash values; [0019] the memory 126 is communicatively coupled to the processor 120 via the I/O subsystem 124, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 120, the memory 126, and other components of the computing device 100; the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip; [0020] the data storage device 128 may be embodied as any type of device or devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices, i.e. “off-chip data storage device”; the data storage device 128 may be used to store one or more executable binary images; [0018] the memory 126 may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein; in operation, the memory 126 may store various data and software used during operation of the computing device 100 such as operating systems, applications, programs, libraries, and drivers; additionally, part of the memory 126 may be used as an enclave page cache (EPC) to store encrypted code and/or data for the secure enclaves established by the processor 120); and
wherein the memory device is an on-chip memory device ([0019] as above).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to combine the on-chip memory device teachings of Shanahan with the verified code page teachings of Nelson. Constructing a computing device as a system on a chip provides many benefits, such as improved miniaturization, ease of installation, and built-in compatibility. In addition, locating security components as part of the same circuit increases the challenge for an attacker to crack or defeat security features, as reduced size, shorter path lengths, and non-removable components make data interception expensive and difficult.
Regarding Claim 19:
Nelson in view of Shanahan teaches the computing system of claim 17. In addition, Nelson teaches wherein the processing circuitry to enter an error state responsive to a determination that the hash representation of the portion of the computer-readable instructions does not correlate to the respective hash information of the hash table ([0024] in an example in which the hash of the page 112 does not match the hash in the validation table 114, the secure microcontroller 108 performs a recovery action).
Regarding Claim 20:
Nelson in view of Shanahan teaches the computing system of claim 17. In addition, Nelson teaches the processing circuitry further comprising a processing core, the processing core to execute the respective portion of the computer-readable instructions responsive to a determination that the portion of the computer-readable instructions correlates to respective hash information of the hash table ([0023] the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106; in response to the hash of the page 112 matching the hash in the validation table 114, the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106 included in the request received from the processor 104).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nelson in view of Shanahan, and further in view of Kim et al (PGPUB 2006/0026372).
Regarding Claim 10:
Nelson in view of Shanahan teaches the apparatus of claim 7.
Neither Nelson nor Shanahan explicitly teaches wherein one portion is a randomly chosen portion of a subset of the portions stored in the pages.
However, Kim teaches the concept wherein a portion is a randomly chosen portion of a subset of portions stored in pages ([0008] however, if there are no free pages in the main memory 120, one of the pages of the main memory 120 that have already been used is selected, and the predetermined data read from the flash memory 150 is written to the selected page of the main memory 120; [0080] the pages included in the CFLRU list 470 may be sequentially chosen as the page to be replaced in a random order).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to combine the randomly chosen memory page teachings of Kim with the verified code page teachings of Nelson in view of Shanahan, in order to incorporate memory management techniques that can minimize the number of write operations performed on a flash memory and can enhance a memory hit rate (Kim, [0003]).
Claim(s) 11, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nelson in view of Shanahan, and further in view of White et al (PGPUB 2022/0318040).
Regarding Claim 11:
Nelson in view of Shanahan teaches the apparatus of claim 1.
Neither Nelson nor Shanahan explicitly teaches wherein the processing circuitry includes a direct memory access (DMA) circuitry separate from the processing circuitry, the DMA circuitry to retrieve the respective portions of the computer-readable instructions from the off-chip data storage device independently from the processing circuitry and store the retrieved portion of the computer-readable instructions on the on-chip memory device.
However, White teaches the concept wherein processing circuitry includes a direct memory access (DMA) circuitry separate from the processing circuitry, the DMA circuitry to retrieve respective portions of the computer-readable instructions from an off-chip data storage device independently from the processing circuitry and store the retrieved portion of the computer-readable instructions on a memory device ([0021] In some implementations, the hardware data mover 126 includes a processor 130, such as a security processor, and a direct memory access (DMA) engine 135 that in some implementations is implemented as a micro controller that executes firmware; [0023] The processor 130 receives page move commands 168 and other commands from the processor 112 and in the case of move commands employs the DMA engine 135 to make page moves from for example a slower memory tier 118 to a faster memory tier 120); and
Shanahan teaches wherein the memory device is the on-chip memory device ([0019] the I/O subsystem 124 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 120, the memory 126, and other components of the computing device 100, on a single integrated circuit chip).
The rationale to combine Nelson and Shanahan is the same as provided for claim 15 due to the overlapping subject matter between claims 15 and 16.
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to combine the DMA circuitry teachings of White with the verified code page teachings of Nelson in view of Shanahan. DMA chips and circuits are common features in computer architecture which are specially designed to perform memory swaps. It would therefore be beneficial to incorporate DMA circuits into a system for validating memory pages in order to improve efficiency and ease of implementation in a system which frequently moves memory pages in order to perform page swaps and validations.
Regarding Claim 18:
Nelson in view of Shanahan teaches the computing system of claim 17.
Neither Nelson nor Shanahan explicitly teaches the processing circuitry further comprising direct memory access (DMA) circuitry.
However, White teaches the concept of processing circuitry further comprising direct memory access (DMA) circuitry ([0021] In some implementations, the hardware data mover 126 includes a processor 130, such as a security processor, and a direct memory access (DMA) engine 135 that in some implementations is implemented as a micro controller that executes firmware; [0023] The processor 130 receives page move commands 168 and other commands from the processor 112 and in the case of move commands employs the DMA engine 135 to make page moves from for example a slower memory tier 118 to a faster memory tier 120).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to combine the DMA circuitry teachings of White with the verified code page teachings of Nelson in view of Shanahan. DMA chips and circuits are common features in computer architecture which are specially designed to perform memory swaps. It would therefore be beneficial to incorporate DMA circuits into a system for validating memory pages in order to improve efficiency and ease of implementation in a system which frequently moves memory pages in order to perform page swaps and validations.
Conclusion
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/FORREST L CAREY/Examiner, Art Unit 2491
/WILLIAM R KORZUCH/Supervisory Patent Examiner, Art Unit 2491
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