DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 07/14/2026. Claims 1, 4-9, 12-17, and 19-20 have been amended. Claims 1-20 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application, 17/990126 filed on 11/18/2022, under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Response to Amendments and Arguments
Applicant’s amendment and remarks have been fully considered, with the Examiner’s response set forth below.
(1)In view of the amendments, double patenting rejections of claims 1-20 have been withdrawn.
(2) Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(3) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 8, 9, 12, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US11,373,710), hereinafter Hsu in view of Imamoto (US2022/0148656), hereinafter Imamoto
Regarding claims 1 and 9, taking claim 1 as exemplary, Hsu teaches a memory device comprising:
one or more memory arrays (Hsu, col.14, line 50-col.15, line 3, the group of memory cells);
control logic (control circuitry 310), operatively coupled with the one or more memory arrays (Hsu, col.6, line 61 – col.7, line10, each memory die 300 includes a memory structure 326, control circuitry 310; Fig. 3A), configured to perform operations comprising:
determining that a memory array of the one or more memory arrays is associated with a memory die in a suspended state, wherein the memory die in the suspended state is allocated a reserved current budget that is determined based on predicted current consumption in anticipation of one or more predicted commands directed to the memory die upon returning from the suspended state (Hsu, col.17, lines 20-31, die 0 determined that if the memory operation were not halted, then the high current portion would have occurred in time slot 5, which is not allocated to die 0 for high current. Hence, die 0 halts the memory operation … Die 0 resumes the memory operation in the next available time slot 0, such that the high current portion occurs during the time slot allocated to die 0 for high current; col.16, line 61 – col.17. line 6, The dashed lines labeled “Threshold” represents a threshold that defines whether current usage is above or below a “high current.”), wherein the one or more predicted commands are associated with one or more predicted media access operations (Hsu, col.14, lines, 14-29, The program phase is one example of a memory operation; col.17, lines 20-31, memory operation), and wherein the reserved current budget comprises at least a portion of a previous current budget allocated to the memory die prior to entering the suspended state (Hsu, col.19 line 65 – col.20, line 8, Step 1106 includes performing a portion of a memory operation having a current usage below a threshold; );
receiving a set of actual commands associated with at least one actual media access operation to be performed on the memory array (Hsu, col.7, lines 11-26, Commands and data are transferred between the controller 102 and the memory die 300 via memory controller interface 315); and
causing the set of actual commands to be processed in a manner determined in accordance with the reserved current budget (Hsu, col.16 line 51 – col.17, line 6, Die 0 resumes the memory operation in the next available time slot 0, such that the high current portion occurs during the time slot allocated to die 0 for high current … Current profiles 608 a and 608 b together represent the current used by a memory operation such as a program, a verify, a read, or an erase. The memory operation was started during time slot 6; col.20, lines, 20-25; Fig.11).
Hsu does not explicitly teach determining that a memory array of the one or more memory arrays is associated with a memory die in a suspended state, as claimed.
However, Hsu in view of Imamoto teaches determining that a memory array of the one or more memory arrays is associated with a memory die in a suspended state (Imamoto, [0265], information that can determine which plane group to suspend the write sequence may be input to the memory die MD).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hsue to incorporate teachings of Imamoto to determine a memory array that is associated with a memory die in a suspended state. A person of ordinary skill in the art would have been motivated to combine the teachings of Hsu with Imamoto because it improves efficiency of the storage system disclosed in the Hsu to identify and take appropriate actions when a requested memory array is determined to be associated with a die in a suspended state.
Claim 9 has similar limitations as claim 1 and is rejected for the similar reasons.
Regarding claims 4 and 12, taking claim 4 as exemplary, the combination of Hsu teaches all the features with respect to claim 1 as outlined above. The combination of Hsu further teaches the memory device of claim 1, wherein the at least one actual media access operation comprises at least one of: a read command (Hsu, col.20, lines 34-54, The memory operation could be, for example, a read of non-volatile memory cells) or an independent wordline read command.
Claim 12 has similar limitations as claim 4 and is rejected for the similar reasons.
Regarding claims 8 and 16, taking claim 8 as exemplary, the combination of Hsu teaches all the features with respect to claim 1 as outlined above. The combination of Hsu further teach the memory device of claim 1, wherein: a single actual command of the set of actual commands has a command current budget that is less than or equal to the reserved current budget, and causing the set of actual commands to be processed further comprises enabling a processor to process the single actual command (Hsu, col. 20, lines 20-25, die 0 resumes the memory operation at time slot 0 such that the high current portion is performed during time slot 0); or each actual command of the set of actual commands has a command current budget that is greater than the reserved current budget, and causing the set of actual commands to be processed further comprises causing a delay to handle at least one actual command of the set of actual commands.
Claim 16 has similar limitations as claim 8 and is rejected for the similar reasons.
Claim(s) 2 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hsu and Imamoto as applied to claims 1 and 9 respectively above, and further in view of Kim et al. (US 2021/0223851), hereinafter Kim.
Regarding claims 2 and 10, taking claim 2 as exemplary, the combination of Hsu teaches all the features with respect to claim 1 as outlined above. The combination of Hsu does not explicitly teach the memory device of claim 1, wherein the reserved current budget is determined in accordance with a memory device specification defining a target delay, as claimed.
However, the combination of Hsu in view of Kim teaches the memory device of claim 1, wherein the reserved current budget is determined in accordance with a memory device specification defining a target delay (Kim, [0020]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hsu to incorporate teachings of Kim to determine power budget of a storage device in accordance with a target delay of the storage device. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Hsu with Kim because it improves efficiency and performance of the storage system disclosed in the combination of Hsu by determining an optimized power budget for the storage system.
Claim 10 has similar limitations as claim 2 and is rejected for the similar reasons.
Claim(s) 3 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hsu and Imamoto as applied to claims 1 and 9 respectively above, and further in view of Seong et al. (US2021/0096773), hereinafter Seong.
Regarding claims 3 and 11, taking claim 3 as exemplary, the combination of Hsu teaches all the features with respect to claim 1 as outlined above. The combination of Hsu further teaches the memory device of claim 1, wherein the operations further comprise performing peak power management (PPM) initialization with respect to the memory die to enable reservation of the reserved current budget (Hsu, col.3, lines 15-55, Each die is allocated one or more of the time slots in each the repeating set in which to perform high current (or high power) portions of memory operations. The current could be a peak current or an average current), and wherein performing PPM initialization comprises receiving a set feature command to enable the reservation of the reserved current budget.
The combination of Hsu does not explicitly teach wherein performing PPM initialization comprises receiving a set feature command to enable the reservation of the reserved current budget, as claimed.
However, the combination of Hsu in view of Seong teaches wherein performing PPM initialization comprises receiving a set feature command to enable the reservation of the reserved current budget (Seong, [0067]; claim 17, the memory controller provides a set power command for setting the voltage threshold range to the memory device; the set power command includes at least one of a set feature command and a set parameter command.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hsu to incorporate teaching of Seong to use a set feature command to set power threshold for storage unit. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Hsu with Seong because it improves efficiency of the storage system disclosed in the combination of Hsu by using standard commands for storage system communication.
Claim 11 has similar limitations as claim 3 and is rejected for the similar reasons.
Claim(s) 5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hsu and Imamoto as applied to claims 1 and 9 respectively above, and further in view of Mukker et al. (US2021/0109587), hereinafter Mukker.
Regarding claims 5 and 13, taking claim 5 as exemplary, the combination of Hsu teaches all the features with respect to claim 1 as outlined above. The combination of Hsu teaches resuming operation on a suspended die, nevertheless, the combination of Hsu does not explicitly teach the memory device of claim 1, wherein the operations further comprise: after processing the set of actual commands, receiving a resume command; and in response to receiving the resume command, causing the memory die to be placed in an active state, as claimed.
However, the combination of Hsu in view of Mukker teaches the memory device of claim 1, wherein the operations further comprise: after processing the set of actual commands, receiving a resume command; and in response to receiving the resume command, causing the memory die to be placed in an active state (Mukker, [0036]; [0037], Once the threshold of cumulative activity has been reached, the power management circuitry 204 can send a message over the PCIe bus 120 using the NVMe standard protocol to the host circuitry 112 to transition power state; [0038], The Host I/O commands are limited so that the solid state drive 102 is in a non-operational power state (idle power state) quickly but enough to keep the solid state drive 102 efficiently busy when sufficient power budget has reaccumulated and the solid state drive 102 transitions to operational power state (active power state)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hsu to incorporate teachings of Mukker to instruct a memory die to transition to an active power state from a low-power state after a halted memory operation has been resumed (i.e. the threshold of cumulative activity has been reached). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Hsu with Mukker because it improves efficiency of the storage system disclosed in the combination of Hsu by allowing a host to set a memory unit in a specific power state when specific criteria is satisfied.
Claim 13 has similar limitations as claim 5 and is rejected for the similar reasons.
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hsu and Imamoto as applied to claims 1 and 9 respectively above, and further in view of Margetts et al. (US2019/0065086), hereinafter Margetts and Hamilton (US2010/0185883), hereinafter Hamilton.
Regarding claims 6 and 14, taking claim 6 as exemplary, the combination of Hsu teaches all the features with respect to claim 1 as outlined above. The combination of Hsu does not explicitly teach the memory device of claim 1, wherein: each actual command of the set of actual commands has a corresponding command current budget that is less than or equal to the reserved current budget; and processing the set of actual commands further comprises enabling a set of processors to process the set of actual commands, as claimed.
However, the combination of Hsu in view of Margetts teaches the memory device of claim 1, wherein: each actual command of the set of actual commands has a corresponding command current budget that is less than or equal to the reserved current budget; and processing the set of actual commands further comprises enabling a set of processors to process the set of actual commands (Margetts, [0032], The estimation of the power may be determined by accessing a register or look-up table for an estimated current associated with a command type. The power budget controller 105 receives the estimation of the power for the command and determines if the present power budget can allow the execution of the command. This may be determined by comparing the estimated power of the command to a difference between the value of the budget register 111 containing the present power budget in Joules per second and the value of the credit register 109 containing an accounting of the amount of power being currently used by the execution of various programs and commands in the SSD. If the value of the credit register 109 is less than the present power budget value stored in the budget register 111 by an amount equal to or greater than the estimated power of the command, the power budget controller 105 will grant the first decision logic 106 permission to transmit the command for execution on the banks ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hsu to incorporate teachings of Margetts to process a plurality of commands in response to determining an estimated power consumption does not exceed an allocated power budget. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Hsu with Margetts because it improves efficiency and reliability of the storage system disclosed in the combination of Hsu by ensuring sufficient power is provided to I/O processing.
The combination of Hsu does not explicitly teach processing the set of actual commands further comprises enabling a set of processors to process the set of actual commands, as claimed.
However, the combination of Hsu in view of Hamilton teaches processing the set of actual commands further comprises enabling a set of processors to process the set of actual commands (Hamilton, [00225], power conservation techniques can also be applied to processors; claim 9, The system of claim 5, further comprising power components to enable or disable one or more processors in order to mitigate system power consumption, the power components employ voltage or frequency scaling to control power consumption).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hsu to incorporate teachings of Hamilton to apply power conservation techniques to processors as well as memory devices and enable processors when power credits reach a threshold for processing I/O requests. A person of ordinary skill in the art would have been motivated to combine the teachings of Hsu with Hamilton because it improves efficiency of the storage system disclosed in the combination of Hsu by switching into lower power states when it’s appropriated which reduces power usage of the storage system.
Claim 14 has similar limitations as claim 6 and is rejected for the similar reasons.
Claim(s) 7 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hsu and Imamoto as applied to claims 1 and 9 respectively above, and further in view of Deng (US2020/0217672), hereinafter Deng.
Regarding claims 7 and 15, taking claim 7 as exemplary, the combination of Hsu teaches all the features with respect to claim 1 as outlined above. The combination of Hsu does not explicitly teach the memory device of claim 1, wherein: half of a total number of actual commands of the set of actual commands has a command current budget that is less than or equal to the reserved current budget; each actual command having a command current budget that is less than or equal to the reserved current budget is comprised within a subset of the set of actual commands; and causing the set of actual commands to be processed further comprises enabling a set of processors to process the subset, as claimed.
However, the combination of Hsu in view of Deng teaches the memory device of claim 1, wherein: half of a total number of actual commands of the set of actual commands has a command current budget that is less than or equal to the reserved current budget; each actual command having a command current budget that is less than or equal to the reserved current budget is comprised within a subset of the set of actual commands; and causing the set of actual commands to be processed further comprises enabling a set of processors to process the subset (Deng, [0046], the algorithm may output an indication to the agent that the number of assigned tasks 504 is greater than the threshold number, and enable the agent to either provide input indicative of a desire to proceed with the approximation algorithm or to select a subset of the assigned tasks 504 that is less than the threshold number so that acceptable routes for the selected subset may be determined; Note – subset can be half of the total number assigned tasks; Note – m can be one half of the total number of data operations.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hsu to incorporate teachings of Deng to compare a subset (i.e. half) of assigned tasks to a threshold in response to determining the assigned tasks exceed the threshold. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Hsu with Deng because it improves efficiency of the storage system disclosed in the combination of Hsu by allowing a subset of assigned tasks to be processed if a full set of assigned tasks is not allowed.
Claim 15 has similar limitations as claim 7 and is rejected for the similar reasons.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US2020/0209944), hereinafter Palmer in view of Kim et al. (US2021/0223851), hereinafter Kim, and further in view of Hsu et al. (US11,373,710), hereinafter Hsu.
Regarding claim 17, Palmer teaches a memory device comprising:
a memory array associated with a memory die (Palmer, [0021], a memory array 120 including, for example, a number of individual memory devices (e.g., each memory device being a stack of three-dimensional (3D) NAND die)); and
control logic, operatively coupled with the memory array (Palmer, [0021], The managed memory device 110 includes a memory controller 115 and a memory array 120), to perform operations comprising:
enabling reservation of a reserved current budget allocated to the memory die in a suspended state, wherein the reserved current budget is reserved in accordance with a memory device specification (Palmer, [0057], memory controller to arbitrate activation and de-activation of the die of a multiple memory die device to maintain as many active die as possible while still managing power consumption of the memory device to a power budget … the power budget scheme and parameters can be derived from benchmark testing of the memory device; [0076], the power budget threshold can be for a memory device, a memory die) defining a target delay, wherein the reserved current budget is determined based on predicted current consumption in anticipation of one or more predicted commands directed to the memory die upon returning from the suspended state, wherein the one or more predicted commands are associated with one or more predicted media access operations, and wherein the reserved current budget comprises at least a portion of a previous current budget allocated to the memory die prior to entering the suspended state;
initiating execution of a media access operation on the memory array (Palmer, [0060], If there are buffered memory requests pending for the die (X), the memory requests can begin to be executed at 609. At 611, as memory request for the die (X) are executing, the active timer can be monitored and evaluated. In certain examples, each die can remain active for a predetermined interval); and
causing the memory die to be placed in the suspended state to suspend execution of the media access operation with the reserved current budget.
Palmer does not explicitly teach wherein the reserved current budget is reserved in accordance with a memory device specification defining a target delay, wherein the reserved current budget is determined based on predicted current consumption in anticipation of one or more predicted commands directed to the memory die upon returning from the suspended state, wherein the one or more predicted commands are associated with one or more predicted media access operations, and wherein the reserved current budget comprises at least a portion of a previous current budget allocated to the memory die prior to entering the suspended state; and causing the memory die to be placed in a suspended state to suspend execution of the media access operation with the reserved current budget, as claimed.
However, Palmer in view of Kim teaches wherein the reserved current budget is reserved in accordance with a memory device specification defining a target delay (Kim, [0020]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Palmer to incorporate teachings of Kim to determine power budget of a storage device in accordance with a delay of the storage device. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Palmer with Kim because it improves efficiency and performance of the storage system disclosed in the combination of Palmer by determining an optimized power budget for the storage system.
The combination of Palmer does not explicitly teach wherein the reserved current budget is determined based on predicted current consumption in anticipation of one or more predicted commands directed to the memory die upon returning from the suspended state, wherein the one or more predicted commands are associated with one or more predicted media access operations, and wherein the reserved current budget comprises at least a portion of a previous current budget allocated to the memory die prior to entering the suspended state and causing the memory die to be placed in a suspended state to suspend execution of the media access operation with the reserved current budget, as claimed.
However, the combination of Palmer in view of Hsu teaches wherein the reserved current budget is determined based on predicted current consumption in anticipation of one or more predicted commands directed to the memory die upon returning from the suspended state (Hsu, col.17, lines 20-31, die 0 determined that if the memory operation were not halted, then the high current portion would have occurred in time slot 5, which is not allocated to die 0 for high current. Hence, die 0 halts the memory operation … Die 0 resumes the memory operation in the next available time slot 0, such that the high current portion occurs during the time slot allocated to die 0 for high current; col.16, line 61 – col.17. line 6, The dashed lines labeled “Threshold” represents a threshold that defines whether current usage is above or below a “high current.”), wherein the one or more predicted commands are associated with one or more predicted media access operations (Hsu, col.14, lines, 14-29, The program phase is one example of a memory operation; col.17, lines 20-31, memory operation), and wherein the reserved current budget comprises at least a portion of a previous current budget allocated to the memory die prior to entering the suspended state (Hsu, col.19 line 65 – col.20, line 8, Step 1106 includes performing a portion of a memory operation having a current usage below a threshold);
initiating execution of a media access operation on the memory array (Hsu, col.17, lines 20-31, The memory operation was started during time slot 4, as indicated by current profile 604 a.);
causing the memory die to be placed in the suspended state to suspend execution of the media access operation with the reserved current budget (Hsu, col.17, lines 20-31, However, die 0 determined that if the memory operation were not halted, then the high current portion would have occurred in time slot 5, which is not allocated to die 0 for high current. Hence, die 0 halts the memory operation; Fig.11).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Palmer to incorporate teachings of Hsu to initiate a memory operation and halt the memory operation on the die when the anticipated current required to complete the memory operation exceeds a current threshold. Allocate a high current slot to the die in order for the die to complete the unfinished memory operation. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Palmer with Hsu because it improves efficiency of the storage system disclosed in the combination of Palmer by preventing many memory dies to have high/peak current usages at the same time.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer, Kim, and Hsu as applied to claim 17 above, and further in view of Seong et al (US2021/0096773), hereinafter Seong.
Regarding claim 18, the combination of Palmer teaches all the features with respect to claim 17 as outlined above. The combination of Palmer does not explicitly teach the memory device of claim 17, wherein the operations further comprise receiving a set feature command to enable the reservation of the reserved current budget, as claimed.
However, the combination of Palmer in view of Seong teaches the memory device of claim 17, wherein the operations further comprise receiving a set feature command to enable the reservation of the reserved current budget (Seong, claim 17, the memory controller provides a set power command for setting the voltage threshold range to the memory device; the set power command includes at least one of a set feature command and a set parameter command.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Palmer to incorporate teaching of Seong to use a set feature command to set power threshold for storage unit. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Palmer with Seong because it improves efficiency of the storage system disclosed in the combination of Palmer by using standard commands for storage system communications.
Allowable Subject Matter
Claims 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 19 recites “[t]he memory device of claim 17, wherein the operations further comprise: after causing the memory die to be placed in the suspended state, receiving a set of actual commands to execute at least one actual media access operation; in response to receiving the set of actual commands, causing the set of actual commands to be processed in a manner determined in accordance with the reserved current budget; after processing the set of actual commands, receiving a resume command; and in response to receiving the resume command, causing the memory die to be placed in an active state”.
The above-noted limitation, in combination with the other limitation of the claims, are neither disclosed nor suggested by the prior art of record. Therefore, in the context of claims 17 and 19 as a whole, the prior art does not teach the claimed subject matter. Thus, the subject matter of claim 19 is allowable. Claim 20 depends on claim 19 and is objected for the similar reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCI N WONG whose telephone number is (571)272-4117. The examiner can normally be reached Monday-Friday 9am -6pm.
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/NANCI N WONG/Primary Examiner, Art Unit 2137
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