DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims below have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ma, US Pub. No. 2020/0285544 in view of Ueda, US Pub. No. 2019/0286203.
Regarding claim 1, Ma teaches a method of driving a display device (fig. 3) comprising a display panel (fig. 4, display 636), a processor (fig. 4, processor 630), and a first memory (fig. 4, memory 632), the method comprising: initializing the first memory upon power-on (fig. 3, steps 306, 318, 320); and organizing data in the first memory (fig. 3, steps 302, 304, 326; in particular Ma teaches organizing data in memory by backing up desired data to non-volatile memory prior to a power-off event and restoring the data after power-on).
Ma fails to explicitly teach providing a power-off notification command to the first memory.
However, in the same field of endeavor, Ueda teaches a control device including a CPU module 14 comprising a CPU, RAM, ROM, and nonvolatile memory (see [0027]). Ueda further teaches a power shutdown detection part 17 configured to monitor a voltage level and output a power shutdown detection signal notifying CPU module 14 of a power shutdown when the voltage falls below a reference value (see [0028]). Upon receiving the power shutdown notification, CPU module 14 performs a termination process including storing data indicative of the state of the device immediately before power shutdown in the built-in nonvolatile memory ([0028]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ma’s method such that a power-off notification is provided to the processor/memory system and the data in the first memory is organized in response to the power-off notification as taught by Ueda. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to preserve data needed following restoration of power.
Regarding claim 2, the combination of Ma and Ueda teach periodically storing data generated during operation of the display panel in the first memory (Ma, fig. 3, step 302; Barton, fig. 6, step 603; it would have been obvious to one of ordinary skill in the art to periodically store data generated during operation in order to ensure updated data is available for recovery) by: storing the data in the first memory (Ma, fig. 3, step 302; fig. 4, flash memory 632); the organizing the data in the first memory by providing a power-off notification (PON) command to the first memory (Ma, fig. 3, step 304; Ueda, [0027-0028]); and periodically repeating the storing of the data and the organizing of the data (Ma, fig. 3; Ueda, [0027-0028]).
Regarding claim 3, the combination of Ma and Ueda teaches further comprising periodically storing in the first memory, accumulated data indicating driving time of pixels of the display panel (Ma, fig. 3, step 302; fig. 4, display 624; Ueda, [0027-0028]).
Regarding claim 4, the combination of Ma and Ueda teaches further comprising: generating sensing data by sensing characteristics of pixels comprised in the display panel based on a signal for power-off being provided to the display device (Ueda, [0027-0028]); storing the sensing data in the first memory (Ueda, [0027-0028]); and providing the PON command to the first memory to organize the data in the first memory (Ma, fig. 3, Ueda, [0027-0028]).
Regarding claim 5, the combination of Ma and Ueda teaches further comprising storing, in a second memory of the display device, performance result information indicating whether the first memory has organized the data during a power-off procedure of the display device (Ma, fig. 3, backup before power-off, restore after reboot; fig. 4, memories 606, 608, 612; Ueda, [0027-0028]).
Regarding claim 6, the combination of Ma and Ueda teaches reading the performance result information stored in the second memory (Ma, fig. 3, system checks memory/state during initialization; Ueda, [0027-0028]).
Regarding claim 7, the combination of Ma and Ueda teaches anticipating, with the processor, delay in initialization of the first memory based on the performance result information indicating that the first memory has organized the data not being read (Ma, fig. 3, memory initialization, checks, restoring operations before boot; Barton, [0027-0028]).
Regarding claim 8, it has similar limitations to those of claim 4 and is rejected on the same grounds presented above.
Regarding claim 9, it has similar limitations to those of claim 4 and is rejected on the same grounds presented above.
Regarding claim 10, it has similar limitations to those of claim 6 and is rejected on the same grounds presented above.
Regarding claim 11, it has similar limitations to those of claim 7 and is rejected on the same grounds presented above.
Regarding claim 12, it has similar limitations to those of claim 7 and is rejected on the same grounds presented above.
Regarding claim 13, Ma teaches wherein the first memory comprises an embedded MultiMedia Card (eMMC), and wherein the second memory comprises an electrically erasable programmable read-only memory (EEPROM) (fig. 4, flash memory 632, ROM 606, storage 612).
Regarding claim 14, Ma teaches further comprising performing, by the first memory, at least one of a data integrity check operation, a garbage collection operation, or a wear-leveling operation to initialize the first memory upon the power-on (fig. 3, system power on, initialization sequence; fig. 4, flash memory 632 inherently performs garbage collection, wear-leveling and integrity management).
Regarding claim 15, Ma and Ueda teach wherein the first memory performs at least one of the data integrity check operation, the garbage collection operation, or the wear-leveling operation in response to the PON command (Ma, fig. 3, power event triggers memory operations; Ueda, [0027-0028]).
Regarding claim 16, it is a display device of claim 1 (and dependents) and is rejected on the same grounds presented above.
Regarding claim 17, it has similar limitations to those of claim 13 and is rejected on the same grounds presented above.
Regarding claim 18, it has similar limitations to those of claim 3 and is rejected on the same grounds presented above.
Regarding claim 19, it is an electronic device of claim 1 (and dependents) and is rejected on the same grounds presented above.
Regarding claim 20, Ma and Ueda teach wherein the electronic device could be any one of these well-known electronic device categories as taught in claim 19. It would have been obvious to implement the combined teachings of Ma and Ueda in any of the recited device types as a matter of design choice.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Zapatylak et al. (US Pub. No. 2024/0303192) teaches power loss protection.
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/KENNETH B LEE JR/Primary Examiner, Art Unit 2625
