DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This office action is in response to the Application filed on 05/12/2025.
Claims 1-25 are presented for examination.
Information Disclosure Statement
There was no information disclosure statement (IDS) submitted.
Drawings
The drawings submitted on 05/12/2025 are accepted.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8-15 and 18 -25 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al. (US 2021/0011767; hereinafter Luo) in view of in view of Tanpairoj et al. (US 2022/0129168 A1; hereinafter Tanpairoj) and Colella et al. (US 2022/0374163 A1; hereinafter Colella).
Regarding independent claims 1, 11 and 21, taking claim 1 as exemplary analysis, Luo teaches A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices (Fig. 1 & [0025], discloses a storage system 110 including non-volatile memory 112 (one or more flash dies/LUNs) and a memory controller 111 (processing circuitry) coupled with the memory devices) and configured to cause the memory system to:
determine whether a quantity of data stored to the memory system satisfies a first threshold value, wherein the quantity of data is associated with a logical saturation of the memory system (Abstract, a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data.
Luo, claims 1 & 5 describing MLS tracking, static vs. dynamic SLC pools, reallocation formula such as static SLC size = (100 – MLS)/3, and endurance differences;
Luo presents equations and a table (FIG. 3B) that map LS to static SLC cache size and over-provisioning, and the controller uses MLS and threshold values to determine whether the device has reached particular saturation levels that warrant reconfiguring cache size. Thus, Luo teaches determining whether a logical-saturation-associated quantity (percentage of device capacity written) satisfies a threshold value),
However, Luo does not expressly teach wherein a block of memory cells of the memory system is allocated to a write booster cursor; disable operation of a write booster mode of the memory system based at least in part on determining that the quantity of data satisfies the first threshold value; and allocate the block of memory cells of the write booster cursor to store data based at least in part on disabling the operation of the write booster mode.
In analogous art of dynamically managing SLC cache resources, Tanpairoj discloses dynamically reconfiguring memory cells of an array between an SLC cache pool and an MLC (or TLC) storage pool based on a behavior profile that includes rules tied to logical saturation / LBA saturation thresholds (See Tanpairoj, Abstract). Specifically, when current logical saturation exceeds a target threshold, the system reconfigures cells from the SLC cache pool to the MLC storage pool, thereby reducing the effective size of the SLC cache and increasing usable storage capacity. The profile can include usage rules for when to bypass the SLC cache entirely. (See Tanpairoj, claims 1, 4–6; [0066]–[0070] describing LBA saturation thresholds triggering SLC-to-MLC reconfiguration and host-updatable profiles.)
Colella discloses a memory system that supports a write booster mode in which data is written using SLC (single-bit-per-cell) configuration to a write booster virtual block / open cursor (see [0069]). Colella teaches classifying incoming data as write booster data or non-write booster data. When the write booster signal/mode is disabled (or for non-booster data), the system routes writes to a normal virtual block/cursor instead of the write booster cursor (see [0077], [0080]). Colella further teaches performing maintenance-related operations (such as garbage collection data relocation/aggregation with write buffer data) when flushing or handling data associated with cursors, particularly during memory management operations like cache synchronization or GC. Virtual blocks spanning planes/devices are explicitly used (see [0078]).
Colella further describes in [0077] that write booster data may be associated with a first size threshold (e.g., 16 KB to fill a page in SLC mode), and non-write booster data with a second size threshold (e.g., 48 KB for TLC mode); the memory system may program write-buffer data into an “open write booster cursor” (e.g., SLC cursor) when in write-booster mode and uses a TLC cursor for non-write-booster mode. Colella explains that write-booster mode uses SLC-style single-bit programming, whereas non-write booster mode uses TLC-style multi-bit programming (three bits per cell) for the same virtual block when configured differently
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the write booster / SLC cache management system of Luo (which already dynamically reduces dedicated SLC resources based on increasing logical saturation / MLS to reclaim capacity and improve OP) by incorporating the explicit SLC-to-MLC cell reconfiguration triggered by saturation thresholds taught in Tanpairoj, and by implementing the management using a dedicated write booster cursor (virtual block) with mode classification/disable logic and maintenance/GC data handling flows taught in Colella.
A person of ordinary skill would have been motivated to make this combination because Luo and Tanpairoj are both directed to the same problem of dynamically managing SLC cache resources based on logical saturation to balance performance and effective capacity/overprovisioning in NAND systems. Colella provides the practical implementation details (cursor-based allocation, explicit write booster mode enable/disable signaling, virtual blocks, and integration with maintenance operations) that are commonly used in modern SSD controllers to realize such dynamic SLC policies without excessive fragmentation or dummy data overhead. Combining these teachings yields a predictable improvement: a saturation-triggered disable/reallocation mechanism that uses a cursor for booster writes, performs clean maintenance before reallocation, and switches to normal multi-bit storage, within the skill of an ordinary artisan in SSD firmware design.
Thus, the combination of Luo, Tanpairoj and Colella would render obvious
wherein a block of memory cells of the memory system is allocated to a write booster cursor; disable operation of a write booster mode of the memory system based at least in part on determining that the quantity of data satisfies the first threshold value; and allocate the block of memory cells of the write booster cursor to store data based at least in part on disabling the operation of the write booster mode.
Regarding claim(s) 2, 12 and 22, the combination of Luo, Tanpairoj and Colella further teaches receive, after disabling the operation of the write booster mode, a write command to write data using the write booster mode; and determine whether the quantity of data stored to the memory system satisfies a second threshold value based at least in part on receiving the write command associated with the write booster mode (
Colella discloses a memory system configured to receive write commands and classify data as either write booster data or non-write booster data. Colella further teaches that the system can detect when a write booster signal/mode is disabled. When the write booster mode is disabled, incoming data is classified as non-write booster data and is directed to a normal virtual block rather than a write booster cursor. (Colella, claim 3; [0035], [0042], [0055] – describing classification of data type as write booster or non-write booster, detection that the write booster signal is disabled, and routing to a normal virtual block.)
Tanpairoj discloses a memory device that uses a behavior profile containing rules for SLC cache usage. The profile can specify conditions under which the SLC cache should be bypassed. The device monitors logical saturation (LBA usage) and applies the rules in the profile to determine SLC cache behavior. (Tanpairoj, claim 6; [0066]–[0070] – describing behavior profiles with rules based on logical saturation thresholds and conditions for writing to or bypassing the SLC cache.)
Luo discloses a memory controller that tracks logical saturation of the memory device over time (including maximum logical saturation) and uses this information to dynamically adjust SLC cache resources. (Luo, claim 1; Abstract; [0025]–[0030] – describing tracking of maximum logical saturation and reallocating SLC cache resources based on the saturation level.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Colella’s system, which already handles the situation where write booster mode is disabled and routes writes accordingly, by incorporating Tanpairoj’s teaching of using a behavior profile with rules conditioned on logical saturation levels to decide whether to enable or bypass SLC/write booster resources. A person of ordinary skill would have been further motivated to use Luo’s technique of monitoring and reacting to logical saturation levels to implement a second, lower threshold for re-enabling write booster resources after they have been disabled. This combination would allow the system to avoid immediately re-enabling the write booster mode after a high-saturation condition while still providing a mechanism to re-enable it when saturation drops to an acceptable level. The combination yields the predictable result of a hysteresis-based control mechanism for write booster mode that is common in SSD firmware design for balancing performance and capacity).
Regarding claim(s) 3, 13 and 23, the combination of Luo, Tanpairoj and Colella further teaches allocate a second block of memory cells to a second write booster cursor based at least in part on determining that the quantity of data stored to the memory system satisfies the second threshold value, wherein the write booster mode is enabled based at least in part on allocating the second block of memory cells to the second write booster cursor; and write, using the write booster mode, the data to the second block of memory cells based at least in part on allocating the second block of memory cells to the second write booster cursor (Colella discloses allocating or selecting a write booster virtual block (cursor) for writes classified as write booster data and programming data to that cursor using SLC mode. Colella also teaches that the system can switch between using a write booster cursor and a normal virtual block depending on the classification of the data or the state of the write booster mode. (Colella, claim 3; [0035], [0040]–[0042] – describing selection of an SLC virtual block / write booster cursor for write booster data and programming data to the cursor.)
Tanpairoj discloses dynamically adjusting the configuration of the SLC cache (including allocating or reconfiguring memory cells for SLC cache use) based on rules in a behavior profile that are triggered by logical saturation levels. When conditions in the profile are satisfied, the system can increase or adjust the SLC cache resources. (Tanpairoj, claim 1; [0066]–[0070] – describing reconfiguration of memory cells into an SLC cache pool based on saturation thresholds and profile rules.)
Luo discloses dynamically reallocating memory cells/blocks into SLC cache resources (from static SLC to dynamic SLC, or by adjusting sizes) based on the current logical saturation of the device. (Luo, claim 1; [0025]–[0035] – describing reallocation of blocks into SLC cache storage based on maximum logical saturation.)
It would have been obvious to one of ordinary skill in the art to modify Colella’s system for selecting and using a write booster cursor when appropriate by incorporating Tanpairoj’s and Luo’s teachings of dynamically allocating or reconfiguring SLC resources (including allocating new blocks for SLC use) when logical saturation drops below a threshold. A skilled artisan would have been motivated to allocate a new write booster cursor (second block) and re-enable write booster mode only when the monitored logical saturation satisfies a second, lower threshold because this provides hysteresis that prevents rapid oscillation between enabling and disabling the write booster mode. Such hysteresis techniques were well known and routinely used in cache and performance feature management in storage systems to improve stability and user experience. The combination of Colella’s cursor allocation mechanism with Tanpairoj’s and Luo’s saturation-based dynamic SLC resource adjustment produces no more than predictable results).
Regarding claim(s) 4, 14 and 24, the combination of Luo, Tanpairoj and Colella further teaches write the data to a third block of memory cells without using the write booster mode based at least in part on determining that the quantity of data stored to the memory system fails to satisfy the second threshold value (Colella discloses a memory system that supports a write booster mode in which data is written using SLC configuration to a write booster virtual block (referred to as an open cursor). Colella further teaches that data may be classified as write booster data or non-write booster data. When the write booster signal/mode is disabled, or when data is classified as non-write booster data, the system routes the write to a normal virtual block instead of the write booster cursor. (Colella, claim 3; [0035], [0042], [0055] – describing classification of data type, selection of SLC virtual block for write booster data, and use of normal virtual block when write booster is disabled.)
Tanpairoj discloses that a memory device may include a behavior profile containing rules for SLC cache usage, including conditions under which the SLC cache may be bypassed so that data is written directly to the MLC storage pool. (Tanpairoj, claim 6; [0067].)
Luo discloses monitoring logical saturation of the memory device and adjusting SLC cache resources based on the level of saturation. (Luo, claim 1; Abstract.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Colella’s system for handling write booster versus normal writes (via cursor selection and mode classification) by incorporating Tanpairoj’s teaching of bypassing the SLC cache and writing directly to MLC storage under certain conditions, and Luo’s teaching of making such decisions based on logical saturation levels. A person of ordinary skill would have been motivated to do so in order to improve capacity utilization and performance consistency when the drive reaches higher levels of logical saturation, which is a known design goal in SSD firmware (as recognized by both Luo and Tanpairoj). The combination yields no more than predictable results).
Regarding claim(s) 5, 15 and 25, the combination of Luo, Tanpairoj and Colella further teaches perform, by the memory system, a maintenance operation, wherein allocating the block of memory cells for storing data at the memory system is based at least in part on performing the maintenance operation (Colella discloses performing maintenance operations such as garbage collection and cache synchronization, during which the system aggregates and relocates data associated with a write booster cursor or buffer before writing to blocks. (Colella, Abstract; claims 3–4; [0048]–[0052] – describing initiation of operations to transfer write buffer data during memory management operations including GC and cache sync, and aggregation/movement of data.)
Luo discloses reallocating blocks from a static SLC cache pool to a dynamic SLC cache pool as part of memory management when logical saturation increases. (Luo, claim 1; [0025]–[0030].)
Tanpairoj discloses reconfiguring memory cells from an SLC cache pool to an MLC storage pool as part of memory management operations when saturation thresholds are exceeded. (Tanpairoj, claim 1; [0066]–[0070].)
It would have been obvious to combine these teachings because performing maintenance (data relocation, GC, or reconfiguration) before making a former SLC/write booster block available for normal storage use was a well-known technique to maintain data integrity and optimize capacity).
Regarding claim(s) 8 and 18, the combination of Luo, Tanpairoj and Colella further teaches designate the block of memory cells as a source block for the maintenance operation based at least in part on determining the quantity of data stored to the memory system satisfies the first threshold value; and defragment the block of memory cells based at least in part on designating the block of memory cells as the source block, wherein defragmenting the block of memory cells comprises transferring data stored to the block of memory cells to a fourth block of memory cells, wherein disabling the operation of the write booster cursor is based at least in part on defragmenting the block of memory cells (Colella discloses selecting a source block for garbage collection/maintenance operations based on data classification (write booster vs. normal) and transferring/aggregating valid data from that source block. (Colella, claims 3–4; [0048]–[0052].)
Luo discloses designating and reallocating blocks from SLC usage when logical saturation increases. (Luo, claim 1.)
It would have been obvious to use a defragmentation-style data transfer (as a form of maintenance) before disabling the write booster cursor and reallocating the block, as this was a conventional technique for reclaiming blocks while preserving data, as suggested by Colella’s GC data movement combined with Luo’s saturation-based block reallocation).
Regarding claim(s) 9 and 19, the combination of Luo, Tanpairoj and Colella further teaches wherein memory cells of the block of memory cells are each configured to store a single bit of data based at least in part on being allocated for the write booster cursor and are each configured to store multiple bits of data based at least in part on being allocated for storing data (Colella discloses that write booster data is written in SLC mode (single bit per cell) to an SLC virtual block/cursor, while non-write booster (normal) data uses normal virtual blocks. (Colella, [0035], [0042], claim 3.)
Colella explicitly describes writing single-bit in write booster mode to an SLC cursor/virtual block vs. normal multi-level operation, as shown in, [0080], the memory system may program the write buffer data into an open write booster cursor (e.g., an SLC cursor). In some other examples, user data and garbage collection valid data may be aggregated in the write buffer when the data size does not reach (e.g., satisfy) the threshold; [0085], the memory system may program the data stored in the write buffer (data associated with one or more write commands) to an open cursor, such as a TLC cursor for non-write booster operations
Tanpairoj discloses dynamically reconfiguring memory cells between an SLC cache pool (single-level) and an MLC storage pool (multiple bits per cell) based on a behavior profile and saturation conditions. (Tanpairoj, claim 1; [0066]–[0070].)
Luo discloses using blocks in static SLC mode versus dynamic mode (which can support multi-level operation) and reallocating between them. (Luo, claim 1; [0027]–[0030].)
It would have been obvious to configure the cells of the block as single-bit when allocated to the write booster cursor and as multi-bit when reallocated for normal storage, as this was a known technique for dynamically balancing performance and capacity, as taught by Tanpairoj’s SLC-to-MLC reconfiguration and Colella’s distinction between write booster (SLC) and normal operation).
Regarding claim(s) 10 and 20, the combination of Luo, Tanpairoj and Colella further teaches wherein the block of memory cells comprises a virtual block (
Colella explicitly discloses the use of virtual blocks for both write booster operations and normal write operations, where a virtual block may comprise blocks from multiple planes or memory devices. (Colella, claims 3–4; [0040]–[0042])
Colella, [0077], the source block for garbage collection may be an SLC virtual block. If the data is classified as other data (e.g., normal data), the source block for garbage collection may be a different virtual block (e.g., an MLC virtual block, TLC virtual block, or QLC virtual block).
Claims 6-7 and 16 -17 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al. (US 2021/0011767; hereinafter Luo) in view of in view of Tanpairoj et al. (US 2022/0129168 A1; hereinafter Tanpairoj) and Colella et al. (US 2022/0374163 A1; hereinafter Colella), further in view of Hoei et al. (US20170249211; hereinafter Hoei).
Regarding claim(s) 6 and 16, Luo, Tanpairoj and Colella do not expressly teach parity information stored to one or more first pages, which is taught by Hoei (Hoei discloses that in a RAIN protection scheme, parity portions of RAIN stripes are stored in pages of the memory array, and that management of such stripes includes handling of the parity data stored within those pages. (Hoei, Abstract; [0014]–[0015], [0039] – describing parity portion of RAIN stripe stored in pages and management of RAIN protection.))
The combination of Luo, Tanpairoj, Colella and Hoei render obvious identify respective parity information stored to one or more first pages of the block of memory cells as allocated to the write booster cursor; transfer, from the one or more first pages of the block of memory cells, the respective parity information to one or more second pages of memory cells different than the one or more first pages of memory cells; and erase, based at least in part on transferring the respective parity information, the block of memory cells, wherein disabling the operation of the write booster cursor is based at least in part on erasing the block of memory cells allocated to the write booster cursor (Colella discloses operations on a write booster cursor/virtual block during maintenance, including moving or aggregating data associated with the cursor (Colella, [0048]–[0055].)
Hoei discloses that in a RAIN protection scheme, parity portions of RAIN stripes are stored in pages of the memory array, and that management of such stripes includes handling of the parity data stored within those pages. (Hoei, Abstract; [0014]–[0015], [0039] – describing parity portion of RAIN stripe stored in pages and management of RAIN protection.)
Luo and Tanpairoj, as noted above, disclose reallocation or reconfiguration of blocks/cells previously used for SLC caching when saturation conditions are met, after which the block becomes available for normal (multi-bit) storage.
It would have been obvious to one of ordinary skill in the art to modify Colella’s maintenance operations performed on a write booster cursor block (which include data movement) by incorporating Hoei’s teaching that RAIN parity resides in specific pages of blocks participating in stripes, such that the parity must be identified and relocated before the block can be erased and repurposed. A skilled artisan would have been motivated to do so to preserve data protection for active RAIN stripes while performing block reallocation or mode changes, which is a routine consideration in NAND systems employing RAID-like protection (as taught by Hoei). The combination of Colella’s cursor/maintenance framework with Hoei’s RAIN parity page storage and Luo/Tanpairoj’s saturation-triggered reallocation would have been obvious as it merely applies known techniques to achieve the predictable result of safely disabling a write booster cursor while maintaining stripe integrity).
Regarding claim(s) 7 and 17, the combination of Luo, Tanpairoj and Colella further teaches wherein the respective parity information is associated with a redundant array of independent NAND (RAIN) data protection scheme (Hoei explicitly discloses a redundant array of independent NAND (RAIN) protection scheme in which parity is generated and stored as part of stripes across the memory array. (Hoei, Abstract; claims; [0014]–[0015].) This limitation is therefore taught by Hoei).
Conclusion
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138
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