DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Specification
The specification is objected to because:
The Cross-Reference to Related Applications section in paragraph [0001] of the specification does not provide the status of U.S. application serial no. 18/521,574 (i.e., now U.S. Patent No. U.S. PN: 12,321,613).
Drawings
The formal drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,321,613.
Claim 1 is rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,321,613. Although the conflicting claims are not identical, they are not patentably distinct from each other because the claimed invention of the instant Application is broader in scope, which encompasses the claimed limitations included in the reference patent. The U.S. reference Patent No. 12,321,613, which is narrower in scope, recites additional limitations, as shown in the table below. Therefore, it would have been obvious to a one ordinary skill in the art before the effective date of the invention was made to incorporate all the limitations in the instant Application as anticipated by the claims of U.S. reference Patent No. 12,321,613.
Independent claims 8 and 15 of the instant application have corresponding issues with the independent claims 8 and 15 of Patent No. 12,321,613 are also rejected under non-statutory obviousness-type double patenting for the same rationales discussed above.
Other parallel dependent claims of the instant application have corresponding issues with the dependent claims of U.S. patent no. 12,321,613 are also rejected non-statutory obviousness-type double patenting
“A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Humans are a species of the animal genus. Our case law firmly establishes that a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim. In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 1053, 29 USPQ2d 2010, 2016(Fed. Cir. 1993); In re Gosteli, 872 F.2d 1008, 1010, 10 USPQ2d 1614, 1616(Fed. Cir. 1989); Titanium Metals Corp. v. Banner, 778 F.2d 775,782, 227 USPQ 773,779 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d at 944, 214 USPQ at 767 (C.C.P.A. 1982)." ELI LILLY AND COMPANY v BARB LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
For illustration, only independent claims of the instant application are compared with the independent claims of the '613 application in the following table.
Instant Application No. 19/205,817
U.S. Patent No. 12,321,613
1.A method comprising: decoding a first plurality of codewords using a first set of bit flipping thresholds, wherein the first set of bit flipping thresholds are more likely to cause the bit flipping decoding to flip bits than a second set of bit flipping thresholds;
determining a first minimum number of iterations of bit flipping decoding performed on the first plurality of codewords to achieve a first target decoding rate; flipping bits in a codeword using the first set of bit flipping thresholds for the first minimum number of iterations; and flipping bits in the codeword using the second set of bit flipping thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.
1. A method comprising: decoding a first plurality of codewords using a first set of bit flipping thresholds; determining a first minimum number of iterations of bit flipping decoding performed on the first plurality of codewords to achieve a first target decoding rate; decoding a second plurality of codewords using a second set of bit flipping thresholds, wherein the first set of bit flipping thresholds are more likely to cause the bit flipping decoding to flip bits than the second set of bit flipping thresholds; determining a second minimum number of iterations of bit flipping decoding performed on the second plurality of codewords to achieve a second target decoding rate; flipping bits in a codeword using the first set of bit flipping thresholds for the first minimum number of iterations; determining the codeword remains undecoded as a result of the first minimum number of iterations; and flipping bits in the codeword using the second set of bit flipping thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.
8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
decode a first plurality of codewords using a first set of bit flipping thresholds, wherein the first set of bit flipping thresholds are more likely to cause the bit flipping decoding to flip bits than a second set of bit flipping thresholds; determine a first minimum number of iterations of bit flipping decoding performed on the first plurality of codewords to achieve a first target decoding rate;
flip bits in a codeword using the first set of bit flipping thresholds for the first minimum number of iterations; and flip bits in the codeword using the second set of bit flipping thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.
8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: decode a first plurality of codewords using a first set of bit flipping thresholds; determine a first minimum number of iterations of bit flipping decoding performed on the first plurality of codewords to achieve a first target decoding rate; decode a second plurality of codewords using a second set of bit flipping thresholds, wherein the first set of bit flipping thresholds are more likely to cause the bit flipping decoding to flip bits than the second set of bit flipping thresholds; determine a second minimum number of iterations of bit flipping decoding performed on the second plurality of codewords to achieve a second target decoding rate;
flip bits in a codeword using the first set of bit flipping thresholds for the first minimum number of iterations; determine the codeword remains undecoded as a result of the first minimum number of iterations; and flip bits in the codeword using the second set of bit flipping thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.
15. A system comprising: memory device; and a processing device, operatively coupled with the memory device, to:
decode a first plurality of codewords using a first set of bit flipping thresholds; decoding a second plurality of codewords using a second set of bit flipping thresholds, wherein the first set of bit flipping thresholds are more likely to cause the bit flipping decoding to flip bits than a second set of bit flipping thresholds;
determine a first minimum number of iterations of bit flipping decoding performed on the first plurality of codewords to achieve a first target decoding rate; flip bits in a codeword using the first set of bit flipping thresholds for the first minimum number of iterations; and Flip bits in the codeword using the second set of bit flipping thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.
15. A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to:
decode a first plurality of codewords using a first set of bit flipping thresholds; determine a first minimum number of iterations of bit flipping decoding performed on the first plurality of codewords to achieve a first target decoding rate; decode a second plurality of codewords using a second set of bit flipping thresholds, wherein the first set of bit flipping thresholds are more likely to cause the bit flipping decoding to flip bits than the second set of bit flipping thresholds;
determine a best decoding rate for the decoding of the second plurality of codewords; and set a second target decoding rate to a value within a threshold difference of the best decoding rate; determine a second minimum number of iterations of bit flipping decoding performed on the second plurality of codewords to achieve the second
target decoding rate; flip bits in a codeword using the first set of bit flipping thresholds for the first minimum number of iterations; determine the codeword remains undecoded as a result of the first minimum number of iterations; and flip bits in the codeword using the second set of bit flipping thresholds in response to determining the codeword remains undecoded as a result of
the first minimum number of iterations.
Allowable Subject Matter
Claims 1-20 would be allowable if the applicant files Terminal Disclaimer to overcome the rejection(s) under obvious-type non-statutory double patenting, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen (U.S. PN: 11,196,446) describes the first decoding may employ a list-based polar code decoding algorithm, and wherein bit-flipping the portion of information bits of the output bits may comprise: if the size of the list employed in the first decoding reaches a threshold and the first decoding fails, bit-flipping a portion of information bits of the output bits. The bit-flipping and the second decoding are performed for a plurality of rounds until the decoding times reach a predetermined threshold or second decoding succeeds, where in each round, the bit-flipping is performed for a different set of bits to obtain different additional frozen bits; and utilizing the different additional frozen bits and the pre-processed data to perform the second decoding. In a further embodiment, the first decoding employs a polar code decoding algorithm based on a first list size, and the method may further comprise: in response to decoding times of second decoding reaching the predetermined threshold and failing of the decoding, performing a fourth decoding of the pre-processed data with a second list size larger than the first list size.
Tseng (U.S. PN: 9,543,983) describes a decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: sending a read command sequence for reading multiple memory cells so as to obtain multiple first bits; determining whether the first bits have a first error; if the first bits have the first error, executing a first iteration decoding procedure on the first bits so as to obtain multiple second bits, and recording first bit flipping information of the first decoding procedure; determining whether the second bits have a second error; and If the second bits have the at least one second error, executing a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain multiple third bits
Zhang (2016/0335160) describe decoding data read from a memory. Coded data may be stored in a buffer. A parity check syndrome vector may be calculated by a bit flip module, based on the coded data and based on a parity matrix. The parity check syndrome vector may include unsatisfied bits. The parity check syndrome vector may be stored in the buffer. The bit flip module may calculate a speculated bit flip threshold based on a feature of the parity matrix. The bit flip module may determine, based on the parity check syndrome vector, several unsatisfied parity checks participated in by a particular bit of the coded data. The bit flip module may flip the particular bit in response to the number of unsatisfied parities checks for the particular bit being greater than or equal to the speculated bit flip threshold.
Wu et al. (U.S. PN: 9,292,394) teach an indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type. A third adjusted threshold associated with the page type is generated, including by: determining a first number of flipped bits using a first adjusted threshold associated with the page type, determining a second number of flipped bits using a second adjusted threshold associated with the page type, and generating the third adjusted threshold using the first number of flipped bits and the second number of flipped bits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
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