Prosecution Insights
Last updated: October 02, 2026
Application No. 19/205,855

ELECTRONIC APPARATUS

Non-Final OA §103
Filed
May 12, 2025
Priority
May 20, 2024 — JP 2024-082128
Examiner
REHMAN, MOHAMMED H
Art Unit
Tech Center
Assignee
Kyocera Document Solutions Inc.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
610 granted / 731 resolved
+23.4% vs TC avg
Strong +18% interview lift
Without
With
+18.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
18 currently pending
Career history
748
Total Applications
across all art units

Statute-Specific Performance

§101
4.0%
-36.0% vs TC avg
§103
58.7%
+18.7% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 731 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION 1. The office acknowledges the receipt of the following and placed of record in the file: Application dated 5/12/2024 claimed priority of date 5/20/24. 2. Claims 1-4 are presented for examination. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 4. Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP-2020-026473 (“JP-473”) as provided in form 1449. Regarding Claim 1, JP-473 teaches an electronic apparatus, comprising: a non-volatile memory device that comprises a first memory area and a second memory area [Para: 0041(flash ROM memory 112 contains write protected area and write accessible area)]; a falsification detecting unit [Para: 0013(falsification detection unit 140)] configured to read a bootcode from the first memory area and determine whether the read bootcode is falsified or not [Para: 0018(a sub-processor CPU 115 that “reads … from flash MFP100 … of verifying the validity” to determine “whether or not the boot program has been corrupted” where the MFP100 is in the flash ROM 112(see para: 0017) and falsification is performed by 140, see 0057)]; and a bootcode rewriting unit configured to rewrite a bootcode in the a second memory with the bootcode in the first memory area if it is determined that the read bootcode is not falsified [Para: 0053 – 0061, (as sub-CPU 115 acquire in a memory a hash value stored in write protected area during version update (0053) and calculate a new hash as “calculate a hash value of the normally used boot data 420 by using encryption key and comparing the hash value” in the memory space (0057-0061))] and the bootcode in the first memory area and the bootcode in the second bootcode are not identical to each other [Para: 0061 (when “determined that the boot program has been tampered with”)]. JP-473 does not disclose expressly rewrite a bootcode in the second memory area with the bootcode in the first memory area (of a partitioned memory). JP-473 teaches a flash ROM memory (112) comprises write protected area and write accessible area [Para: 0041] where write accessible area is configured to update with boot data update history [Para: 0052(at storage area 501)]. One of ordinary skill in the art would modify JP-473’s teachings of a partitioned memory with a rewriteable memory area to rewrite a bootcode in the second memory area with the bootcode in the first memory area (for comparison) for the purpose of validating a boot code in a secure environment without corrupting the system and to protect alteration of boot data at the time factory shipment [JP-473, Para: 0005]. Regarding Claim 2, JP-473 teaches wherein if it is determined that the bootcode read from the first memory area is falsified, the falsification detecting unit reads the bootcode in the second memory area and determines whether the bootcode read from the second memory area is falsified or not [Para: 0061(“boot program has been tampered with …”)]; and if it is determined that the bootcode read from the second memory area is not falsified, the bootcode rewriting unit acquires a newest bootcode and rewrites the bootcode in the first memory area with the acquired bootcode [Para: 0053 – 0061, (as sub-CPU 115 acquire in a memory a hash value stored in write protected area during version update (0053) and calculate a new hash as “calculate a hash value of the normally used boot data 420 by using encryption key and comparing the hash value” in the memory space (0057-0061))]. Regarding Claim 3, JP-473 teaches wherein if it is determined that the bootcode read from the second memory area is not falsified, the bootcode rewriting unit acquires the newest bootcode and a hash value of the newest bootcode and rewrites the bootcode and a hash value in the first memory area with the newest bootcode and the hash value of the newest bootcode [Para: 0053(a new hash value is added “each time version update is performed”)]; if it is determined that the bootcode read from the first memory area is not falsified and the bootcode in the first memory area and the bootcode in the second memory area are not identical to each other, the bootcode rewriting unit rewrites the bootcode and the hash value in the second memory area with the bootcode and the hash value in the first memory area [Para: 0059, (as sub-CPU 115 acquire in a memory a hash value stored in write protected area during version update (0053) and calculate a new hash)]; and the falsification detecting unit (a) acquires a hash value of both the bootcode and the hash value of the bootcode in the first memory area and writes the acquired hash value as falsification detection information into the first memory area and determines whether the bootcode read from the first memory area is falsified or not on the basis of the falsification detection information, and (b) determines whether the bootcode read from the second memory area is falsified or not on the basis of falsification detection information in the second memory area [Para: 0053 – 0061, (as sub-CPU 115 acquire in a memory a hash value stored in write protected area during version update (0053) and calculate a new hash as “calculate a hash value of the normally used boot data 420 by using encryption key and comparing the hash value” in the memory space (0057-0061))]. Regarding Claim 4, JP-473 wherein when the bootcode rewriting unit rewrites the bootcode and the hash value in the second memory area with the bootcode and the hash value in the first memory area, the falsification detecting unit generates certification information unique to this electronic apparatus and stores the certification information into the second memory area, and writes as the falsification detection information to the second memory area a hash value of all the bootcode, the hash value of the bootcode and the certification information in the second memory area [Para: 0061(as setting “boot falsification detection flag”) and 0064]; and when the falsification detecting unit reads the bootcode from the second memory area, the falsification detecting unit also reads the falsification detection information and the certification information from the second memory area, and determines whether the bootcode read from the second memory area is falsified or not on the basis of the read falsification detection information, and if the read certification information is different from the generated certification information, the falsification detecting unit determines that the memory device has been replaced fraudulently and stops a starting process performed in accordance with the bootcode [Para: 0066-0068]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176
Read full office action

Prosecution Timeline

May 12, 2025
Application Filed
Sep 21, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12748477
MULTI-BATTERY ELECTRONIC DEVICE AND PROTECTION METHOD THEREOF
2y 3m to grant Granted Sep 29, 2026
Patent 12739139
SLEEP AND WAKEUP SIGNALING FOR ETHERNET
2y 8m to grant Granted Sep 15, 2026
Patent 12705152
METHODS AND APPARATUS TO MANAGE ENDPOINT PERFORMANCE
4y 10m to grant Granted Aug 11, 2026
Patent 12704895
POWER GRID ALLOCATION IN EXTENDED REALITY (XR) DEVICES
2y 7m to grant Granted Aug 11, 2026
Patent 12705066
SYSTEMS AND METHODS FOR CONFIGURING A SYSTEM-ON-CHIP DURING BOOT OF AN INFORMATION HANDLING SYSTEM
2y 2m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+18.5%)
2y 10m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 731 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month