DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
The disclosure is objected to under 37 CFR 1.71, as being so incomprehensible as to preclude a reasonable search of the prior art by the examiner. For example, the following items are not understood:
Abstract, and [0005] recite "the at least one cascade control module being connected to a cascade control signal" is incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
[0010] recites "the cascade control signal, by controlling switch states of the plurality of cascade control modules, adjusts a position at which the transmission of the turn-on potential of the scan signal to the next-stage register input terminal is cut off during one frame of display" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
[0015] recited "a gate of the second transistor being connected to a corresponding one of the second cascade control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
[0018] recites "the cascade control signal further includes: a plurality of third cascade control signals respectively corresponding to the plurality of cascade control modules" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
[0019] recites "a gate of the third transistor being connected to a corresponding one of the third cascade control signals" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
[0045] recites "a cascade control signal connected to the first-side first scan driving circuit… a cascade control signal connected to the second-side first scan driving circuit" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
[113] recites "with the control terminal of the cascade control module 20 being connected to the cascade control signal SJL" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
[0130] recites "Fig. 5…the cascade control signal SJL includes: a first cascade control signal SW1, where the plurality of cascade control modules 20 are connected to the same first cascade control signal SW1" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Applicant is required to submit an amendment which clarifies the disclosure so that the examiner may make a proper comparison of the invention with the prior art.
Applicant should be careful not to introduce any new matter into the disclosure (i.e., matter which is not supported by the disclosure as originally filed).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Independent claim 1, lines 8-9 recite term "the at least one cascade control module being connected to a cascade control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 2, lines 1-2 recites " wherein the at least one cascade control module comprises a plurality of cascade control modules" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 2 lines 7-10 recites "the cascade control signal, by controlling switch states of the plurality of cascade control modules, adjusts a position at which the transmission of the turn-on potential of the scan signal to the next-stage register input terminal is cut off during one frame of display" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 3 lines 1-4 recites " wherein the cascade control signal comprises: a first cascade control signal; and each of the plurality of cascade control modules comprises: a first transistor," incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 3 lines 7-8 recites "a gate of the first transistor is connected to the first cascade control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 4 line 1-4 recites "wherein the cascade control signal comprise: a plurality of second cascade control signals respectively corresponding to the plurality of cascade control modules" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 4 lines 6-7 recites "a gate of the second transistor being connected to a corresponding one of the plurality of second cascade control signals" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 4 lines 19-20 recites "a plurality of third cascade control signals respectively corresponding to the plurality of cascade control modules" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 4 lines 21-23 recites "a gate of the third transistor being connected to a corresponding one of the plurality of third cascade control signals" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 5 lines 4-5 recites "wherein a control terminal of each of the at least one auxiliary cut-off module is connected to a switch control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 5 lines 6-7 recites " an input terminal of each of the at least one auxiliary cut-off module is connected to an auxiliary cut-off signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 5 lines 14-15 recites "the plurality of auxiliary cut-off modules being connected to the same switch control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
The dependent claims 6-7 rejected for depending upon a rejected base claim 5.
Claim 8 lines 4-5 recites "a gate of the first transistor is connected to the first cascade control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 8 line 10 recites "a gate of the fourth transistor is connected to the switch control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 8 lines 10-11 recites " a first electrode of the fourth transistor is connected to the auxiliary cut-off signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Dependent claims 9-11 rejected for depending upon a rejected base claim 1.
Claim 12 lines 4-5 recites " the at least one split- screen control module are connected to the same split-screen control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 13 lines 1-2 recites "a cascade control signal connected to the first-side first scan driving circuit… a cascade control signal connected to the second-side first scan driving circuit" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim 13 line 3 recites " a cascade control signal connected to the second-side first scan driving circuit" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Dependent claims 14-17 rejected for depending upon a rejected base claim 11.
Independent Claims 18 lines 8-9 recite term "the at least one cascade control module being connected to a cascade control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
The dependent claim 19 rejected for depending upon a rejected base claim 18.
Independent Claims 20 lines 11-12 recite term "the at least one cascade control module being connected to a cascade control signal" incomprehensive and indefinite subject matter so that examiner cannot interpret this limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, 8-10 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 2021/0193048).
As to claim 1, Lim teaches a display driver circuit (100, 530, 540, Figs 1, 7), at least one first scan driving circuit ( scan drivers 100, 530, 540, Figs 1, 7, ¶44, ¶95),
a plurality of first shift registers (110, 130, ¶45, Fig 1) arranged in cascade (111 to 117, ¶45), each of the plurality of first shift registers comprising a register input terminal and a register output terminal, wherein the plurality of first shift registers are configured to output a plurality of scan signals (ISS1 to ISSN, ¶45, Fig 1); and
at least one cascade control module (transistors MST1 to MSTN, ¶44), the at least one cascade control module (MST1) being connected between a current-stage register output terminal (111, Fig 1) and a next-stage register input terminal (131, Fig 1), and the at least one cascade control module (MST1, MST2, see ¶64) being connected to a cascade control signal (MSS, see ¶64), where the at least one cascade control module, in response to the cascade control signal, controls transmission of turn-on potential of the scan signal from the current-stage register output terminal to the next-stage register input terminal (See ¶65), so as to implement multi-frequency display of a display panel in a first direction (Par. 6 and Fig 9 explained a scan driver and a display device capable of performing multi-frequency driving (MFD) in a first direction).
As to claim 2, Lim teaches the display driver circuit according to claim 1, wherein the at least one cascade control module comprises a plurality of cascade control modules, the plurality of cascade control modules being arranged respectively corresponding to at least part of the plurality of first shift registers in the at least one first scan driving circuit, and each of the plurality of cascade control modules being arranged between a corresponding current-stage first shift register and a corresponding next-stage first shift register in the at least part of the plurality of first shift registers; and the cascade control signal, by controlling switch states of the plurality of cascade control modules, adjusts a position at which the transmission of the turn-on potential of the scan signal to the next-stage register input terminal is cut off during one frame of display. (See ¶109, ¶114, and Fig 9).
As to claim 3, Lim teaches the display driver circuit according to claim 1, wherein the cascade control signal comprises: a first cascade control signal; and each of the plurality of cascade control modules comprises: a first transistor, wherein a first electrode of the first transistor is electrically connected to a corresponding current-stage register output terminal, and a second electrode of the first transistor is electrically connected to a corresponding next-stage register input terminal; and a gate of the first transistor is connected to the first cascade control signal, wherein turn-off time of the at least one cascade control module during one frame of display is determined based on potential jump time of the first cascade control signal during the one frame of display, thereby determining a partition position for reduced-frequency display of the display panel in the first direction. (See at least ¶ 112 to ¶114).
As to claim 5, Lim teaches the display driver circuit according to claim 1, wherein the at least one first scan driving circuit further comprises: at least one auxiliary cut-off module (SWT1 to SWT2, ¶90, Fig 6), the at least one auxiliary cut-off module being arranged corresponding to the at least one cascade control module (the transistors MST1 to MSTN, ¶44, Fig 6), wherein a control terminal of each of the at least one auxiliary cut-off module is connected to a switch control signal, an input terminal of each of the at least one auxiliary cut-off module is connected to an auxiliary cut-off signal, and an output terminal of each of the at least one auxiliary cut-off module is connected to the same register input terminal as one of the plurality of cascade control modules corresponding to the at least one auxiliary cut-off module (See ¶91, Fig 6), wherein the at least one auxiliary cut-off module comprises a plurality of auxiliary cut-off modules, and the at least one cascade control module comprises a plurality of cascade control modules, the plurality of auxiliary cut-off modules being arranged respectively corresponding to the plurality of cascade control modules, and the plurality of auxiliary cut-off modules being connected to the same switch control signal (See ¶92, Fig 6), wherein on time of the plurality of auxiliary cut-off modules during one frame of display is determined based on potential jump time of the switch control signal during the one frame of display (See ¶92, Fig 6).
As to claim 6, Lim teaches the display driver circuit according to claim 5, wherein the current-stage first shift register and the next-stage first shift register are respectively an ith-stage first shift register and an (i+a)th-stage first shift register, where i and a are both positive integers (See ¶19, ¶45), wherein in a case where the ith-stage first shift register outputs turn-on potential of an ith-stage scan signal and the (i+a)th-stage first shift register outputs turn-on potential of an (i+a)th stage scan signal, during a phase when the ith-stage first shift register outputs the turn-on potential of the ith-stage scan signal, the cascade control signal controls one of the plurality of cascade control modules between the ith-stage first shift register and the (i+a)th-stage first shift register to be turned on, and the switch control signal controls one of the at least one auxiliary cut-off module between the ith-stage first shift register and the (i+a)th-stage first shift register to be turned off (See ¶65-¶67); and
in a case where the ith-stage first shift register outputs the turn-on potential of the ith-stage scan signal and the (i+a)th-stage first shift register outputs cutoff potential of the (i+a)th-stage scan signal, during the phase when the ith-stage first shift register outputs the turn-on potential of the ith-stage scan signal, the cascade control signal controls the one of the plurality of cascade control modules between the ith-stage first shift register and the (i+a)th-stage first shift register to be turned off, and the switch control signal controls the one of the at least one auxiliary cut-off module between the ith-stage first shift register and the (i+a)th-stage first shift register to be turned on (See ¶65-¶67).
As to claim 8, Lim teaches display driver circuit according to claim 5, wherein the cascade control signal comprises: a first cascade control signal (MSS, Fig 6); and each of the at least one cascade control module comprises: a first transistor (a transistor MST1, Fig 6), wherein a gate of the first transistor is connected to the first cascade control signal (MSS), a first electrode of the first transistor is electrically connected to a corresponding current-stage register output terminal (111), and a second electrode of the first transistor is electrically connected to a corresponding next-stage register input terminal (131);
each of the at least one auxiliary cut-off module comprises: a fourth transistor (SWT1, Fig 6), wherein a gate of the fourth transistor is connected to the switch control signal (/MSS), a first electrode of the fourth transistor is connected to the auxiliary cut-off signal (off volage of VGH), and a second electrode of the fourth transistor (SWT2) is electrically connected to a corresponding next-stage register input terminal (112), wherein the first transistor has the same channel type as that of the fourth transistor (the same p-type channel), and the first cascade control signal has an opposite phase to that of the switch control signal (/MSS and MSS, ¶74), and the first cascade control signal is reused as the switch control signal (/MSS, ¶77), and the first cascade control signal is reused as the auxiliary cut-off signal (MSS, ¶78).
As to claim 9, Lim teaches the display driver circuit according to claim 1, further comprising: a plurality of pixel driver circuits and a plurality of first scan lines, wherein the plurality of pixel driver circuits are arranged in an array, and each row of the plurality of pixel driver circuits is electrically connected to at least one of the plurality of first scan lines; and the register output terminal in the at least one first scan driving circuit is electrically connected to one of the plurality of first scan lines (See ¶25), wherein each of the plurality of pixel driver circuits (Fig 8, ¶97-¶99) comprises: a driving module (PXT1), a data writing module (PXT2), a threshold compensation module (PXT3), and a light emission control module (PXT5, PXT6), wherein the driving module(PXT1) is connected between the light emission control module (PXT5) and a light-emitting device (EL), and the driving module (the drive transistor PXT1) is configured to generate a driving current; the data writing module (PXT2) is electrically connected to a first terminal of the driving module (PXT1), and the data writing module (PXT2) is configured to transmit a data voltage (DS) to the driving module (PXT1); the threshold compensation module (PXT3) is connected between a control terminal and a second terminal of the driving module (PXT1), and the threshold compensation module (PXT3) is configured to compensate for a threshold voltage of the driving module (PXT1); and one of the plurality of first scan lines (SS) is electrically connected to a control terminal of the threshold compensation module (PXT3) in a corresponding row of the plurality of pixel driver circuits (530),
a first reset module (PXT4) electrically connected to the control terminal of the driving module (PXT1), the first reset module (PXT4) being configured to reset the control terminal of the driving module (PXT1); each of the plurality of second scan lines (SI/ISS, Fig 8 ) being electrically connected to a control terminal of the first reset module (PXT4) in a corresponding row of the plurality of pixel driver circuits, wherein the register output terminals (534, Fig 7) in the at least one first scan driving circuit are electrically connected to the plurality of second scan lines (SI/ISS, Fig 7), wherein one of the plurality of second scan lines (SI/ISS, Fig 7) connected to a jth row of the plurality of pixel driver circuits is electrically connected to a jth-stage register output terminal (534, Fig 7), and one of the plurality of first scan lines (SS, Fig 7, ¶102) connected to the jth row of the plurality of pixel driver circuits is electrically connected to a (j+b)th-stage register output terminal (534, Fig 7, ¶102), where j and b are both positive integers (¶15).
As to claim 10, Lim teaches the display driver circuit according to claim 9, wherein each of the plurality of pixel driver circuits (pixel circuits PX(s), see ¶97-¶99, Fig. 8) further comprises: a first reset module electrically connected to the control terminal of the driving module, the first reset module (first initializing transistor PXT4, ¶98, Fig 4) being configured to reset the control terminal of the driving module (PXT5, PXT6); a plurality of second scan lines (SI, ISS, Fig 8) , each of the plurality of second scan (SI, Fig 8) lines being electrically connected to a control terminal of the first reset module (PXT4, Fig 8) in a corresponding row of the plurality of pixel driver circuits (530, 540, Fig 7), wherein the register output terminals (131, Fig 6) in the at least one first scan driving circuit are electrically connected to the plurality of second scan lines (SS1 to SSN), wherein one of the plurality of second scan lines (SS1 to SSN) connected to a jth row of the plurality of pixel driver circuits (530, 540) is electrically connected to a jth-stage register output terminal (131), and one of the plurality of first scan lines (SS1 to SSN) connected to the jth row of the plurality of pixel driver circuits (530) is electrically connected to a (j+b)th-stage register output terminal (131), where j and b are both positive integers (See ¶15).
As to claim 18, Lim teaches a control method for a display driver circuit, which is used to control the display driver circuit (scan drivers 100, 530, 540, Figs 1, 7, ¶44, ¶95), at least one first scan driving circuit ( scan drivers 100, 530, 540, Figs 1, 7, ¶44, ¶95); a plurality of first shift registers (110, 130, ¶45, Fig 1) arranged in cascade (111 to 117, ¶45), each of the plurality of first shift registers comprising a register input terminal and a register output terminal, wherein the plurality of first shift registers are configured to output a plurality of scan signals (ISS1 to ISSN, ¶45, Fig 1); and
at least one cascade control module (transistors MST1 to MSTN, ¶44), the at least one cascade control module (MST1) being connected between a current-stage register output terminal (111, Fig 1) and a next-stage register input terminal (131, Fig 1), and the at least one cascade control module (MST1, see ¶64) being connected to a cascade control signal (MSS, see ¶64), where the at least one cascade control module, in response to the cascade control signal, controls transmission of turn-on potential of the scan signal from the current-stage register output terminal to the next-stage register input terminal (See ¶65), so as to implement multi-frequency display of a display panel in a first direction (Par. 6 and Fig 9 explained a scan driver and a display device capable of performing multi-frequency driving (MFD) in a first direction);
obtaining a target partition position of a display panel in a first direction; and determining a cascade control signal during each frame of display based on the target partition position (See ¶27), and controlling a switch state of the cascade control module during each frame of display based on the cascade control signal (See ¶28).
As to claim 19, Lim teaches the control method for a display driver circuit according to claim 18, wherein the at least one cascade control module comprises a plurality of cascade control modules (the transistors MST1 to MSTN, ¶44); the display panel comprises at least one target partition position (See ¶27); and
a display process of the display panel comprises a plurality of types of display frames, the plurality of types of display frames comprise a first active frame and at least one type of second active frame, with the type of the at least one type of second active frame corresponding to the at least one target partition position, respectively, wherein in the first active frame, the cascade control signal controls all of the plurality of cascade control modules to remain turned on (See ¶73-¶74, Fig 4); and
in the second active frame, the cascade control signal controls turn-off time of all of the plurality of cascade control modules, or controls one of the plurality of cascade control modules at a preset position to be turned off, so that the display panel displays based on the target partition position corresponding to the second active frame (See ¶77-¶78, Fig 4).
As to claim 20, Lim teaches a display device (500, Fig 7, ¶94), a display driver circuit (100, 530, 540, Figs 1, 7), at least one first scan driving circuit (100, 530, 540, Figs 1, 7), a plurality of first shift registers (110, 130, ¶45, Fig 1) arranged in cascade (111 to 117, ¶45), each of the plurality of first shift registers comprising a register input terminal and a register output terminal, wherein the plurality of first shift registers are configured to output a plurality of scan signals (ISS1 to ISSN, ¶45, Fig 1); and
at least one cascade control module (transistors MST1 to MSTN, ¶44), the at least one cascade control module (MST1) being connected between a current-stage register output terminal (111, Fig 1) and a next-stage register input terminal (131, Fig 1), and the at least one cascade control module (MST1, see ¶64) being connected to a cascade control signal (MSS, see ¶64), where the at least one cascade control module, in response to the cascade control signal, controls transmission of turn-on potential of the scan signal from the current-stage register output terminal to the next-stage register input terminal (See ¶65), so as to implement multi-frequency display of a display panel in a first direction (Par. 6 and Fig 9 explained a scan driver and a display device capable of performing multi-frequency driving (MFD) in a first direction); and
a display panel (510, ¶96, Fig 7), wherein the display driver circuit is disposed in the display panel (See ¶25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lim as applied to claim 1 above, and further in view of Okumura (US 9,081,218).
As to claim 4, Lim teaches everything as applied to claim 2 above, except for "a first resistor string comprising a plurality of first resistors connected in series between the first power terminal and the second power terminal, with a plurality of first output terminals tapped from the first resistor string, and a second resistor string comprising a plurality of second resistors connected in series between the third power terminal and the fourth power terminal, with a plurality of second output terminals tapped from the second resistor string."
Okumura teaches a first resistor string comprising a plurality of first resistors (R11, R12, R13) connected in series between the first power terminal (VCC) and the second power terminal (ground), a second resistor string comprising a plurality of second resistors (R21, R22, R23) connected in series between the third power terminal (VCC) and the fourth power terminal (ground). See Okumura Col. 10, lines 38-55, Figs 1-2.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement a first resistor string comprising a plurality of first resistors (R11, R12, R13) connected in series between the first power terminal (VCC) and the second power terminal (ground), a second resistor string comprising a plurality of second resistors (R21, R22, R23) connected in series between the third power terminal (VCC) and the fourth power terminal (ground), as Okumura teaches, to modify the scan drivers of Lim . The motivation for doing so would improve a better quality of the image being displayed, while preventing the luminance unevenness from occurring in each display region.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lim as applied to claim 1 above, and further in view of Itoh (US 2020/0141850).
As to claim 7, Lim teaches everything as applied to claim 5 above, except for a first potential signal line and a second potential signal line, the first potential signal line being configured to provide a first potential signal to the plurality of first shift registers, and the second potential signal line being configured to provide a second potential signal to the plurality of first shift registers, wherein when the potential of the first potential signal is cutoff potential, the first potential signal is reused as the auxiliary cut-off signal; and when the potential of the second potential signal is the cutoff potential, the second potential signal is reused as the auxiliary cut-off signal.
Itoh teaches voltage regulated power supply 11 including first voltage line and second voltage line supply first voltage signal and second voltage signal to first gate driver SDF and second gate driver GDS. (Itoh Figure 8 and ¶105). Each of the transistors S1 through S3 is turned ON or OFF in accordance with a signal from the LSI. FIG. 5 illustrates patterns (patterns 1 through 8) of combinations of ON and OFF of the transistors S1 through S3. See ¶100, ¶119. Transistor S1 is turned OFF interpreted the first voltage signal is reused as the auxiliary cut-off signal, Transistor S2 is turned OFF interpreted the second voltage signal is reused as the auxiliary cut-off signal.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the voltage regulated power supply 11 including first voltage line and second voltage line supply first voltage signal and second voltage signal to first gate driver SDF and second gate driver GDS. Each of the transistors S1 through S3 is turned ON or OFF in accordance with a signal from the LSI. FIG. 5 illustrates patterns (patterns 1 through 8) of combinations of ON and OFF of the transistors S1 through S3, as Itoh teaches, to modify the display device of Lim. The motivation for doing so would reduce a difference in luminance between the regions. (Itoh ¶ 4 ).
Claim(s) 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lim as applied to claim 1 above, and in view of Liu et al. (US 2021/0350733) cited in the IDS.
As to claim 11, Lim teaches everything as applied to claim 9 above, except for "the first-side first scan driving circuit and the second-side first scan driving circuit being respectively disposed on two sides of the plurality of pixel driver circuits; at least one split-screen control module, the at least one split-screen control module comprising a plurality of split-screen switch units, wherein the plurality of split-screen switch units are arranged respectively corresponding to the at least part of the plurality of first scan lines; each of the plurality of split-screen switch units is connected between two adjacent sub-scan lines in the same one of the plurality of first scan lines; and when each of the plurality of split-screen switch units is turned off in response to a split-screen control signal, the first-side first scan driving circuit and the second-side first scan driving circuit respectively transmit scan signals to sub-scan lines on both sides of the plurality of split-screen switch units."
Liu teaches a first gate driving circuit 01_D and a second gate driving circuit 01_E are disposed on the left and right sides of the active display area 100, in the first gate driving circuit 01_D, a signal output end of each level of shift register SR in each first driving group (driving group 11_A), in the second gate driving circuit 01_E, a signal output end of each level of shift register SR in each first driving group (driving group 11_A). (See Liu ¶146-¶148, Fig 11). Liu further teaches [0144] In addition, when the connection controller 12_B disconnects the connection path between the driving group 11_A and the driving group 11_B and the connection controller 12_C disconnects the connection path between the driving group 11_B and the driving group 11_C, a start signal STV provides a high voltage for the driving group 11_A, to enable the driving group 11_A to control the display subarea A to perform displaying independently. [0145] It should be noted that either of the split-screen gating signal STV_d_B and the split-screen gating signal STV_d_C is the foregoing split-screen gating signal STV_d. For ease of description, the split-screen gating signals STV_d are differentiated by using letters such as “B” and “C” based on different locations at which the split-screen gating signals STV_d are received in the gate driving circuit 01. [0146] In addition, in the example for description of FIG. 7b or FIG. 8, the gate driving circuit 01 is located on one side of the active display area 10. To facilitate narrow-bezel design of the display panel 10 of the mobile terminal, as shown in FIG. 11, a first gate driving circuit 01_D and a second gate driving circuit 01_E may be respectively disposed on the left and right (or upper and lower) sides of the active display area 100.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the split-screen controllers 12_B and the second slit-screen controller 12_C are electrically connected between the first gate driving circuit 01_D and the second gate driving circuit 01_E are disposed on the left and right sides of the active display area 100, as Liu teaches, to modify the display device of Lim. The motivation for doing so would control the display subarea connected to the sub driving group to independently display an image. (See Liu ¶ 6).
As to claim 12, Liu teaches the display driver circuit according to claim 11, wherein at the same moment, the number of the plurality of split-screen switch units on the same one of the plurality of first scan lines that are in an off state is less than or equal to one; and the plurality of split-screen switch units in the same one of the at least one split- screen control module are connected to the same split-screen control signal. (See Liu ¶189).
As to claim 13, Liu teaches the display driver circuit according to claim 12, wherein a cascade control signal connected to the first-side first scan driving circuit is a first-side cascade control signal, and a cascade control signal connected to the second-side first scan driving circuit is a second-side cascade control signal, the first-side cascade control signal being different from the second-side cascade control signal. (See Liu ¶146-¶148, Fig 11).
As to claim 14, Liu teaches the display driver circuit according to claim 11, wherein when turn-on potential of scan signals is simultaneously transmitted on two sub-scan lines respectively connected to both ends of one split-screen switch unit among the plurality of split-screen switch units, the split-screen control signal controls the one split-screen switch unit among the plurality of split-screen switch units to be turned on. (See Liu ¶146-¶148, Fig 11).
As to claim 15, Liu teaches the display driver circuit according to claim 11, wherein each of the at least part of the plurality of first scan lines comprises a first sub-scan line and a second sub-scan line, the first sub-scan line being connected to the first-side first scan driving circuit, and the second sub-scan line being connected to the second-side first scan driving circuit; and each of the plurality of split-screen switch units is separately electrically connected to a corresponding first sub-scan line and second sub-scan line. (See Liu ¶146-¶148, Fig 11).
As to claim 16, Liu teaches the display driver circuit according to claim 11, wherein each of the at least part of the plurality of first scan lines comprises a third sub-scan line, a fourth sub-scan line, and a fifth sub-scan line (see ¶125, ¶140, ¶193); and the at least one split-screen control module comprises: a first split-screen control module and a second split-screen control module, wherein the third sub-scan line is connected to the first-side first scan driving circuit, the first split-screen control module is connected between the third sub-scan line and the fourth sub-scan line, the second split-screen control module is connected between the fourth sub-scan line and the fifth sub-scan line, and the fifth sub-scan line is connected to the second-side first scan driving circuit (See Liu ¶146-¶148, Fig 11);
wherein within the same display frame, during a data writing process of part of the rows of the plurality of pixel driver circuits, the first split-screen control module is turned on and the second split-screen control module is turned off, and during a data writing process of other rows of the plurality of pixel driver circuits, the first split-screen control module is turned off and the second split-screen control module is turned on, (See Liu ¶73);
wherein the split-screen control signal comprises a first split-screen control signal and a second split-screen control signal, the first split-screen control module being connected to the first split-screen control signal, and the second split-screen control module being connected to the second split-screen control signal; and a transistor in one of the plurality of split-screen switch units in the first split-screen control module has a different channel type from that of a transistor in one of the plurality of split-screen switch units in the second split-screen control module, and the first split-screen control signal is reused as the second split-screen control signal. (See Liu ¶161, Fig 10).
As to claim 17, Liu teaches the display driver circuit according to claim 11, wherein each of the plurality of split-screen switch units comprises: a fifth transistor, wherein a gate of the fifth transistor is connected to the split-screen control signal, and a first electrode of the fifth transistor and a second electrode of the fifth transistor are respectively connected to two adjacent sub-scan lines in the same one of the plurality of first scan lines (See ¶156-¶161, Figs 9AB).
Conclusion
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KEVIN M NGUYEN
Patent Examiner, Art Unit 2628
/Kevin M Nguyen/Primary Examiner, Art Unit 2628 Telephone: (571) 272-7697
Email: kevin.nguyen2@uspto.gov