DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/10/26 has been entered.
Response to Amendment
This Office action is in response to the amendments to specification and the amendments to the claims filed on 8/10/2026 are entered. Claims 1, 4-5, 12-13, 16-18, 20 have been amended. Claims 2-3, 8 are canceled. Therefore, claims 1, 4-7, 9-20 are currently pending. The amendments do not overcome the 112(b) rejections due to the technical errors (See par. 3-11 below).
Response to Arguments
With respect to the specification objections and the 112(b) rejections, applicant’s arguments based on the technical errors claims 1, lines 6-8 recited “wherein the at least one cascade control module is connected between a current-stage register output terminal and a next-stage register input terminal is connected to a cascade control signal” (emphasis) have been considered but are directed toward newly amended or newly added claims and are believed to be answered by and are therefore moot in view of the new grounds of rejection (Updated) presented below.
More specifically, in electrical engineering, electrical connections are the physical joining between conductors (e.g., a terminal, a wire, a line, an electrode…) and electronic components (e.g., a transistor, a register input terminal, a register output terminal, a scan driving circuit…) to create signal, voltage, current, or data. This allows electrical current (e.g., signal) to flow smoothly among different electronic components in the circuitry. Therefore, regarding to the technical errors, the Applicant is required to change “…is connected to a cascade control signal” to --is connected to a cascade control line—
Applicant's arguments, based on the prior art rejection, filed 5/17/2026 have been fully considered but they are not persuasive.
With respect to the amened claim 1, the Applicant alleged (pages 19-20) that Lim fails to disclose or suggest limitation “at least one cascade control module, wherein the at least one cascade control module is connected between a current-stage register output terminal and a next-stage register input terminal and is connected to a cascade control signal.” (Emphasis).
These arguments are not persuasive because the term “is connected to a cascade control signal” has the technical error. The circuitry does not work. In the circuitry, an electronic component (e.g., one cascade control module) is impossible connected to a signal (e.g., a cascade control signal).
Applicant’s arguments with respect to claim(s) 1, 4-7, 9-20 have been considered but are moot because the new ground of rejection (See Par. 13-17 below) does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent unamended claim 1, 18, 20 (previously), lines 6-8 recite limitation “wherein the at least one cascade control module is connected between a current-stage register output terminal and a next-stage register input terminal is connected to a cascade control signal” (Emphasis). The term “is connected to a cascade control signal” renders the claim indefinite. The circuitry does not work. In the circuitry, an electronic component (e.g., a next-stage register input terminal) is impossible connected to a signal (e.g., a cascade control signal).
Dependent claims rejected for depending upon a rejected base claims.
Claim limitation “at least one cascade control module” AND “at least one auxiliary cut-off module” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Specification [0030] the cascade control module includes a first transistor. Specification [0152] each auxiliary cut-off module 30 includes a fourth transistor T4. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 4-7 and 9-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent amended claims 1, 18, 20 (Updated) lines 8-9 recite term “wherein the at least one cascade control module is configured to a cascade control line for transmitting a cascade control signal, where the at least one cascade control module" as being incomprehensive and new subject matter.
The dependent claims are rejected for depending upon a rejected base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, 8-10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al US2021/0193048 in view of Chung US 2011/0187691.
As to amended claims 1, 18 and 20 (Updated), Lim teaches in Figures 6, 7, 9, 10 and ¶90-¶117 comprising: the at least one first scan driving circuit comprises: a plurality of first shift registers arranged in cascade, each of the plurality of first shift registers comprising a register input terminal and a register output terminal, wherein the plurality of first shift registers are configured to output a plurality of scan signals; and at least one cascade control module, wherein the at least one cascade control module is connected between a current-stage register output terminal and a next-stage register input terminal and is connected to a cascade control signal, wherein the at least one cascade control module is configured to a cascade control line for transmitting a cascade control signal, where the at least one cascade control module, in response to the cascade control signal, control transmission of turn-on potential of the scan signal from the current-stage register output terminal to the next-stage register input terminal.
( [0090] a scan driver 400 according to some example embodiments may include a plurality of first stages 110, a plurality of masking transistors MST1 through MSTN, a plurality of second stages 130, and a plurality of switching transistors SWT1 through SWTN.
[0091] The plurality of switching transistors SWT1 through SWTN may transfer a gate off voltage VGH (e.g., a high gate voltage) to a plurality of input terminals of the plurality of second stages 130 in response to an inverted masking signal /MSS that is an inversion signal of a masking signal MSS. In some example embodiments, each of the plurality of switching transistors SWT1 through SWTN may include a gate for receiving the inverted masking signal /MSS, a first terminal for receiving the gate off voltage VGH, and a second terminal connected to a corresponding one of the plurality of input terminals of the plurality of second stages 130.
[0092] When the masking signal MSS has an on level, and the inverted masking signal /MSS has an off level, a plurality of intermediate scan signals ISS1 through ISSN may be transferred through the plurality of masking transistors MST1 through MSTN to the input terminals of the plurality of second stages 130. Alternatively, when the masking signal MSS has the off level, and the inverted masking signal /MSS has the on level, the gate off voltage VGH may be transferred through the plurality of switching transistors SWT1 through SWTN to the input terminals of the plurality of second stages 130. )
Lim teaches implementing multi-frequency display of a display panel in a first direction; adjusts a position at which the transmission of the turn-on potential of the scan signal to the next-stage register input terminal is cut off during one frame of display.
( [0006] and Fig 9 for a scan driver and a display device capable of performing multi-frequency driving (MFD) in a first direction ).
Lim teaches adjusting a position at which the transmission of the turn-on potential of the scan signal to the next-stage register input terminal is cut off during one frame of display.
( [0090] Referring to FIG. 6, a scan driver 400 according to some example embodiments may include a plurality of first stages 110, a plurality of masking transistors MST1 through MSTN, a plurality of second stages 130, and a plurality of switching transistors SWT1 through SWTN. The scan driver 400 of FIG. 6 may have a configuration and an operation substantially the same as those of a scan driver 100 of FIG. 1, except that the scan driver 400 of FIG. 6 may further include the plurality of switching transistors SWT1 through SWTN.
[0091] The plurality of switching transistors SWT1 through SWTN may transfer a gate off voltage VGH (e.g., a high gate voltage) to a plurality of input terminals of the plurality of second stages 130 in response to an inverted masking signal /MSS that is an inversion signal of a masking signal MSS.
[0092] When the masking signal MSS has an on level, and the inverted masking signal /MSS has an off level, a plurality of intermediate scan signals ISS1 through ISSN may be transferred through the plurality of masking transistors MST1 through MSTN to the input terminals of the plurality of second stages 130. Alternatively, when the masking signal MSS has the off level, and the inverted masking signal /MSS has the on level, the gate off voltage VGH may be transferred through the plurality of switching transistors SWT1 through SWTN to the input terminals of the plurality of second stages 130.
[0114] The scan driver control block 580 may generate the masking signal MSS based on the plurality of driving frequencies for the plurality of panel regions. In some example embodiments, the scan driver control block 580 may set at least a portion of one or more frame periods as a hold period, may change the masking signal MSS to an off level before one horizontal time from a start time point of the hold period, and may change the masking signal to an on level before one horizontal time from an end time point of the hold period.
[0115] For example, as illustrated in FIGS. 7, 9 and 10, the plurality of first stages 532 may sequentially generate the plurality of intermediate scan signals ISS1 through ISS6 in each frame period FP1 through FP4. The scan driver control block 580 may set at least a portion of one or more frame periods FP2 and FP3 as the hold period HP according to the plurality of driving frequencies DF1, DF2 and DF3 for the plurality of panel regions PZ1, PZ2 and PZ3. For example, adjusting a position at which the transmission of the turn-on potential of the scan signal to the next-stage register input terminal is cut off during one frame of display in a case of the second driving frequency DF2 for the second panel region PZ2 is the low frequency of about 20 Hz, two frame periods FP2 and FP3 from among three frame periods FP1, FP2 and FP3 may include the hold period HP in a partial period in which the third and fourth scan signals SS3 and SS4 are provided to the second panel region PZ2. Further, the scan driver control block 580 may change the masking signal MSS to the off level before one horizontal time from the start time point of the hold period HP, and may change the masking signal MSS to the on level before one horizontal time from the end time point of the hold period HP. In response to this masking signal MSS, the plurality of masking transistors MST may transfer first through sixth intermediate scan signals ISS1 through ISS6 to the plurality of second stages 534 in a first frame period FP1, and may transfer only the first, second, fifth and sixth intermediate scan signals ISS1, ISS2, ISS5 and ISS6 to the plurality of second stages 534 while not transferring the third and fourth intermediate scan signals ISS3 and ISS4 in each of second and third frame periods FP2 and FP3.
[0116] Accordingly, the plurality of second stages 534 may provide the first through sixth scan signals SS1 through SS6 to the first through third panel regions PZ1, PZ2 and PZ3 in the first frame period FP1, and may provide only the first, second, fifth and sixth scan signals SS1, SS2, SS5 and SS6 to the first and third panel regions PZ1 and PZ3 while not providing the third and fourth scan signals SS3 and SS4 to the second panel region PZ2 in each of second and third frame periods FP2 and FP3. Further, the controller 550 may provide the first through third panel region data PD1, PD2 and PD3 for the first through third panel regions PZ1, PZ2 and PZ3 to the data driver 520 in the first frame period FP1, and may provide only the first and third panel region data PD1 and PD3 for the first and third panel regions PZ1 and PZ3 to the data driver 520 while not providing the second panel region data PD2 for the second panel region PZ2 to the data driver 520 in each of second and third frame periods FP2 and FP3. Accordingly, the first and third panel regions PZ1 and PZ3 may be driven at the normal driving frequency of about 60 Hz, and the second panel region PZ2 may be driven at the low frequency of about 20 Hz.
[0117] As described above, in the display device 500 according to some example embodiments, the plurality of first stages 532 may sequentially output the plurality of intermediate scan signals ISS, the plurality of masking transistors MST may selectively transfer the plurality of intermediate scan signals ISS in response to the masking signal MSS, respectively, and the plurality of second stages 534 may selectively output the plurality of scan signals SS based on the plurality of intermediate scan signals ISS selectively transferred by the plurality of masking transistors MST. Accordingly, the display device 500 according to some example embodiments may perform the multi-frequency driving that drives the plurality of panel regions PZ1, PZ2 and PZ3 at different driving frequencies DF1, DF2 and DF3. )
Lim fails to teach the at least one first scan driving circuit comprises: a plurality of first shift registers arranged in cascade, each of the plurality of first shift registers comprising a register input terminal and a register output terminal, wherein the plurality of first shift registers are configured to output a plurality of scan signals; and at least one cascade control module, wherein the at least one cascade control module is connected between a current-stage register output terminal and a next-stage register input terminal and is connected to a cascade control signal, wherein the at least one cascade control module is configured to a cascade control line for transmitting a cascade control signal, where the at least one cascade control module, in response to the cascade control signal, control transmission of turn-on potential of the scan signal from the current-stage register output terminal to the next-stage register input terminal.
Chung teaches in Figure 1, 11, 12 and ¶52, ¶163-¶177, comprising: the at least one first scan driving circuit comprises: a plurality of first shift registers arranged in cascade, each of the plurality of first shift registers comprising a register input terminal and a register output terminal, wherein the plurality of first shift registers are configured to output a plurality of scan signals; and at least one cascade control module, wherein the at least one cascade control module is connected between a current-stage register output terminal and a next-stage register input terminal and is connected to a cascade control signal, wherein the at least one cascade control module is configured to a cascade control line for transmitting a cascade control signal, where the at least one cascade control module, in response to the cascade control signal, control transmission of turn-on potential of the scan signal from the current-stage register output terminal to the next-stage register input terminal ( [0174] A difference between the scan drivers of FIGS. 1 and 12 is that the plurality of input signal select circuits 1 through n-1 of the scan driver in FIG. 12 each include transistors having different channel types. For example, first transistors Tr1-3 through Tr(n-1)-3 are PMOS transistors, and second transistors Tr1-4 through Tr(n-1)-4 are NMOS transistors.
[0175] When the input signal select circuits 1 through n-1 are configured as described above, a first mode signal PROG and a second mode signal INTER may have the same logic level value. Also, the first mode signal PROG and the second mode signal INTER are not separately applied, but a common mode signal MODE is applied from one signal line so as to control switching operations of the first transistors Tr1-3 through Tr(n-1)-3 and the second transistors Tr1-4 through Tr(n-1)-4. In a progressive scanning method, the common mode signal MODE is at a low level; and in an interlaced scanning method, the common mode signal MODE is at a high level. )
wherein the at least one cascade control module comprises a plurality of cascade control modules, the plurality of cascade control modules being arranged respectively corresponding to at least part of the plurality of first shift registers in the at least one first scan driving circuit, and each of the plurality of cascade control modules being arranged between a corresponding current-stage first shift register and a corresponding next-stage first shift register in the at least part of the plurality of first shift registers, and the cascade control signal, by controlling switch states of the plurality of cascade control modules, wherein the cascade control signal comprises a plurality of second cascade
control signals respectively corresponding to the plurality of cascade control modules, and each of the plurality of cascade control modules comprises a second transistor, a gate of the second transistor being connected to a corresponding one of a plurality of second cascade control lines, and the second transistor being connected between a corresponding current-stage register output terminal and a corresponding next-stage register input terminal. ( [0174] A difference between the scan drivers of FIGS. 1 and 12 is that the plurality of input signal select circuits 1 through n-1 of the scan driver in FIG. 12 each include transistors having different channel types. For example, first transistors Tr1-3 through Tr(n-1)-3 are PMOS transistors, and second transistors Tr1-4 through Tr(n-1)-4 are NMOS transistors. [0175] When the input signal select circuits 1 through n-1 are configured as described above, a first mode signal PROG and a second mode signal INTER may have the same logic level value. Also, the first mode signal PROG and the second mode signal INTER are not separately applied, but a common mode signal MODE is applied from one signal line so as to control switching operations of the first transistors Tr1-3 through Tr(n-1)-3 and the second transistors Tr1-4 through Tr(n-1)-4. In a progressive scanning method, the common mode signal MODE is at a low level; and in an interlaced scanning method, the common mode signal MODE is at a high level. )
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the scan driver taught by Chung, to modify the scan driver of Lim such that the masking signal MSS based on the plurality of driving frequencies for the plurality of panel regions. In some example embodiments, the scan driver control block 580 may set at least a portion of one or more frame periods as a hold period, may change the masking signal MSS to an off level before one horizontal time from a start time point of the hold period, and may change the masking signal to an on level before one horizontal time from an end time point of the hold period. The motivation for doing so would have been to reduce the power consumption of the display device, a low frequency driving technique, which drives or refreshes a display panel at a frequency lower than a normal driving frequency. (Lim ¶ 3).
As to claim 5, Lim and Chung teach everything applied to claim 1, wherein the at least one first scan driving circuit further comprises: at least one auxiliary cut-off module (SWT1 to SWT2, ¶90, Lim Fig 6), the at least one auxiliary cut-off module being arranged corresponding to the at least one cascade control module (the transistors MST1 to MSTN, ¶44, Fig 6), wherein a control terminal of each of the at least one auxiliary cut-off module is connected to a switch control signal, an input terminal of each of the at least one auxiliary cut-off module is connected to an auxiliary cut-off signal, and an output terminal of each of the at least one auxiliary cut-off module is connected to the same register input terminal as one of the plurality of cascade control modules corresponding to the at least one auxiliary cut-off module (See ¶91, Fig 6), wherein the at least one auxiliary cut-off module comprises a plurality of auxiliary cut-off modules, and the at least one cascade control module comprises a plurality of cascade control modules, the plurality of auxiliary cut-off modules being arranged respectively corresponding to the plurality of cascade control modules, and the plurality of auxiliary cut-off modules being connected to the same switch control signal (See ¶92, Fig 6), wherein on time of the plurality of auxiliary cut-off modules during one frame of display is determined based on potential jump time of the switch control signal during the one frame of display (See ¶92, Fig 6).
As to claim 6, Lim and Chung teach everything applied to claim 5, wherein the current-stage first shift register and the next-stage first shift register are respectively an ith-stage first shift register and an (i+a)th-stage first shift register, where i and a are both positive integers (See Lim ¶19, ¶45), wherein in a case where the ith-stage first shift register outputs turn-on potential of an ith-stage scan signal and the (i+a)th-stage first shift register outputs turn-on potential of an (i+a)th stage scan signal, during a phase when the ith-stage first shift register outputs the turn-on potential of the ith-stage scan signal, the cascade control signal controls one of the plurality of cascade control modules between the ith-stage first shift register and the (i+a)th-stage first shift register to be turned on, and the switch control signal controls one of the at least one auxiliary cut-off module between the ith-stage first shift register and the (i+a)th-stage first shift register to be turned off (See ¶65-¶67); and
in a case where the ith-stage first shift register outputs the turn-on potential of the ith-stage scan signal and the (i+a)th-stage first shift register outputs cutoff potential of the (i+a)th-stage scan signal, during the phase when the ith-stage first shift register outputs the turn-on potential of the ith-stage scan signal, the cascade control signal controls the one of the plurality of cascade control modules between the ith-stage first shift register and the (i+a)th-stage first shift register to be turned off, and the switch control signal controls the one of the at least one auxiliary cut-off module between the ith-stage first shift register and the (i+a)th-stage first shift register to be turned on (See ¶65-¶67).
As to claim 9, Lim and Chung teach everything applied to claim 1, wherein each of the plurality of pixel driver circuits (Lim Fig 8, ¶97-¶99) comprises: a driving module (PXT1), a data writing module (PXT2), a threshold compensation module (PXT3), and a light emission control module (PXT5, PXT6), wherein the driving module(PXT1) is connected between the light emission control module (PXT5) and a light-emitting device (EL), and the driving module (the drive transistor PXT1) is configured to generate a driving current; the data writing module (PXT2) is electrically connected to a first terminal of the driving module (PXT1), and the data writing module (PXT2) is configured to transmit a data voltage (DS) to the driving module (PXT1); the threshold compensation module (PXT3) is connected between a control terminal and a second terminal of the driving module (PXT1), and the threshold compensation module (PXT3) is configured to compensate for a threshold voltage of the driving module (PXT1); and one of the plurality of first scan lines (SS) is electrically connected to a control terminal of the threshold compensation module (PXT3) in a corresponding row of the plurality of pixel driver circuits (530),
a first reset module (PXT4) electrically connected to the control terminal of the driving module (PXT1), the first reset module (PXT4) being configured to reset the control terminal of the driving module (PXT1); each of the plurality of second scan lines (SI/ISS, Fig 8 ) being electrically connected to a control terminal of the first reset module (PXT4) in a corresponding row of the plurality of pixel driver circuits, wherein the register output terminals (534, Fig 7) in the at least one first scan driving circuit are electrically connected to the plurality of second scan lines (SI/ISS, Fig 7), wherein one of the plurality of second scan lines (SI/ISS, Fig 7) connected to a jth row of the plurality of pixel driver circuits is electrically connected to a jth-stage register output terminal (534, Fig 7), and one of the plurality of first scan lines (SS, Fig 7, ¶102) connected to the jth row of the plurality of pixel driver circuits is electrically connected to a (j+b)th-stage register output terminal (534, Fig 7, ¶102), where j and b are both positive integers (¶15).
As to claim 10, Lim and Chung teach everything applied to claim 9, wherein each of the plurality of pixel driver circuits (pixel circuits PX(s), see Lim ¶97-¶99, Fig. 8) further comprises: a first reset module electrically connected to the control terminal of the driving module, the first reset module (first initializing transistor PXT4, ¶98, Fig 4) being configured to reset the control terminal of the driving module (PXT5, PXT6); a plurality of second scan lines (SI, ISS, Fig 8) , each of the plurality of second scan (SI, Fig 8) lines being electrically connected to a control terminal of the first reset module (PXT4, Fig 8) in a corresponding row of the plurality of pixel driver circuits (530, 540, Fig 7), wherein the register output terminals (131, Fig 6) in the at least one first scan driving circuit are electrically connected to the plurality of second scan lines (SS1 to SSN), wherein one of the plurality of second scan lines (SS1 to SSN) connected to a jth row of the plurality of pixel driver circuits (530, 540) is electrically connected to a jth-stage register output terminal (131), and one of the plurality of first scan lines (SS1 to SSN) connected to the jth row of the plurality of pixel driver circuits (530) is electrically connected to a (j+b)th-stage register output terminal (131), where j and b are both positive integers (See ¶15).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lim and Chung as applied to claim 1 above, and further in view of Okumura (US 9,081,218).
As to claim 4, Lim and Chung teach everything to claim 2 above, except for "a first resistor string comprising a plurality of first resistors connected in series between the first power terminal and the second power terminal, with a plurality of first output terminals tapped from the first resistor string, and a second resistor string comprising a plurality of second resistors connected in series between the third power terminal and the fourth power terminal, with a plurality of second output terminals tapped from the second resistor string."
Okumura teaches a first resistor string comprising a plurality of first resistors (R11, R12, R13) connected in series between the first power terminal (VCC) and the second power terminal (ground), a second resistor string comprising a plurality of second resistors (R21, R22, R23) connected in series between the third power terminal (VCC) and the fourth power terminal (ground). See Okumura Col. 10, lines 38-55, Figs 1-2.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement a first resistor string comprising a plurality of first resistors (R11, R12, R13) connected in series between the first power terminal (VCC) and the second power terminal (ground), a second resistor string comprising a plurality of second resistors (R21, R22, R23) connected in series between the third power terminal (VCC) and the fourth power terminal (ground), as Okumura teaches, to modify the scan drivers of Lim and Chung. The motivation for doing so would improve a better quality of the image being displayed, while preventing the luminance unevenness from occurring in each display region.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lim and Chung as applied to claim 1 above, and further in view of Itoh (US 2010/0141850).
As to claim 7, Lim and Chung teach everything to claim 5 above, except for a first potential signal line and a second potential signal line, the first potential signal line being configured to provide a first potential signal to the plurality of first shift registers, and the second potential signal line being configured to provide a second potential signal to the plurality of first shift registers, wherein when the potential of the first potential signal is cutoff potential, the first potential signal is reused as the auxiliary cut-off signal; and when the potential of the second potential signal is the cutoff potential, the second potential signal is reused as the auxiliary cut-off signal.
Itoh teaches voltage regulated power supply 11 including first voltage line and second voltage line supply first voltage signal and second voltage signal to first gate driver SDF and second gate driver GDS. (Itoh Figure 8 and ¶105). Each of the transistors S1 through S3 is turned ON or OFF in accordance with a signal from the LSI. FIG. 5 illustrates patterns (patterns 1 through 8) of combinations of ON and OFF of the transistors S1 through S3. See ¶100, ¶119. Transistor S1 is turned OFF interpreted the first voltage signal is reused as the auxiliary cut-off signal, Transistor S2 is turned OFF interpreted the second voltage signal is reused as the auxiliary cut-off signal.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the voltage regulated power supply 11 including first voltage line and second voltage line supply first voltage signal and second voltage signal to first gate driver SDF and second gate driver GDS. Each of the transistors S1 through S3 is turned ON or OFF in accordance with a signal from the LSI. FIG. 5 illustrates patterns (patterns 1 through 8) of combinations of ON and OFF of the transistors S1 through S3, as Itoh teaches, to modify the display device of Lim and Chung. The motivation for doing so would reduce a difference in luminance between the regions. (Itoh ¶ 4 ).
Claim(s) 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lim and Chung as applied to claim 1 above, and in view of Liu et al. (US 2021/0350733) cited in the IDS.
As to claim 11, Lim and Chung teach everything to claim 9 above, except for "the first-side first scan driving circuit and the second-side first scan driving circuit being respectively disposed on two sides of the plurality of pixel driver circuits; at least one split-screen control module, the at least one split-screen control module comprising a plurality of split-screen switch units, wherein the plurality of split-screen switch units are arranged respectively corresponding to the at least part of the plurality of first scan lines; each of the plurality of split-screen switch units is connected between two adjacent sub-scan lines in the same one of the plurality of first scan lines; and when each of the plurality of split-screen switch units is turned off in response to a split-screen control signal, the first-side first scan driving circuit and the second-side first scan driving circuit respectively transmit scan signals to sub-scan lines on both sides of the plurality of split-screen switch units."
Liu teaches a first gate driving circuit 01_D and a second gate driving circuit 01_E are disposed on the left and right sides of the active display area 100, in the first gate driving circuit 01_D, a signal output end of each level of shift register SR in each first driving group (driving group 11_A), in the second gate driving circuit 01_E, a signal output end of each level of shift register SR in each first driving group (driving group 11_A). (See Liu ¶146-¶148, Fig 11). Liu further teaches [0144] In addition, when the connection controller 12_B disconnects the connection path between the driving group 11_A and the driving group 11_B and the connection controller 12_C disconnects the connection path between the driving group 11_B and the driving group 11_C, a start signal STV provides a high voltage for the driving group 11_A, to enable the driving group 11_A to control the display subarea A to perform displaying independently. [0145] It should be noted that either of the split-screen gating signal STV_d_B and the split-screen gating signal STV_d_C is the foregoing split-screen gating signal STV_d. For ease of description, the split-screen gating signals STV_d are differentiated by using letters such as “B” and “C” based on different locations at which the split-screen gating signals STV_d are received in the gate driving circuit 01. [0146] In addition, in the example for description of FIG. 7b or FIG. 8, the gate driving circuit 01 is located on one side of the active display area 10. To facilitate narrow-bezel design of the display panel 10 of the mobile terminal, as shown in FIG. 11, a first gate driving circuit 01_D and a second gate driving circuit 01_E may be respectively disposed on the left and right (or upper and lower) sides of the active display area 100.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the split-screen controllers 12_B and the second slit-screen controller 12_C are electrically connected between the first gate driving circuit 01_D and the second gate driving circuit 01_E are disposed on the left and right sides of the active display area 100, as Liu teaches, to modify the display device of Lim and Chung. The motivation for doing so would control the display subarea connected to the sub driving group to independently display an image. (See Liu ¶ 6).
As to claim 12, Liu teaches the display driver circuit according to claim 11, wherein at the same moment, the number of the plurality of split-screen switch units on the same one of the plurality of first scan lines that are in an off state is less than or equal to one; and the plurality of split-screen switch units in the same one of the at least one split- screen control module are connected to the same split-screen control signal. (See Liu ¶189).
As to claim 13, Liu teaches the display driver circuit according to claim 12, wherein a cascade control signal connected to the first-side first scan driving circuit is a first-side cascade control signal, and a cascade control signal connected to the second-side first scan driving circuit is a second-side cascade control signal, the first-side cascade control signal being different from the second-side cascade control signal. (See Liu ¶146-¶148, Fig 11).
As to claim 14, Liu teaches the display driver circuit according to claim 11, wherein when turn-on potential of scan signals is simultaneously transmitted on two sub-scan lines respectively connected to both ends of one split-screen switch unit among the plurality of split-screen switch units, the split-screen control signal controls the one split-screen switch unit among the plurality of split-screen switch units to be turned on. (See Liu ¶146-¶148, Fig 11).
As to claim 15, Liu teaches the display driver circuit according to claim 11, wherein each of the at least part of the plurality of first scan lines comprises a first sub-scan line and a second sub-scan line, the first sub-scan line being connected to the first-side first scan driving circuit, and the second sub-scan line being connected to the second-side first scan driving circuit; and each of the plurality of split-screen switch units is separately electrically connected to a corresponding first sub-scan line and second sub-scan line. (See Liu ¶146-¶148, Fig 11).
As to claim 16, Liu teaches the display driver circuit according to claim 11, wherein each of the at least part of the plurality of first scan lines comprises a third sub-scan line, a fourth sub-scan line, and a fifth sub-scan line (see ¶125, ¶140, ¶193); and the at least one split-screen control module comprises: a first split-screen control module and a second split-screen control module, wherein the third sub-scan line is connected to the first-side first scan driving circuit, the first split-screen control module is connected between the third sub-scan line and the fourth sub-scan line, the second split-screen control module is connected between the fourth sub-scan line and the fifth sub-scan line, and the fifth sub-scan line is connected to the second-side first scan driving circuit (See Liu ¶146-¶148, Fig 11);
wherein within the same display frame, during a data writing process of part of the rows of the plurality of pixel driver circuits, the first split-screen control module is turned on and the second split-screen control module is turned off, and during a data writing process of other rows of the plurality of pixel driver circuits, the first split-screen control module is turned off and the second split-screen control module is turned on, (See Liu ¶73);
wherein the split-screen control signal comprises a first split-screen control signal and a second split-screen control signal, the first split-screen control module being connected to the first split-screen control signal, and the second split-screen control module being connected to the second split-screen control signal; and a transistor in one of the plurality of split-screen switch units in the first split-screen control module has a different channel type from that of a transistor in one of the plurality of split-screen switch units in the second split-screen control module, and the first split-screen control signal is reused as the second split-screen control signal. (See Liu ¶161, Fig 10).
As to claim 17, Liu teaches the display driver circuit according to claim 11, wherein each of the plurality of split-screen switch units comprises: a fifth transistor, wherein a gate of the fifth transistor is connected to the split-screen control signal, and a first electrode of the fifth transistor and a second electrode of the fifth transistor are respectively connected to two adjacent sub-scan lines in the same one of the plurality of first scan lines (See ¶156-¶161, Figs 9AB).
Conclusion
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/Kevin M Nguyen/Primary Examiner, Art Unit 2628 Telephone: (571) 272-7697
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